Nuvoton NuMicro series Product manual

ML51
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ML51 SERIES TECHNICAL REFERENCE MANUAL
1T 8051
8-bit Microcontroller
NuMicro®Family
ML51 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

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TABLE OF CONTENTS
1GENERAL DESCRIPTION.............................................................................12
2FEATURES....................................................................................................14
3PART INFORMATION ...................................................................................17
3.1 ML51 Series Selection Guide.................................................................................... 17
3.2 ML51 Series Selection Code ..................................................................................... 18
4PIN CONFIGURATION ..................................................................................19
4.1 Pin Configuration......................................................................................................... 19
4.1.1 ML51 Series Pin Diagram .............................................................................................19
4.1.2 ML51 Series Multi Function Pin Diagram ...................................................................24
4.2 Pin Description............................................................................................................. 29
5BLOCK DIAGRAM.........................................................................................37
5.1 ML51 FULL FUNCTION BLOCK............................................................................... 37
6MEMORY ORGANIZATION...........................................................................38
6.1 Program Memory......................................................................................................... 38
6.2 Data Memory................................................................................................................ 40
6.3 On-Chip XRAM ............................................................................................................ 43
6.4 Data Flash .................................................................................................................... 43
7SPECIAL FUNCTION REGISTER (SFR).......................................................44
7.1 SFR Page Selection.................................................................................................... 44
7.2 All SFR Description ..................................................................................................... 63
8GENERAL 80C51 SYSTEM CONTROL......................................................152
9I/O PORT STRUCTURE AND OPERATION................................................156
9.1 Quasi-Bidirectional Mode ......................................................................................... 156
9.2 Push-Pull Mode.......................................................................................................... 157
9.3 Input-Only Mode ........................................................................................................ 159
9.4 Open-Drain Mode...................................................................................................... 159
9.5 Read-Modify-Write Instructions............................................................................... 159
9.6 Control Registers of I/O Ports.................................................................................. 160
9.6.1 Input and Output Data Control....................................................................................160
9.6.2 GPIO Mode Control......................................................................................................163
9.6.3 GPIO Multi-Function Select ........................................................................................164
9.6.4 Input Type ......................................................................................................................166
9.6.5 Output Slew Rate Control ...........................................................................................167
9.6.6 Pull-Up Resister Control..............................................................................................168

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9.6.7 Pull-Down Resister Control.........................................................................................168
10TIMER/COUNTER 0 AND 1.........................................................................170
10.1 Mode 0 (13-Bit Timer) ......................................................................................... 174
10.2 Mode 1 (16-Bit Timer) ......................................................................................... 175
10.3 Mode 2 (8-Bit Auto-Reload Timer) .................................................................... 175
10.4 Mode 3 (Two Separate 8-Bit Timers)................................................................ 176
11TIMER 2 AND INPUT CAPTURE.................................................................178
11.1 Auto-Reload Mode............................................................................................... 182
11.2 Compare Mode .................................................................................................... 183
11.3 Input Capture Module ......................................................................................... 184
11.4 Control Registers of Timer2 ............................................................................... 185
12TIMER 3 .......................................................................................................189
13WATCHDOG TIMER (WDT) ........................................................................191
13.1 Time-Out Reset Timer......................................................................................... 193
13.2 General Purpose Timer....................................................................................... 194
14SELF WAKE-UP TIMER (WKT)...................................................................196
15SERIAL PORT (UART0 & UART1)..............................................................198
15.1 Mode 0 .................................................................................................................. 199
15.2 Mode 1 .................................................................................................................. 200
15.3 Mode 2 .................................................................................................................. 201
15.4 Mode 3 .................................................................................................................. 202
15.5 Baud Rate............................................................................................................. 202
15.6 Framing Error Detection ..................................................................................... 206
15.7 Multiprocessor Communication ......................................................................... 207
15.8 Automatic Address Recognition ........................................................................ 208
16SMART CARD INTERFACE (SC)................................................................216
16.1 Functional Description ........................................................................................ 216
16.2 Control Registers of SC Controller.................................................................... 217
16.3 Operating Modes ................................................................................................. 225
16.3.1Smart Card Mode .........................................................................................................225
16.3.2UART Mode...................................................................................................................227
16.4 Smart Card Data Transfer .................................................................................. 228
16.4.1Initial Character TS.......................................................................................................228
16.4.2Error Signal and Character Repetition ......................................................................229
16.4.3Block Guard Time and Extra Guard Time .................................................................229

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17SERIAL PERIPHERAL INTERFACE (SPI)..................................................231
17.1 Functional Description ........................................................................................ 231
17.2 SPI Protocol Registers........................................................................................ 234
17.3 Operating Modes ................................................................................................. 240
17.3.1Master Mode .................................................................................................................240
17.3.2Slave Mode....................................................................................................................240
17.4 Clock Formats and Data Transfer ..................................................................... 240
17.5 Slave Select Pin Configuration.......................................................................... 243
17.6 Mode Fault Detection.......................................................................................... 243
17.7 Write Collision Error ............................................................................................ 243
17.8 Overrun Error ....................................................................................................... 244
17.9 SPI Interrupt ......................................................................................................... 244
18INTER-INTEGRATED CIRCUIT (I2C)...........................................................245
18.1 Functional Description ........................................................................................ 245
18.1.1START and STOP Condition.......................................................................................246
18.1.27-Bit Address with Data Format..................................................................................247
18.1.3Acknowledge.................................................................................................................248
18.1.4Arbitration ......................................................................................................................249
18.1.5Operation Modes ..........................................................................................................250
18.1.6Slave mode....................................................................................................................254
18.1.7General Call ..................................................................................................................256
18.1.8Miscellaneous States ...................................................................................................257
18.2 Control Registers of I2C...................................................................................... 258
18.3 Typical Structure of I2C Interrupt Service Routine .......................................... 264
18.4 I2C Time-Out......................................................................................................... 267
18.5 I2C Interrupt .......................................................................................................... 268
19PIN INTERRUPT..........................................................................................269
20PULSE WIDTH MODULATED (PWM).........................................................274
20.1 Functional Description ........................................................................................ 274
20.1.1PWM Generator............................................................................................................274
20.1.2PWM Types ...................................................................................................................282
20.1.3Operation Modes ..........................................................................................................284
20.1.4Mask Output Control ....................................................................................................287
20.1.5Fault Brake ....................................................................................................................288
20.1.6Polarity Control .............................................................................................................289
20.2 PWM Interrupt ...................................................................................................... 290
2112-BIT ANALOG-TO-DIGITAL CONVERTER (ADC)..................................293

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21.1 Functional Description ........................................................................................ 293
21.1.1ADC Operation..............................................................................................................293
21.1.2ADC Conversion Triggered by External Source ......................................................295
21.1.3ADC Conversion Result Comparator.........................................................................295
21.1.4ADC Continues Conversion ........................................................................................296
21.2 Control Registers of ADC ................................................................................... 297
22VOLTAGE REFERENCE.............................................................................304
23ANALOG COMPARATOR CONTROLLER (ACMP) ...................................306
23.1 Functional Description ........................................................................................ 306
23.2 Hysteresis Function............................................................................................. 307
23.3 Comparator Reference Voltage (CRV)............................................................. 308
23.4 Interrupt Sources ................................................................................................. 309
23.5 Control Registers of ACMP Controller.............................................................. 310
24PDMA CONTROLLER (PDMA) ...................................................................314
24.1 Functional Description ........................................................................................ 315
24.2 Operating Modes ................................................................................................. 315
24.2.1SPI peripheral to XRAM memory...............................................................................315
24.2.2SMC/UART peripheral to XRAM memory.................................................................316
24.2.3Memory to Memory (XRAM) Transfer .......................................................................316
24.3 PDMA Control Registers..................................................................................... 317
25TIMED ACCESS PROTECTION (TA)..........................................................321
26INTERRUPT SYSTEM .................................................................................323
26.1 Interrupt Overview ............................................................................................... 323
26.2 Enabling Interrupts .............................................................................................. 324
26.3 Interrupt Priorities ................................................................................................ 329
26.4 Interrupt Service................................................................................................... 336
26.5 Interrupt Latency.................................................................................................. 337
26.6 External Interrupt Pins ........................................................................................ 337
27IN-APPLICATION-PROGRAMMING (IAP)..................................................339
27.1 IAP Commands.................................................................................................... 343
27.2 IAP User Guide .................................................................................................... 344
27.3 Using Flash Memory as Data Storage ............................................................. 344
27.4 In-System-Programming (ISP) .......................................................................... 346
28POWER MANAGEMENT.............................................................................352
28.1 Idle Mode .............................................................................................................. 353

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28.2 Low Power Run Mode......................................................................................... 354
28.3 Low Power Idle Mode ......................................................................................... 354
28.4 Power-Down Mode.............................................................................................. 354
29CLOCK SYSTEM.........................................................................................355
29.1 System Clock Sources........................................................................................ 355
29.1.1Internal Oscillators........................................................................................................355
29.1.2External Crystal/Resonator or Clock Input ...............................................................356
29.2 System Clock Switching ..................................................................................... 357
29.3 System Clock Divider.......................................................................................... 359
29.4 System Clock Output .......................................................................................... 360
30POWER MONITORING................................................................................361
30.1 Power-On Detection............................................................................................ 361
30.2 Brown-Out Detection (BOD) .............................................................................. 361
31RESET .........................................................................................................367
31.1 Power-On Reset and Low Voltage Reset ........................................................ 367
31.2 Brown-Out Reset ................................................................................................. 368
31.3 External Reset and Hard Fault Reset............................................................... 368
31.4 Watchdog Timer Reset ....................................................................................... 369
31.5 Software Reset..................................................................................................... 369
31.6 Boot Select ........................................................................................................... 371
31.7 Reset State........................................................................................................... 372
32AUXILIARY FEATURES..............................................................................373
32.1 Dual DPTRs.......................................................................................................... 373
32.2 96-Bit Unique Code............................................................................................. 375
33ON-CHIP-DEBUGGER (OCD).....................................................................376
33.1 Functional Description ........................................................................................ 376
33.2 Limitation of OCD ................................................................................................ 376
34IN-CIRCUIT-PROGRAMMING (ICP)............................................................378
35INSTRUCTION SET.....................................................................................379
36CONFIG BYTES...........................................................................................385
36.1 CONFIG0 .............................................................................................................. 386
36.2 CONFIG1 .............................................................................................................. 387
36.3 CONFIG2 .............................................................................................................. 388
36.4 CONFIG4 .............................................................................................................. 389

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37PACKAGE DIMENSIONS............................................................................390
37.1 LQFP 48 (7x7x1.4 mm) ...................................................................................... 390
37.2 QFN 33 (4x4x0.8 mm)........................................................................................ 391
37.3 LQFP 32 (7x7x1.4 mm) ...................................................................................... 392
37.4 TSSOP 28 (4.4x9.7x1.0 mm)............................................................................. 393
37.5 SOP 28 (300 mil) ................................................................................................. 394
37.6 TSSOP 20 (3.0X3.0 mm).................................................................................... 395
37.7 SOP 20 (300 mil) ................................................................................................. 396
37.8 QFN 20 ( 3.0 X 3.0 mm ) .................................................................................... 397
37.9 TSSOP 14 (4.4 X 5.5 mm)................................................................................. 398
37.10 MSOP 10 (3 x 3 mm).......................................................................................... 399
38REVISION HISTORY ...................................................................................400

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LIST OF FIGURES
Figure 4.1-1 Pin Assignment of QFN-33 Package........................................................................19
Figure 4.1-2 Pin Assignment of LQFP-32 Package......................................................................20
Figure 4.1-3 Pin Assignment of TSSOP-28 Package................................................................... 20
Figure 4.1-4 Pin Assignment of SOP-28 Package........................................................................21
Figure 4.1-5 Pin Assignment of TSSOP-20 Package................................................................... 21
Figure 4.1-6 Pin Assignment of TSSOP-20 Package................................................................... 22
Figure 4.1-7 Pin Assignment of QFN-20 Package........................................................................ 22
Figure 4.1-8 Pin Assignment of TSSOP-14 Package................................................................... 23
Figure 4.1-9 Pin Assignment of MSOP-10 Package.....................................................................23
Figure 4.1-10 Multi Function Pin Assignment of QFN-33 Package..............................................24
Figure 4.1-11 Multi Function Pin Assignment of LQFP-32 Package ............................................25
Figure 4.1-12 Multi Function Pin Assignment of TSSOP-28 Package..........................................26
Figure 4.1-13 Multi Function Pin Assignment of SOP-28 Package..............................................26
Figure 4.1-14 Multi Function Pin Assignment of TSSOP-20 Package..........................................26
Figure 4.1-15 Multi Function Pin Assignment of SOP-20 Package..............................................27
Figure 4.1-16 Multi Function Pin Assignment of QFN-20 Package..............................................27
Figure 4.1-17 Multi Function Pin Assignment of Package............................................................ 28
Figure 4.1-18 Pin Assignment of MSOP-10 Package...................................................................28
Figure 5.1-1 Functional Block Diagram.........................................................................................37
Figure 6.1-1 ML51 Program Memory Map....................................................................................40
Figure 6.2-1 Data Memory Map....................................................................................................40
Figure 6.2-2 Internal 256 Bytes RAM Addressing.........................................................................42
Figure 9.1-1 Quasi-Bidirectional Mode Structure........................................................................157
Figure 9.2-1 Push-Pull Mode Structure.......................................................................................157
Figure 9.3-1 Input-Only Mode Structure ..................................................................................... 159
Figure 9.4-1 Open-Drain Mode Structure ................................................................................... 159
Figure 10.1-1 Timer/Counters 0 and 1 in Mode 0.......................................................................175
Figure 10.2-1 Timer/Counters 0 and 1 in Mode 1.......................................................................175
Figure 10.3-1 Timer/Counters 0 and 1 in Mode 2.......................................................................176
Figure 10.4-1 Timer/Counter 0 in Mode 3...................................................................................177
Figure 10.4-1 Timer 2 Block Diagram......................................................................................... 178
Figure 11.1-1 Timer 2 Auto-Reload Mode and Input Capture Module Functional Block Diagram
..............................................................................................................................................182
Figure 11.2-1 Timer 2 Compare Mode and Input Capture Module Functional Block Diagram...183
Figure 11.4-1 Timer 3 Block Diagram......................................................................................... 189
Figure 13.1-1 WDT as A Time-Out Reset Timer.........................................................................193
Figure 13.2-1 Watchdog Timer Block Diagram...........................................................................194

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Figure 13.2-1 Self Wake-Up Timer Block Diagram.....................................................................196
Figure 15.1-1 Serial Port Mode 0 Timing Diagram .....................................................................199
Figure 15.2-1 Serial Port Mode 1 Timing Diagram .....................................................................200
Figure 15.3-1 Serial Port Mode 2 and 3 Timing Diagram ...........................................................201
Figure 16.1-1 SC Controller Block Diagram................................................................................. 216
Figure 16.4-1 SC Data Character ...............................................................................................228
Figure 16.4-2 Initial Character TS..............................................................................................229
Figure 16.4-3 SC Error Signal..................................................................................................... 229
Figure 16.4-4 Transmit Direction Block Guard Time Operation..................................................230
Figure 16.4-5 Receive Direction Block Guard Time Operation.................................................... 230
Figure 16.4-6 Extra Guard Time Operation .................................................................................230
Figure 17.1-1 SPI Block Diagram.................................................................................................231
Figure 17.1-2 SPI Multi-Master, Multi-Slave Interconnection .....................................................232
Figure 17.1-3 SPI Single-Master, Single-Slave Interconnection................................................. 233
Figure 17.4-1 SPI Clock Formats................................................................................................241
Figure 17.4-2 SPI Clock and Data Format with CPHA = 0 ......................................................... 242
Figure 17.4-3 SPI Clock and Data Format with CPHA = 1 ......................................................... 242
Figure 17.8-1 SPI Overrun Waveform ........................................................................................244
Figure 17.9-1 SPI Interrupt Request...........................................................................................244
Figure 18.1-1 I2C Bus Interconnection........................................................................................245
Figure 18.1-2 I2C Bus Protocol ...................................................................................................246
Figure 18.1-3 START, Repeated START, and STOP Conditions .............................................. 247
Figure 18.1-4 Master Transmits Data to Slave by 7-bit ..............................................................247
Figure 18.1-5 Master Reads Data from Slave by 7-bit................................................................248
Figure 18.1-6 Data Format of One I2C Transfer..........................................................................248
Figure 18.1-7 Acknowledge Bit...................................................................................................249
Figure 18.1-8 Arbitration Procedure of Two Masters..................................................................250
Figure 18.1-9 Control I2C Bus according to the Current I2C Status............................................251
Figure 18.1-10 Flow and Status of Master Transmitter Mode .................................................... 252
Figure 18.1-11 Flow and Status of Master Receiver Mode ........................................................253
Figure 18.1-12 Flow and Status of Slave Receiver Mode ..........................................................255
Figure 18.1-13 Flow and Status of General Call Mode...............................................................256
Figure 18.4-1 I2C Time-Out Counter...........................................................................................267
Figure 18.5-1 Pin Interface Block Diagram.................................................................................269
Figure 20.1-1 PWM Block Diagram.............................................................................................275
Figure 20.1-2 PWM and Fault Brake Output Control Block Diagram .........................................276
Figure 20.1-3 PWM Edge-aligned Type Waveform....................................................................282

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Figure 20.1-4 PWM Center-aligned Type Waveform..................................................................283
Figure 20.1-5 PWM Complementary Mode with Dead-time Insertion ........................................285
Figure 20.1-6 Fault Brake Function Block Diagram....................................................................288
Figure 20.2-1 PWM Interrupt Type..............................................................................................292
Figure 21.1-1 12-bit ADC Block Diagram..................................................................................... 293
Figure 21.1-2 External Triggering ADC Circuit ...........................................................................295
Figure 21.1-3 ADC Result Comparator.......................................................................................296
Figure 21.1-4 ADC Continues mode with DMA ..........................................................................296
Figure 21.2-1 VREF Block Diagram ..............................................................................................304
Figure 21.2-2 Pre-load Timing ....................................................................................................304
Figure 23.1-1 Analog Comparator Block Diagram......................................................................306
Figure 23.2-1 Comparator Hysteresis Function..........................................................................308
Figure 23.3-1 Comparator Reference Voltage Block Diagram ................................................... 309
Figure 23.4-1 Analog Comparator Interrupt Sources..................................................................309
Figure 23.5-1 PDMA Interface Diagram......................................................................................314
Figure 24.1-1 PDMA Controller Block Diagram ..........................................................................315
Figure 28.4-1 Clock System Block Diagram ................................................................................ 355
Figure 30.2-1 Brown-out Detection Block Diagram.....................................................................362
Figure 31.6-1 Boot Selecting Diagram........................................................................................371
Figure 36.1-1 CONFIG0 Any Reset Reloading...........................................................................386
Figure 36.3-1 CONFIG2 Power-On Reset Reloading................................................................. 388
Figure 37.1-1 LQFP-48 Package Dimension..............................................................................390
Figure 37.2-1 QFN-33 Package Dimension................................................................................ 391
Figure 37.3-1 LQFP-32 Package Dimension..............................................................................392
Figure 37.4-1 TSSOP-28 Package Dimension ...........................................................................393
Figure 37.5-1 SOP-28 Package Dimension............................................................................... 394
Figure 37.6-1 TSSOP-20 Package Dimension...........................................................................395
Figure 37.7-1 SOP-20 Package Dimension................................................................................ 396
Figure 37.8-1 QFN-20 Package Dimension................................................................................397
Figure 37.9-1 TSSOP-14 Package Dimension ...........................................................................398
Figure 37.10-1 MSOP-10 Package Dimension........................................................................... 399

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List of Tables
Table 7.1-1 Special Function Register (SFR) Memory Map......................................................... 45
Table 7.1-2 SFR Definitions And Reset Values............................................................................47
Table 7.2-1 Instructions That Affect Flag Settings......................................................................154
Table 7.2-1 Configuration for Different I/O Modes....................................................................... 156
Table 11.4-1 Watchdog Timer-out Interval Under Different Pre-scalars......................................193
Table 15.5-1 Serial Port 0 Mode / baudrate Description..............................................................202
Table 15.5-2 Serial Port 1 Mode / baudrate Description..............................................................203
Table 17.2-1 Slave Select Pin Configurations .............................................................................238
Table 26.1-1 Interrupt Vectors .....................................................................................................323
Table 26.3-1 Interrupt Priority Level Setting ............................................................................... 329
Table 26.3-2 Characteristics of Each Interrupt Source...............................................................330
Table 27.1-1 IAP Modes and Command Codes ......................................................................... 343
Table 27.4-1 Power Mode Table................................................................................................. 352
Table 27.4-2 Entry setting of power down mode ........................................................................352
Table 30.2-1 BOF Reset Value...................................................................................................364
Table 30.2-2 Minimum Brown-out Detect Pulse Width...............................................................366
Table 33.2-1 Instruction Set........................................................................................................380

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1 GENERAL DESCRIPTION
The ML51 is a Flash embedded 1T 8051-based microcontroller. The instruction set of the ML51 is fully
compatible with the standard 80C51 with performance enhanced.
The ML51 runs up to 24 MHz at a wide voltage range from 1.8V to 5.5V, and contains up to 64/32/16
Kbytes Flash called APROM for programming code. The ML51 Flash supports In-Application-
Programming (IAP) function, which enables on-chip firmware updates. Partial Flash can be optionally
configured as Data Flash programmed by IAP and read by IAP or MOVC instruction. The ML51
includes an additional configurable up to 4/3/2/1 Kbytes Flash area called LDROM, in which the Boot
Code normally resides for carrying out the In-System-Programming (ISP). To facilitate mass
production programming and verification, the Flash is allowed to be programmed and read
electronically by parallel Writer/Programmer or In-Circuit-Programming (ICP) with Nu-Link. Once
programmed and verified, the programmed code can be protected by the Flash lock mechanism for
not being read out by any external programming tool.
The ML51 provides rich peripherals including 256 bytes of SRAM, 4/2/1 Kbytes of auxiliary RAM
(XRAM), up to 43 general purpose I/O, two 16-bit Timers/Counters 0/1, one 16-bit Timer2 with three-
channel input capture module, one Watchdog Timer (WDT), one Self Wake-up Timer (WKT), one 16-
bit auto-reload Timer3 for general purpose or baud rate generator, two UARTs with frame error
detection and automatic address recognition, two ISO7816 Smartcard interface, two SPI, two I2C, 12
enhanced PWM output channels with dead zone control, two analog comparators, eight-channel
shared pin interrupt for all I/O ports, and one 12-bit ADC at 500 ksps. There are a total of 30 sources
with 4-level-priority interrupts capability.
The ML51 is equipped with four clock sources and supports on-the-fly clock switching via software
control. The four clock sources include two sets of external crystal inputs (HXT, LXT), 38.4 kHz
internal oscillator, and one 24 MHz internal high-precision ±5% oscillator. The ML51 provides
additional power monitoring detection such as power-on reset and 7-level brown-out detection, which
stabilizes the power-on/off sequence for a high reliability system design.
The ML51 microcontroller provides 3 power modes to reduce power consumption －Low power run
mode, Low power Idle mode, and Power-down mode. In Low power run mode, the power consumption
can be down to 15 uA at 38.4 kHz LIRC. In Low power idle mode, CPU processing is suspended by
holding the Program Counter. No program code is fetched and run in low power idle mode if the power
consumption does not exceed 13 uA. Power-down mode stops the whole system clock for minimum
power consumption with the leakage current less than 1 uA. The system clock of the ML51 can also
be slowed down by software clock divider, which allows for flexibility between execution performance
and power consumption.

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Through the high performance of 1T 8051 core, low power performance of ML51 and rich well-
designed peripherals, the ML51 benefits for low-power, battery powered devices, general purpose,
home appliances, or motor control system.

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2 FEATURES
CPU:
–Fully static design 8-bit high performance 1T 8051-based CMOS microcontroller.
–Instruction set fully compatible with MCS-51.
–4-priority-level interrupts capability.
–Dual Data Pointers (DPTRs).
Operating:
–Wide supply voltage from 1.8 V to 5.5 V.
–Wide operating frequency up to 24 MHz
–Industrial temperature grade: -40 ℃to +105 ℃.
Low power features:
–Normal run typical power consumption 80 A/ MHz
–Low power run mode typical power consumption 15 A
–Low power Idle mode power consumption does not exceed 13 A
–Power down mode typical power consumption less than 1 A
–Wake up time from power down mode less than 10 s (run with HIRC).
Memory:
–Up to 64/32/16 Kbytes of APROM for User Code.
–4/3/2/1 Kbytes of Flash for loader (LDROM) configure from APROM for In-System-
Programmable (ISP)
–Flash Memory accumulated with pages of 128 Bytes from APROM by In-Application-
Programmable (IAP).
–Flash Memory 100,000 writing cycle endurance.
–Code lock for security.
–256 Bytes on-chip RAM.
–Additional 4/2/1 Kbytes on-chip auxiliary RAM (XRAM) accessed by MOVX instruction.
PDMA:
–Three modes: peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer.
–Source address and destination address must be word alignment in all modes.
–Memory-to-memory mode: transfer length must be word alignment.
–Peripheral-to-memory and memory-to-peripheral mode: transfer length could be byte
alignment.

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–Peripheral-to-memory and memory-to-peripheral mode: transfer data width byte alignment.
Clock sources:
–24 MHz high-speed internal oscillator (HIRC) trimmed to ±1% (accuracy at 25 ℃, 3.3 V), ±5%
in all conditions.
–38.4 kHz low-speed internal oscillator (LIRC) calibrating to ±1% by software from high-speed
internal oscillator (HIRC) or external crystal (HXT).
–External 4~24 MHz crystal (HXT) input for precise timing operation.
–External 32.768 kHz (LXT) crystal input.
–On-the-fly clock source switch via software.
–Programmable system clock divider from 1/2, 1/4, 1/6, 1/8…, up to 1/512.
Peripherals:
–Up to 56 general purpose I/O pins. All output pins have individual 2-level slew rate control.
–8 channels of GPIO interrupt with variable edge/level detection from all 56 GPIO configure as
one of the input source.
–Standard interrupt pins INT0







and INT1







compatible with standard 8051.
–Two 16-bit Timers/Counters 0 and 1 compatible with standard 8051.
–One 16-bit Timer 2 with three-channel input capture module.
–One 16-bit auto-reload Timer 3, which can be the baud rate clock source of UARTs.
–One programmable Watchdog Timer (WDT) clocked by dedicated 38.4 kHz LIRC.
–One dedicated Self Wake-up Timer (WKT) for self-timed wake-up for power reduced modes by
dedicated 38.4 kHz LIRC or 32.768 kHz LXT.
–Two full-duplex UART ports with frame error detection and automatic address recognition. TXD
and RXD pins of all UART exchangeable via software.
–Two smart card port supports ISO7816-3 compliant T=0, T=1 and supports full-duplex UART
mode .
–Two SPI port with master and slave modes, up to 6 Mbps when system clock is 24 MHz
–Two I2C bus with master and slave modes, up to 400 kbps data rate.
–Maxima 6 pairs, 12 channels of pulse width modulator (PWM) output, up to 16-bit resolution,
with different modes and Fault Brake function for motor control. The 16-bit PWM counter
individual used as timer with interrupt.
–Two comparator supports hysteresis function.
–One 12-bit ADC, up to 500 ksps (when VDD over then 2.5 V) converting rate, hardware
triggered and conversion result compare facilitating motor control.
Power monitor:

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–Brown-out detection (BOD) with low power mode available, 7-level selection, interrupt or reset
options.
–Power-on reset (POR).
–Low voltage reset (LVR).
Strong ESD and EFT immunity.
–ESD HBM pass 8 KV
–EFT > ± 4.4 KV
–Latch-up pass 150 mA
Development Tools:
–Nuvoton Nu-Link with KEILTM and IAR development environment.
–Nuvoton In-Circuit-Programmer (Nu-Link).
–Nuvoton In-System-Programming (ISP) via UART.

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3 PART INFORMATION
3.1 ML51 Series Selection Guide
Part Number
Flash (KB)
SRAM (KB)
ISP ROM (KB)*
I/O
Timer/
PWM
Analog Comparator
Internal Voltage Reference
PDMA
Connectivity
ADC(12-Bit)
Package
ISO-7816**
UART
SPI
I2C
ML51BB9AE
16
1
4
7
4
5
-
-
-
-
2
-
2
2-ch
MSOP10
ML51DB9AE
16
1
4
11
4
6
-
-
-
1
2
1
2
3-ch
TSSOP14
ML51FB9AE
16
1
4
16
4
6
-
-
-
1
2
1
2
6-ch
TSSOP20
ML51OB9AE
16
1
4
16
4
6
-
-
-
1
2
1
2
6-ch
SOP20
ML51XB9AE
16
1
4
17
4
6
-
-
-
1
2
1
2
6-ch
QFN20
ML51EB9AE
16
1
4
24
4
6
-
-
-
1
2
1
2
8-ch
TSSOP28
ML51UB9AE
16
1
4
24
4
6
-
-
-
1
2
1
2
8-ch
SOP28
ML51PB9AE
16
1
4
28
4
6
2
Y
2
1
2
1
2
8-ch
LQFP32
ML51TB9AE
16
1
4
28
4
6
2
Y
2
1
2
1
2
8-ch
QFN33
ML51EC0AE
32
2
4
24
4
6
2
Y
2
1
2
2
2
8-ch
TSSOP28
ML51UC0AE
32
2
4
24
4
6
2
Y
2
1
2
2
2
8-ch
SOP28
ML51PC0AE
32
2
4
28
4
6
2
Y
2
1
2
2
2
8-ch
LQFP32
ML51TC0AE
32
2
4
28
4
6
2
Y
2
1
2
2
2
8-ch
QFN33
* ISP ROM programmable 1K/2K/3K/4KB Flash for user program loader (LDROM) share from ARPOM.
** ISO-7816 configurable as standard UART function.

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3.2 ML51 Series Selection Code

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4 PIN CONFIGURATION
4.1 Pin Configuration
Users can find pin configuaration informations in chapter 3 or by using NuTool - PinConfigure. The
NuTool - PinConfigure contains all Nuvoton NuMicro®Family chip series with all part number, and
helps users configure GPIO multi-function correctly and handily.
4.1.1 ML51 Series Pin Diagram
QFN33 Package4.1.1.1
Corresponding Part Number: ML51TC0AE / ML51TB9AE
33 VSS
1 2 3 4 5 6 7 8
16
15
14
13
12
11
10
9
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
VSS
P4.6
VDD
P3.3
P3.2
P3.1
P3.0
VREF
P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P5.5 P5.4
nRESET
P5.6
P0.0
P0.1
P0.2
P0.3
P5.2
P5.3
P1.7 P1.6 P1.5 P1.4 P4.0 P4.1 P5.1 P5.0
Top transparent view
QFN33
ML51TC0AE
ML51TB9AE
Figure 4.1-1 Pin Assignment of QFN-33 Package

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LQFP32 Package4.1.1.2
Corresponding Part Number: ML51PD1AE / ML51PC0AE / ML51PB9AE
1 2 3 4 5 6 7 8
16
15
14
13
12
11
10
9
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
VSS
P4.6
VDD
P3.3
P3.2
P3.1
P3.0
VREF
P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P5.5 P5.4
nRESET
P5.6
P0.0
P0.1
P0.2
P0.3
P5.2
P5.3
P1.7 P1.6 P1.5 P1.4 P4.0 P4.1 P5.1 P5.0
LQFP32
ML51PD1AE
ML51PC0AE
ML51PB9AE
Figure 4.1-2 Pin Assignment of LQFP-32 Package
TSSOP28 Package4.1.1.3
Corresponding Part Number: ML51EC0AE / ML51EB9AE
TSSOP28
ML51EC0AE ML51EB9AE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P1.4
P1.5
P1.6
P1.7
VSS
P4.6
VDD
P3.2
P3.1
P3.0
VREF
P2.5
P2.4
P2.3
P4.0
P4.1
P5.1
P5.0
nRESET
P0.0
P0.1
P0.2
P0.3
P5.2
P5.3
P2.0
P2.1
P2.2
Figure 4.1-3 Pin Assignment of TSSOP-28 Package
SOP28 Package4.1.1.4