Nuvoton NUC970 series Product manual

NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
- 1 - Revision V1.30
NUC970 TECHNICAL REFERENCE MANUAL
ARM926EJ-S Based
32-bit Microcontroller
NUC970 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
- 2 - Revision V1.30
NUC970 TECHNICAL REFERENCE MANUAL

NUC970 Technical Reference Manual
Publication Release Date: Dec. 15, 2015
- 3 - Revision V1.30
NUC970 TECHNICAL REFERENCE MANUAL
TABLE OF CONTENTS
TABLE OF CONTENTS.........................................................................................................3
LIST OF FIGURES...............................................................................................................12
LIST OF TABLES.................................................................................................................17
1 GENERAL DESCRIPTION..........................................................................................18
2 FEATURES .................................................................................................................19
NUC970 Series Features...................................................................................................19
2.1
3 PARTS INFORMATION LIST AND PIN CONFIGURATION........................................27
NUC970 Series Part Number Naming Guide......................................................................273.1 NUC970 Series Part Selection Guide.................................................................................283.2 Pin Configuration ...............................................................................................................293.3
3.3.1 NUC972DFxxY Pin Diagram............................................................................................................ 29
3.3.2 NUC976DKxxY Pin Diagram............................................................................................................ 30
3.3.3 NUC977DKxxY Pin Diagram............................................................................................................ 31
Pin Description...................................................................................................................323.4
4 BLOCK DIAGRAM.......................................................................................................58
NUC970 Series Block Diagram..........................................................................................584.1
5 FUNCTIONAL DESCRIPTION....................................................................................59
ARM®ARM926EJ-S CPU Core..........................................................................................595.1
5.1.1 Overview........................................................................................................................................... 59
5.1.2 System Control Coprocessor (CP15)............................................................................................... 60
5.1.3 Memory Management Unit (MMU)................................................................................................... 60
5.1.4 Caches and Write Buffer .................................................................................................................. 61
5.1.5 Bus Interface Unit............................................................................................................................. 62
5.1.6 Power Management......................................................................................................................... 62
System Manager................................................................................................................635.2
5.2.1 Overview........................................................................................................................................... 63
5.2.2 System Reset................................................................................................................................... 63
5.2.3 System Power Distribution ............................................................................................................... 64
5.2.4 System Memory Map ....................................................................................................................... 65
5.2.5 Power-On Setting............................................................................................................................. 69
5.2.6 Register Map.................................................................................................................................... 71
5.2.7 Register Description......................................................................................................................... 73
Clock Controller (CLK_CTL).............................................................................................139
5.3

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5.3.1 Overview......................................................................................................................................... 139
5.3.2 Features ......................................................................................................................................... 139
5.3.3 Block diagram................................................................................................................................. 140
5.3.4 Functional description .................................................................................................................... 149
5.3.5 Registers Map ................................................................................................................................ 151
5.3.6 Register description........................................................................................................................ 152
Advanced Interrupt Controller (AIC).................................................................................1865.4
5.4.1 Overview......................................................................................................................................... 186
5.4.2 Features ......................................................................................................................................... 186
5.4.3 Block Diagram................................................................................................................................ 187
5.4.4 Functional Description.................................................................................................................... 187
5.4.5 Register Map.................................................................................................................................. 192
5.4.6 Register Description....................................................................................................................... 194
SDRAM Interface Controller (SDIC).................................................................................2175.5
5.5.1 Overview......................................................................................................................................... 217
5.5.2 Features ......................................................................................................................................... 217
5.5.3 Block Diagram................................................................................................................................ 218
5.5.4 Basic Configuration ........................................................................................................................ 219
5.5.5 Functional Description.................................................................................................................... 219
5.5.6 Register Map.................................................................................................................................. 223
5.5.7 Register Description....................................................................................................................... 223
MTP Controller (MTP)......................................................................................................2465.6
5.6.1 Overview......................................................................................................................................... 246
5.6.2 Features ......................................................................................................................................... 246
5.6.3 Block Diagram................................................................................................................................ 247
5.6.4 Basic Configuration ........................................................................................................................ 248
5.6.5 Functional Description.................................................................................................................... 249
5.6.6 Software Programming Flow.......................................................................................................... 250
5.6.7 Register Map.................................................................................................................................. 251
5.6.8 Register Description....................................................................................................................... 252
External Bus Interface (EBI).............................................................................................2615.7
5.7.1 Overview......................................................................................................................................... 261
5.7.2 Features ......................................................................................................................................... 261
5.7.3 Block Diagram................................................................................................................................ 261
5.7.4 Basic Configuration ........................................................................................................................ 262
5.7.5 Functional Description.................................................................................................................... 262

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5.7.6 Register Map.................................................................................................................................. 263
5.7.7 Register Description....................................................................................................................... 264
General Purpose I/O (GPIO)............................................................................................2725.8
5.8.1 Overview......................................................................................................................................... 272
5.8.2 Features ......................................................................................................................................... 272
5.8.3 Block Diagram................................................................................................................................ 273
5.8.4 Basic Configuration ........................................................................................................................ 273
5.8.5 Functional Description.................................................................................................................... 273
5.8.6 Register Map.................................................................................................................................. 274
5.8.7 Register Description....................................................................................................................... 279
General DMA Controller (GDMA).....................................................................................2995.9
5.9.1 Overview......................................................................................................................................... 299
5.9.2 Features ......................................................................................................................................... 299
5.9.3 Block Diagram................................................................................................................................ 299
5.9.4 Basic Configuration ........................................................................................................................ 300
5.9.5 Functional Description.................................................................................................................... 300
5.9.6 Register Map.................................................................................................................................. 304
5.9.7 Register Description....................................................................................................................... 305
Timer Controller (TMR) ....................................................................................................3225.10
5.10.1 Overview......................................................................................................................................... 322
5.10.2 Features ......................................................................................................................................... 322
5.10.3 Block Diagram................................................................................................................................ 323
5.10.4 Basic Configuration ........................................................................................................................ 323
5.10.5 Functional Description.................................................................................................................... 323
5.10.6 Register Map.................................................................................................................................. 325
5.10.7 Register Description....................................................................................................................... 326
Enhance Timer Controller (ETMR)...................................................................................3325.11
5.11.1 Overview......................................................................................................................................... 332
5.11.2 Features ......................................................................................................................................... 332
5.11.3 Block Diagram................................................................................................................................ 332
5.11.4 Basic Configuration ........................................................................................................................ 333
5.11.5 Functional Description.................................................................................................................... 333
5.11.6 Register Map.................................................................................................................................. 336
5.11.7 Register Description....................................................................................................................... 336
Pulse Width Modulation (PWM) .......................................................................................3475.12
5.12.1 Overview......................................................................................................................................... 347

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5.12.2 Features ......................................................................................................................................... 347
5.12.3 Block Diagram................................................................................................................................ 348
5.12.4 Basic Configuration ........................................................................................................................ 348
5.12.5 Functional Description.................................................................................................................... 348
5.12.6 Register Map.................................................................................................................................. 352
5.12.7 Register Description....................................................................................................................... 353
Watchdog Timer (WDT)...................................................................................................3635.13
5.13.1 Overview......................................................................................................................................... 363
5.13.2 Features ......................................................................................................................................... 363
5.13.3 Block Diagram................................................................................................................................ 363
5.13.4 Basic Configuration ........................................................................................................................ 363
5.13.5 Functional Description.................................................................................................................... 364
5.13.6 Register Map.................................................................................................................................. 367
5.13.7 Register Description....................................................................................................................... 368
Windowed Watchdog Timer (WWDT) ..............................................................................3725.14
5.14.1 Overview......................................................................................................................................... 372
5.14.2 Features ......................................................................................................................................... 372
5.14.3 Block Diagram................................................................................................................................ 372
5.14.4 Basic Configuration ........................................................................................................................ 372
5.14.5 Function Description....................................................................................................................... 373
5.14.6 Register Map.................................................................................................................................. 377
5.14.7 Register Description....................................................................................................................... 378
Real Time Clock (RTC)....................................................................................................3845.15
5.15.1 Overview......................................................................................................................................... 384
5.15.2 Features ......................................................................................................................................... 384
5.15.3 Block Diagram................................................................................................................................ 385
5.15.4 Basic Configuration ........................................................................................................................ 385
5.15.5 Functional Description.................................................................................................................... 385
5.15.6 Register Map.................................................................................................................................. 387
5.15.7 Register Description....................................................................................................................... 389
UART Interface Controller (UART)...................................................................................4115.16
5.16.1 Overview......................................................................................................................................... 411
5.16.2 Features ......................................................................................................................................... 412
5.16.3 Block Diagram................................................................................................................................ 413
5.16.4 Basic Configuration ........................................................................................................................ 414
5.16.5 Functional Description.................................................................................................................... 414

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5.16.6 Register Map.................................................................................................................................. 443
5.16.7 Register Description....................................................................................................................... 445
Smart Card Host Interface (SC) .......................................................................................4745.17
5.17.1 Overview......................................................................................................................................... 474
5.17.2 Features ......................................................................................................................................... 474
5.17.3 Block Diagram................................................................................................................................ 475
5.17.4 Basic Configuration ........................................................................................................................ 476
5.17.5 Functional description .................................................................................................................... 476
5.17.6 Register Map.................................................................................................................................. 486
5.17.7 Register Description....................................................................................................................... 488
I2C Synchronous Serial Interface Controller (I2C).............................................................5165.18
5.18.1 Overview......................................................................................................................................... 516
5.18.2 Features ......................................................................................................................................... 516
5.18.3 Block Diagram................................................................................................................................ 517
5.18.4 Basic Configuration ........................................................................................................................ 517
5.18.5 Functional Description.................................................................................................................... 518
5.18.6 Register Map.................................................................................................................................. 526
5.18.7 Register Description....................................................................................................................... 527
SPI Interface Controller (SPI)...........................................................................................5355.19
5.19.1 Overview......................................................................................................................................... 535
5.19.2 Features ......................................................................................................................................... 535
5.19.3 Block Diagram................................................................................................................................ 536
5.19.4 Basic Configuration ........................................................................................................................ 536
5.19.5 Function Description....................................................................................................................... 537
5.19.6 Registers Map ................................................................................................................................ 542
5.19.7 Register Description....................................................................................................................... 543
I2S Controller (I2S)............................................................................................................5505.20
5.20.1 Overview......................................................................................................................................... 550
5.20.2 Features ......................................................................................................................................... 550
5.20.3 Block Diagram................................................................................................................................ 551
5.20.4 Basic Configuration ........................................................................................................................ 551
5.20.5 Functional Description.................................................................................................................... 552
5.20.6 Register Map.................................................................................................................................. 555
5.20.7 Register Description....................................................................................................................... 556
Ethernet MAC Controller (EMAC).....................................................................................5815.21
5.21.1 Overview......................................................................................................................................... 581

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5.21.2 Features ......................................................................................................................................... 581
5.21.3 Block Diagram................................................................................................................................ 582
5.21.4 Basic Configuration ........................................................................................................................ 582
5.21.5 Functional Description.................................................................................................................... 583
5.21.6 DMA Descriptors Data Structure.................................................................................................... 586
5.21.7 Register Map.................................................................................................................................. 599
5.21.8 Register Description....................................................................................................................... 603
USB 2.0 Device Controller (USBD) ..................................................................................656
5.22
5.22.1 Overview......................................................................................................................................... 656
5.22.2 Features ......................................................................................................................................... 656
5.22.3 Block Diagram................................................................................................................................ 657
5.22.4 Basic Configuration ........................................................................................................................ 657
5.22.5 Functional Description.................................................................................................................... 657
5.22.6 Registers Map ................................................................................................................................ 660
5.22.7 Register Description....................................................................................................................... 665
USB Host Controller (USBH)............................................................................................7175.23
5.23.1 Overview......................................................................................................................................... 717
5.23.2 Features ......................................................................................................................................... 717
5.23.3 Block Diagram................................................................................................................................ 718
5.23.4 Basic Configuration ........................................................................................................................ 718
5.23.5 Functional Description.................................................................................................................... 718
5.23.6 Register Map.................................................................................................................................. 721
5.23.7 Register Description....................................................................................................................... 723
Controller Area Network (CAN)........................................................................................7715.24
5.24.1 Overview......................................................................................................................................... 771
5.24.2 Features ......................................................................................................................................... 771
5.24.3 Block Diagram................................................................................................................................ 772
5.24.4 Basic Configuration ........................................................................................................................ 773
5.24.5 Functional Description.................................................................................................................... 773
5.24.6 Test Mode....................................................................................................................................... 774
5.24.7 CAN Communications.................................................................................................................... 777
5.24.8 Register Map.................................................................................................................................. 795
5.24.9 Register Description....................................................................................................................... 801
Flash Memory Interface (FMI)..........................................................................................8365.25
5.25.1 Overview......................................................................................................................................... 836
5.25.2 Features ......................................................................................................................................... 836

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5.25.3 Block Diagram................................................................................................................................ 837
5.25.4 Basic Configuration ........................................................................................................................ 837
5.25.5 Functional Description.................................................................................................................... 838
5.25.6 Register Map.................................................................................................................................. 843
5.25.7 Register Description....................................................................................................................... 846
Secure Digital Host Controller (SDH)...............................................................................9075.26
5.26.1 Overview......................................................................................................................................... 907
5.26.2 Features ......................................................................................................................................... 907
5.26.3 Block Diagram................................................................................................................................ 907
5.26.4 Basic Configuration ........................................................................................................................ 908
5.26.5Functional Description.................................................................................................................... 908
5.26.6 Registers Map ................................................................................................................................ 910
5.26.7 Register Description....................................................................................................................... 910
Cryptographic Accelerator (CRYPTO)..............................................................................9335.27
5.27.1 Overview......................................................................................................................................... 933
5.27.2 Features ......................................................................................................................................... 933
5.27.3 Block Diagram................................................................................................................................ 934
5.27.4 Basic Configuration ........................................................................................................................ 934
5.27.5 Functional description .................................................................................................................... 935
5.27.6 Register Map.................................................................................................................................. 947
5.27.7 Register Description....................................................................................................................... 953
2D Graphic Engine (GE2D)............................................................................................10025.28
5.28.1 Overview....................................................................................................................................... 1002
5.28.2 Features ....................................................................................................................................... 1002
5.28.3 Block Diagram.............................................................................................................................. 1003
5.28.4 Basic Configuration ...................................................................................................................... 1003
5.28.5 Functional Description.................................................................................................................. 1003
5.28.6 Register Map................................................................................................................................ 1008
5.28.7 Register Description..................................................................................................................... 1010
JPEG Codec (JPEG)......................................................................................................10395.29
5.29.1 Overview....................................................................................................................................... 1039
5.29.2 Features ....................................................................................................................................... 1039
5.29.3 Block Diagram.............................................................................................................................. 1040
5.29.4 Basic Configuration ...................................................................................................................... 1041
5.29.5 Functional Description.................................................................................................................. 1042
5.29.6 Register Map................................................................................................................................ 1047

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5.29.7 Register Description..................................................................................................................... 1051
LCD Display Interface Controller (LCM) .........................................................................11055.30
5.30.1 Overview....................................................................................................................................... 1105
5.30.2 Features ....................................................................................................................................... 1105
5.30.3 Block Diagram.............................................................................................................................. 1106
5.30.4 Basic Configuration ...................................................................................................................... 1106
5.30.5 Functional Description.................................................................................................................. 1107
5.30.6 Register Map................................................................................................................................ 1110
5.30.7 Register Description..................................................................................................................... 1112
Capture Sensor Interface Controller (CAP) ....................................................................11615.31
5.31.1 Overview....................................................................................................................................... 1161
5.31.2 Feature......................................................................................................................................... 1161
5.31.3 Block Diagram.............................................................................................................................. 1162
5.31.4 Basic Configuration ...................................................................................................................... 1162
5.31.5 Functional Description.................................................................................................................. 1163
5.31.6 Register Map................................................................................................................................ 1166
5.31.7 Register Description..................................................................................................................... 1167
Analog to Digital Converter (ADC)..................................................................................11985.32
5.32.1 Overview....................................................................................................................................... 1198
5.32.2 Features ....................................................................................................................................... 1198
5.32.3 Block Diagram.............................................................................................................................. 1199
5.32.4 Basic Configuration ...................................................................................................................... 1200
5.32.5 Functional Description.................................................................................................................. 1200
5.32.6 Register Map................................................................................................................................ 1206
5.32.7 Register Description..................................................................................................................... 1207
Keypad Interface (KPI)...................................................................................................12315.33
5.33.1 Overview....................................................................................................................................... 1231
5.33.2 Features ....................................................................................................................................... 1231
5.33.3 Block Diagram.............................................................................................................................. 1232
5.33.4 Basic Configuration ...................................................................................................................... 1233
5.33.5 Functional Description.................................................................................................................. 1233
5.33.6 Register Map................................................................................................................................ 1235
5.33.7 Register Description..................................................................................................................... 1236
6 PACKAGE DIMENSIONS........................................................................................1248
LQFP 216L (24x24x1.4mm footprint 2.0mm) .................................................................12486.1 LQFP 128L (14x14x1.4mm footprint 2.0mm) .................................................................12496.2

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7 REVISION HISTORY...............................................................................................1250

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LIST OF FIGURES
Figure 3.1-1 NUC970 Series Part Number Naming Guide............................................................ 27
Figure 3.3-1 NUC972DFxxY LQFP 216-pin Pin Diagram.............................................................. 29
Figure 3.3-2 NUC976DKxxY LQFP 128-pin Pin Diagram.............................................................. 30
Figure 3.3-3 NUC977DKxxY LQFP 128-pin Pin Diagram.............................................................. 31
Figure 4.1-1 NUC970 Series Block Diagram ................................................................................. 58
Figure 5.1-1 ARM926EJ-S Block Diagram .................................................................................... 60
Figure 5.2-1 NUC970 Series Power Distribution Diagram............................................................. 64
Figure 5.3-1 Clock Controller Block Diagram............................................................................... 141
Figure 5.3-2 ADC Controller Clock Divider Block Diagram.......................................................... 142
Figure 5.3-3 eMMC Host Controller Clock Divider Block Diagram .............................................. 142
Figure 5.3-4 Enhanced Timer Clock Divider Clock Diagram ....................................................... 142
Figure 5.3-5 Ethernet MAC Controller Clock Divider Block Diagram........................................... 143
Figure 5.3-6 GPIO Clock Divider Block Diagram......................................................................... 143
Figure 5.3-7 I2S Controller Clock Divider Block Diagram............................................................. 143
Figure 5.3-8 KPI Controller Clock Divider Block Diagram............................................................ 144
Figure 5.3-9 LCD Display Controller Clock Divider Block Diagram ............................................. 144
Figure 5.3-10 Reference Clock Output Divider Block Diagram ................................................... 144
Figure 5.3-11 SD Card Host Controller Clock Divider Block Diagram......................................... 145
Figure 5.3-12 Smart Card Host Controller Clock Divider Block Diagram .................................... 145
Figure 5.3-13 CMOS Sensor Controller Divider Block Diagram.................................................. 145
Figure 5.3-14 UART Clock Divider Block Diagram...................................................................... 146
Figure 5.3-15 USB 1.1 Host Controller 48 MHz Clock Divider Block Diagram............................ 146
Figure 5.3-16 Watchdog Timer Clock Divider Block Diagram ..................................................... 146
Figure 5.3-17 Windowed Watchdog Timer Clock Divider Block Diagram.................................... 147
Figure 5.3-18 CPU_HCLK Clock Generator Block Diagram........................................................ 148
Figure 5.4-1 Advanced Interrupt Controller (AIC) Block Diagram................................................ 187
Figure 5.5-1 SDRAM Controller Block Diagram........................................................................... 218
Figure 5.5-2 Clock Delay Circuit .................................................................................................. 242
Figure 5.6-1 MTP Controller Block Diagram................................................................................ 247
Figure 5.6-2 MTP INTERFACE PIN DESCRIPTION................................................................... 248
Figure 5.7-1 EBI Block Diagram................................................................................................... 261
Figure 5.7-2 External I/O Write operation timing.......................................................................... 271
Figure 5.7-3 External I/O Read operation timing ......................................................................... 271
Figure 5.8-1 GPIO Block Diagram ............................................................................................... 273
Figure 5.9-1 GDMA Block Diagram.............................................................................................. 299

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Figure 5.10-1 Timer Controller Block Diagram ............................................................................ 323
Figure 5.11-1 Enhance Timer Controller Block Diagram............................................................. 332
Figure 5.11-2 Enhance Timer Clock Controller Diagram............................................................. 333
Figure 5.11-3 Timer Clock Controller Diagram ............................................................................ 335
Figure 5.12-1 Two channels of PWM in one pair......................................................................... 348
Figure 5.12-2 Legend of Internal Comparator Output of PWM-Timer ......................................... 349
Figure 5.12-3 PWM Double Buffer Illustration ............................................................................. 349
Figure 5.12-4 PWM Controller Output Duty Ratio........................................................................ 350
Figure 5.12-5 Paired PWM Output with Dead Zone Generation Operation................................. 350
Figure 5.13-1 Watchdog Timer Block Diagram............................................................................ 363
Figure 5.13-2 Watchdog Timer Clock Control.............................................................................. 364
Figure 5.13-3 Watchdog Timer Time-out Interval and Reset Period Timing ............................... 365
Figure 5.14-1 WWDT Block Diagram........................................................................................... 372
Figure 5.14-2 WWDT Clock Control............................................................................................. 372
Figure 5.14-3 WWDT Reset and Reload Behavior...................................................................... 375
Figure 5.15-1 RTC Functional Block Diagram ............................................................................. 385
Figure 5.16-1 UART Block Diagram............................................................................................. 413
Figure 5.16-2 Auto Flow Control Block Diagram.......................................................................... 414
Figure 5.16-3 UART Line Control of Word and Stop Length Setting........................................... 415
Figure 5.16-4 UART Line Control of Parity Bit Setting................................................................. 415
Figure 5.16-5 UART Auto-Flow Control Block Diagram............................................................... 417
Figure 5.16-6 UART CTSn Wake-Up Case 1.............................................................................. 417
Figure 5.16-7 UART CTSn Wake-Up Case 2.............................................................................. 418
Figure 5.16-8 IrDA Block Diagram ............................................................................................... 418
Figure 5.16-9 IrDA TX/RX Timing Diagram ................................................................................. 421
Figure 5.16-10 RS-485 Frame Structure ..................................................................................... 425
Figure 5.16-11 LIN Frame Structure............................................................................................ 426
Figure 5.16-12 Break Detection in LIN Mode............................................................................... 429
Figure 5.16-13 Relationship between Break Detection and Frame Error Detection.................... 430
Figure 5.16-14 LIN Sync Field Measurement.............................................................................. 438
Figure 5.16-15 UA_BAUD Update Method.................................................................................. 439
Figure 5.17-1 SC Clock Control Diagram (4-bit Prescale Counter in Clock Controller) .............. 475
Figure 5.17-2 SC Controller Block Diagram................................................................................. 475
Figure 5.17-3 SC Data Character ................................................................................................ 476
Figure 5.17-4 SC Activation Sequence........................................................................................ 477
Figure 5.17-5 SC Warm Reset Sequence ................................................................................... 479

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Figure 5.17-6 SC Deactivation Sequence.................................................................................... 480
Figure 5.17-7 Basic Operation Flow............................................................................................. 481
Figure 5.17-8 Initial Character TS................................................................................................ 482
Figure 5.17-9 SC Error Signal...................................................................................................... 482
Figure 5.18-1 I2C Block Diagram ................................................................................................. 517
Figure 5.18-2 I2C Bus Timing....................................................................................................... 518
Figure 5.18-3 Data transfer on the I2C-bus.................................................................................. 518
Figure 5.18-4 START and STOP conditions................................................................................ 520
Figure 5.18-5 Bit transfer on the I2C-bus ..................................................................................... 521
Figure 5.18-6 Acknowledge on the I2C-bus ................................................................................. 521
Figure 5.18-7 Master Transmits Data to Slave ............................................................................ 521
Figure 5.18-8 Master Reads Data from Slave ............................................................................. 522
Figure 5.18-9 Write 1 byte of data to a slave............................................................................... 523
Figure 5.18-10 Read a byte of data ............................................................................................. 524
Figure 5.18-11 Implementation of Software I2C........................................................................... 524
Figure 5.19-1 SPI Block Diagram................................................................................................. 536
Figure 5.19-2 Normal SPI Timing................................................................................................. 538
Figure 5.19-3 Alternate Phase SCLK Clock Timing..................................................................... 539
Figure 5.19-4 Dual-IO output Sequence...................................................................................... 539
Figure 5.19-5 Dual-IO Input Sequence........................................................................................ 540
Figure 5.20-1 I2S Controller Block Diagram................................................................................. 551
Figure 5.20-2 I2S Interface Signal of Master Mode...................................................................... 552
Figure 5.20-3 I2S Interface Signal of Slave Mode........................................................................ 552
Figure 5.20-4 I2S MSB-Justified Format ...................................................................................... 553
Figure 5.20-5 PCM Mode Signal Interface................................................................................... 553
Figure 5.20-6 PCM Mode Interface Waveform............................................................................ 554
Figure 5.21-1 Ethernet MAC Controller Block Diagram............................................................... 582
Figure 5.21-2 Ethernet Frame Format ......................................................................................... 584
Figure 5.21-3 64-bit Reference Timing Counter .......................................................................... 585
Figure 5.21-4 RXDMA Descriptor Data Structure........................................................................ 586
Figure 5.21-5 TXDMA Descriptor Data Structure ........................................................................ 592
Figure 5.21-6 MII Management Frame Format............................................................................ 621
Figure 5.22-1 USB Device Controller Block Diagram.................................................................. 657
Figure 5.23-1 USB Host Controller Block Diagram...................................................................... 718
Figure 5.24-1 CAN Peripheral Block Diagram ............................................................................. 772
Figure 5.24-2 CAN Core in Silent Mode ...................................................................................... 775

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Figure 5.24-3 CAN Core in Loop Back Mode .............................................................................. 775
Figure 5.24-4 CAN Core in Loop Back Mode Combined with Silent Mode ................................. 776
Figure 5.24-5 Data transfer between IFn Registers and Message.............................................. 779
Figure 5.24-6 Application Software Handling of a FIFO Buffer.................................................... 784
Figure 5.24-7 Bit Timing............................................................................................................... 786
Figure 5.24-8 Propagation Time Segment................................................................................... 787
Figure 5.24- ......................................................... 789
Figure 5.24-10 Filtering of Short Dominant Spikes...................................................................... 790
Figure 5.24- ........................................ 791
Figure 5.25-1 FMI Block Diagram................................................................................................ 837
Figure 5.25-2 Data Arrangement for 2 kB Page Size NAND Flash............................................. 841
Figure 5.25-3 Data Arrangement for 4 kB Page Size NAND Flash............................................. 841
Figure 5.25-4 Data Arrangement for 8 kB Page Size NAND Flash............................................. 842
Figure 5.25-5 PAD (Physical Address Descriptor) Table Format................................................ 848
Figure 5.25-6 PAD (Physical Address Descriptor) Table Fetch Modes....................................... 849
Figure 5.26-1 PAD (Physical Address Descriptor) Table Format................................................ 912
Figure 5.26-2 PAD (Physical Address Descriptor) Table Fetch Modes....................................... 913
Figure 5.27-1 Cryptographic Accelerator Block Diagram............................................................. 934
Figure 5.27-2 PRNG Function Diagram....................................................................................... 936
Figure 5.27-3 Electronic Codebook Mode ................................................................................... 937
Figure 5.27-4 Cipher Block Chaining Mode................................................................................. 938
Figure 5.27-5 Cipher Feedback Mode ......................................................................................... 939
Figure 5.27-6 Output Feedback Mode......................................................................................... 940
Figure 5.27-7 Counter Mode........................................................................................................ 941
Figure 5.27-8 CBC-CS1 Encryption............................................................................................. 942
Figure 5.27-9 CBC-CS1 Decryption............................................................................................. 942
Figure 5.28-1 2-D GE Engine Architecture ................................................................................ 1003
Figure 5.28-2 BitBLT Direction................................................................................................... 1005
Figure 5.28-3 Bresenham Line Drawing Octant......................................................................... 1006
Figure 5.28-4 Rotation Operation Octant................................................................................... 1007
Figure 5.29-1 JPEG Codec block diagram (Encode)................................................................. 1040
Figure 5.29-2 JPEG Codec block diagram (Decode)................................................................. 1041
Figure 5.29-3 Image starting address and stride....................................................................... 1043
Figure 5.29-4 Primary and thumbnail encode............................................................................ 1044
Figure 5.29-5 Single mode and continue mode......................................................................... 1045
Figure 5.29-6 Specified window decode mode.......................................................................... 1046

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Figure 5.30-1 LCD Display Interface Controller Functional Block Diagram................... 1106
Figure 5.30-2 Display and Overlay Control Timing ............................................................ 1107
Figure 5.31-1 Image Capture Functional Block Diagram........................................................... 1162
Figure 5.32-1 ADC Functional Block Diagram........................................................................... 1199
Figure 5.32-2 ADC Transfer Function........................................................................................ 1200
Figure 5.32-3 Simplified Sampling Diagram .............................................................................. 1201
Figure 5.32-4 ADC Battery Voltage Detection Diagram............................................................. 1202
Figure 5.32-5 Key Pad Detection Diagram ................................................................................ 1203
Figure 5.32-6 4-wire Touch Screen Connection Diagram ......................................................... 1204
Figure 5.32-7 5-wire Touch Screen Connection Diagram ......................................................... 1204
Figure 5.33-1 Keypad Controller Block Diagram ....................................................................... 1232
Figure 5.33-2 Keypad Connection ............................................................................................. 1233
Figure 5.33-3 Keypad Interface.................................................................................................. 1233
Figure 5.33-4 4x8 Keypad Scan Timing Diagram...................................................................... 1234

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LIST OF TABLES
Table 5.2-1 Address Space Assignments for On-Chip Controllers................................................ 68
Table 5.13-1 Watchdog Time-out Interval Period Selection ........................................................ 365
Table 5.13-2 Watchdog Reset Period Selection.......................................................................... 365
Table 5.14-1 Window Watchdog Prescaler Value Selection ....................................................... 373
Table 5.14-2 CMPDA Setting Limitation ...................................................................................... 376
Table 5.16-1 Baud Rate Equation Table...................................................................................... 416
Table 5.16-2 Baud Rate Equation Table...................................................................................... 416
Table 5.16-3 UART Interrupt Sources and Flag List in Software Mode....................................... 442
Table 5.17-1 SC Host Controller Pin Description......................................................................... 476
Table 5.17-2 UART Pin Description............................................................................................. 476
Table 5.21-1 Arbiter Arbitration Results....................................................................................... 583
Table 5.21-2 Different CAMCMR Setting and Type of Received Packet..................................... 606
Table 5.21-3 MII Management Function Configure Sequence.................................................... 621
Table 5.24-1 Initialization of a Transmit Object............................................................................ 781
Table 5.24-2 Initialization of a Receive Object............................................................................. 782
Table 5.24-3 CAN Bit Time Parameters ...................................................................................... 786
Table 5.24-4 CAN Register Map for Each Bit Function ............................................................... 800
Table 5.24-5 Error Code .............................................................................................................. 805
Table 5.24-6 Source of Interrupts ................................................................................................ 808
Table 5.24-7 IF1 and IF2 Message Interface Register ................................................................ 811
Table 5.24-8 Structure of a Message Object in the Message Memory........................................ 825
Table 5.25-1 Number of Parity (Byte) for Each BCH Algorithm................................................... 840

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1 GENERAL DESCRIPTION
The NUC970 series targeted for general purpose 32-bit microcontroller embeds an outstanding
CPU core ARM926EJ-S, a RISC processor designed by Advanced RISC Machines Ltd., runs up
to 300 MHz, with 16 KB I-cache, 16 KB D-cache and MMU, 56KB embedded SRAM and 16 KB
IBR (Internal Boot ROM) for booting from USB, NAND and SPI FLASH.
The NUC970 series integrates two 10/100 Mb Ethernet MAC controllers, USB 2.0 HS
HOST/Device controller with HS transceiver embedded, TFT type LCD controller, CMOS sensor
I/F controller, 2D graphics engine, DES/3DES/AES crypto engine, I2S I/F controller,
SD/MMC/NAND FLASH controller, GDMA and 8 channels 12-bit ADC controller with resistance
touch screen functionality. It also integrates UART, SPI/MICROWIRE, I2C, CAN, LIN, PWM,
Timer, WDT/Windowed-WDT, GPIO, Keypad, Smart Card I/F, 32.768 KHz XTL and RTC (Real
Time Clock).
In addition, the NUC970 series integrates a DRAM I/F, that runs up to 150MHz with supporting
DDR2 type SDRAM, and an External Bus Interface (EBI) that supports SRAM and external device
with DMA request and ack.

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2 FEATURES
NUC970 Series Features2.1
Core
–ARM® ARM926EJ-Sprocessor core runs up to 300 MHz
–Support 16 KB instruction cache and 16 KB data cache
–Support MMU
–Support JTAG Debug interface
External Bus Interface (EBI)
–Support SRAM and external I/O devices
–Support 8/16-bit data bus width
–Support up to five chip selects for SRAM and external I/O devices
–Support programmable access cycle
–Support four 32-bit write buffers
DDR SDRAM Controller
–Support DDR, DDR2 and LPDDR SDRAM
–Clock speed up to 150 MHz
–Support 16-bit data bus width
–Support two chip selects
–Support total memory size up to 256M bytes (each chip select for 128M bytes)
Embedded SRAM and ROM
–Support 56K bytes embedded SRAM
–Support 16K bytes Internal Boot ROM (IBR)
–Support up to four booting modes
–Boot from USB
–Boot from eMMC
–Boot from NAND Flash
–Boot from SPI Flash
Clock Control
–Support two PLLs, up to 500 MHz, for high performance system operation
–External 12 MHz high speed crystal input for precise timing operation
–External 32.768 kHz low speed crystal input for RTC function and low speed clock
source
Ethernet MAC Controller
–Support up to 2 Ethernet MAC controllers
–Support IEEE Std. 802.3 CSMA/CD protocol
–Support packet time stamping for IEEE Std. 1588 protocol
–Support 10 and 100 Mbps operations
–Support Half- and Full-duplex operations
–Support RMII interface to Ethernet physical layer PHY
–Support Ethernet physical layer PHY management through MDC and MDIO interface
–Support flow control in Full-duplex mode to receive, recognize and transmit PAUSE
frame
–Support CAM-like function to recognize 48-bit Ethernet MAC address
–Support Wake-On-LAN by detecting Magic Packet
–Support 256 bytes transmit FIFO and 256 bytes receive FIFO
–Support DMA function
–Support internal loop back mode for diagnostic
USB 2.0 Controller

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–Support USB Revision 2.0 specification
–Support one set of USB 2.0 High-Speed (HS) Device/Host with embedded transceiver
–Support one set of USB 2.0 High-Speed (HS) Host with embedded transceiver
–Support Control, Bulk, Interrupt, Isochronous and Split transfers
–Support USB host function compliant to Enhanced Host Controller Interface (EHCI) 1.0
specification to connect with USB 2.0 High-Speed (HS) device.
–Support USB host function compliant to Open Host Controller Interface (OHCI) 1.0
specification to connect with USB 1.1 Full-Speed (FS) and Low-Speed (LS) devices
–Support USB High-Speed (HS) and Full-Speed (FS) device function
–Support USB device function with 1 endpoint for Control IN/OUT transfers and 12
programmable endpoints for Bulk, Interrupt and Isochronous IN/OUT transfers
–Support suspend, resume and remote wake-up capability
–Support DMA function
–Support 2048 Bytes internal SRAM for USB host function and 4096 Bytes internal
SRAM for USB device function
Flash Memory Interface
–Support NAND flash interface
–Support 8-bit data bus width
–Support SLC and MLC type NAND flash device
–Support 512 B, 2 KB, 4 KB and 8 KB page size NAND flash device
–Support ECC4, ECC8, ECC12, ECC15 and ECC24 BCH algorithm for ECC code
generation, error detection and error correction.
–Support eMMC flash interface
–Support DMA function to accelerate the data transfer between system memory and
NAND and eMMC flash.
I2S Controller
–Support I2S interface
Support both mono and stereo
Support both record and playback
Support 8-bit, 16-bit 20-bit and 24-bit data precision
Support master and slave mode
–Support PCM interface
Support 2 slots mode to connect 2 device
Support 8-bit, 16-bit 20-bit and 24-bit data precision
Support master mode
–Support four 8x24 (8 24-bit) buffer for left/right channel record and left/right playback
–Support DMA function to accelerate the data transfer between system memory and
internal buffer
–Support 2 buffer address for left/right channel and 2 slots data transfer
LCD Display Controller
–Support 8/9/16/18/24-bit data with to connect with 80/68 series MPU type LCD module
–Support resolution up to 1024x768
–Support data format conversion from RGB444, RGB565, RGB666, RGB888, YUV422
and YUV444 to RGB444, RGB565, RGB666, RGB888, YUV422 and YUV444 for
display output
–Support CCIR-656 (with VSYNC, HSYNC and data enable sync signal) 8/16-bit YUV
data output to connect with external TV encoder
–Support 8/16 bpp OSD data with video overlay function to facilitate the diverse graphic
UI
–Support linear 1X to 8X image scaling up function
–Support Picture-In-Picture display function
–Support hardware cursor