Nuvoton NuMicro M0A21 Series Product manual

M0A21/M0A23 Series
May 06, 2022 Page 1of 746 Rev 1.02
M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
NuMicro®Family
Arm®Cortex®-M0-based Microcontroller
M0A21/M0A23 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller and
microprocessor based system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

M0A21/M0A23 Series
May 06, 2022 Page 2of 746 Rev 1.02
M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
TABLE OF CONTENTS
1GENERAL DESCRIPTION ............................................................................17
2FEATURES....................................................................................................18
3PARTS INFORMATION.................................................................................26
3.1 Package Type .............................................................................................................. 26
3.2 NuMicro® M0A21/M0A23 Series Selection Guide .................................................. 27
3.2.1 NuMicro® M0A21 Series ................................................................................................27
3.2.2 NuMicro® M0A23 Series ................................................................................................27
3.2.3 NuMicro® M0A21/M0A23 Selection Code ..................................................................28
4PIN CONFIGURATION ..................................................................................29
4.1 Pin Configuration ......................................................................................................... 29
4.1.1 M0A21 Series Pin Diagram...........................................................................................29
4.1.2 M0A21 Series Function Pin Table................................................................................30
4.1.3 M0A23 Series Pin Diagram...........................................................................................38
4.1.4 M0A23 Series Function Pin Table................................................................................40
4.2 Pin Description............................................................................................................. 44
4.2.1 M0A21/M0A23 Series Pin Description........................................................................44
4.2.2 M0A21/M0A23 Series Multi-function Summary Table...............................................62
4.2.3 M0A21/M0A23 Series Multi-function Summary Table Sorted by GPIO .................80
5BLOCK DIAGRAM.........................................................................................98
6FUNCTIONAL DESCRIPTION.......................................................................99
6.1 Arm® Cortex®-M0 Core ............................................................................................... 99
6.2 System Manager........................................................................................................ 101
6.2.1 Overview........................................................................................................................101
6.2.2 System Reset................................................................................................................101
6.2.3 System Power Distribution..........................................................................................107
6.2.4 Power Modes and Wake-up Sources........................................................................107
6.2.5 System Memory Map...................................................................................................111
6.2.6 SRAM Memory Orginization .......................................................................................113
6.2.7 Chip Bus Matrix ............................................................................................................114
6.2.8 IRC Auto Trim................................................................................................................114
6.2.9 Register Lock Control ..................................................................................................115
6.2.10UART0_TXD/USCI0_DAT0 Modulation with PWM.................................................115
6.2.11Register Map.................................................................................................................116
6.2.12Register Description.....................................................................................................118
6.2.13System Timer (SysTick)...............................................................................................151
6.2.14Nested Vectored Interrupt Controller (NVIC)............................................................156
6.2.15System Control Register .............................................................................................172
6.3 Clock Controller ......................................................................................................... 182

M0A21/M0A23 Series
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M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
6.3.1 Overview........................................................................................................................182
6.3.2 Clock Generator............................................................................................................183
6.3.3 System Clock and SysTick Clock...............................................................................185
6.3.4 Peripherals Clock .........................................................................................................186
6.3.5 Power-down Mode Clock ............................................................................................186
6.3.6 Clock Output..................................................................................................................187
6.3.7 Register Map.................................................................................................................188
6.3.8 Register Description.....................................................................................................189
6.4 Flash Memory Controller (FMC).............................................................................. 208
6.4.1 Overview........................................................................................................................208
6.4.2 Features.........................................................................................................................208
6.4.3 Block Diagram...............................................................................................................208
6.4.4 Functional Description .................................................................................................210
6.4.5 Register Map.................................................................................................................227
6.4.6 Register Description.....................................................................................................228
6.5 General Purpose I/O (GPIO) ................................................................................... 237
6.5.1 Overview.......................................................................................................................237
6.5.2 Features........................................................................................................................237
6.5.3 Block Diagram.............................................................................................................238
6.5.4 Basic Configuration...................................................................................................238
6.5.5 Functional Description .............................................................................................238
6.5.6 Register Map................................................................................................................243
6.5.7 Register Description..................................................................................................245
6.6 PDMA Controller (PDMA)......................................................................................... 259
6.6.1 Overview........................................................................................................................259
6.6.2 Features.........................................................................................................................259
6.6.3 Block Diagram...............................................................................................................259
6.6.4 Basic Configuration......................................................................................................259
6.6.5 Functional Description .................................................................................................260
6.6.6 Register Map.................................................................................................................266
6.6.7 Register Description.....................................................................................................267
6.7 Timer Controller (TMR)............................................................................................. 294
6.7.1 Overview........................................................................................................................294
6.7.2 Features.........................................................................................................................294
6.7.4 Block Diagram...............................................................................................................295
6.7.5 Basic Configuration......................................................................................................296
6.7.6 Functional Description .................................................................................................297
6.7.7 Register Map.................................................................................................................304
6.7.8 Register Description.....................................................................................................306
6.8 Watchdog Timer (WDT)............................................................................................ 317
6.8.1 Overview........................................................................................................................317

M0A21/M0A23 Series
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M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
6.8.2 Features.........................................................................................................................317
6.8.3 Block Diagram...............................................................................................................317
6.8.4 Basic Configuration......................................................................................................317
6.8.5 Functional Description .................................................................................................318
6.8.6 Register Map.................................................................................................................321
6.8.7 Register Description.....................................................................................................322
6.9 Window Watchdog Timer (WWDT)......................................................................... 326
6.9.1 Overview........................................................................................................................326
6.9.2 Features.........................................................................................................................326
6.9.3 Block Diagram...............................................................................................................326
6.9.4 Basic Configuration......................................................................................................326
6.9.5 Functional Description .................................................................................................327
6.9.6 Register Map.................................................................................................................331
6.9.7 Register Description.....................................................................................................332
6.10 PWM Generator and Capture Timer (PWM) ................................................... 337
6.10.1Overview........................................................................................................................337
6.10.2Features.........................................................................................................................337
6.10.3Block Diagram...............................................................................................................338
6.10.4Basic Configuration......................................................................................................341
6.10.5Functional Description .................................................................................................343
6.10.6Register Map.................................................................................................................365
6.10.7Register Description.....................................................................................................368
6.11 UART Interface Controller (UART).................................................................... 416
6.11.1Overview........................................................................................................................416
6.11.2Features.........................................................................................................................416
6.11.3Block Diagram...............................................................................................................417
6.11.4Basic Configuration......................................................................................................420
6.11.5Functional Description .................................................................................................421
6.11.6Register Map.................................................................................................................446
6.11.7Register Description.....................................................................................................448
6.12 USCI - Universal Serial Control Interface Controller (USCI)......................... 485
6.12.1Overview........................................................................................................................485
6.12.2Features.........................................................................................................................485
6.12.3Block Diagram...............................................................................................................485
6.12.4Functional Description .................................................................................................485
6.13 USCI – UART Mode............................................................................................ 496
6.13.1Overview........................................................................................................................496
6.13.2Features.........................................................................................................................496
6.13.3Block Diagram...............................................................................................................496
6.13.4Basic Configuration......................................................................................................496
6.13.5Functional Description .................................................................................................498

M0A21/M0A23 Series
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M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
6.13.6Register Map.................................................................................................................507
6.13.7Register Description.....................................................................................................508
6.14 USCI - SPI Mode ................................................................................................. 529
6.14.1Overview........................................................................................................................529
6.14.2Features.........................................................................................................................529
6.14.3Block Diagram...............................................................................................................530
6.14.4Basic Configuration......................................................................................................530
6.14.5Functional Description .................................................................................................531
6.14.6Register Map.................................................................................................................543
6.14.7Register Description.....................................................................................................545
6.15 USCI - I2C Mode .................................................................................................. 567
6.15.1Overview........................................................................................................................567
6.15.2Features.........................................................................................................................567
6.15.3Block Diagram...............................................................................................................568
6.15.4Basic Configuration......................................................................................................568
6.15.5START or Repeated START Signal ...........................................................................569
6.15.6Register Map.................................................................................................................587
6.15.7Register Description.....................................................................................................588
6.16 Controller Area Network (CAN) ......................................................................... 607
6.16.1Overview........................................................................................................................607
6.16.2Features.........................................................................................................................607
6.16.3Block Diagram...............................................................................................................607
6.16.4Basic Configuration......................................................................................................608
6.16.5Functional Description .................................................................................................609
6.16.6Test Mode ......................................................................................................................610
6.16.7CAN Communications .................................................................................................612
6.16.8Register Map.................................................................................................................628
6.16.9Register Description.....................................................................................................633
6.17 CRC Controller (CRC) ........................................................................................ 667
6.17.1Overview........................................................................................................................667
6.17.2Features.........................................................................................................................667
6.17.3Block Diagram...............................................................................................................667
6.17.4Basic Configuration......................................................................................................667
6.17.5Functional Description .................................................................................................668
6.17.6Register Map.................................................................................................................670
6.17.7Register Description.....................................................................................................671
6.18 Hardware Divider (HDIV).................................................................................... 676
6.18.1Overview........................................................................................................................676
6.18.2Features.........................................................................................................................676
6.18.3Basic Configuration......................................................................................................676
6.18.4Functional Description .................................................................................................676

M0A21/M0A23 Series
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M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
6.18.5Register Map.................................................................................................................677
6.18.6Register Description.....................................................................................................678
6.19 Analog-to-Digital Converter (ADC).................................................................... 683
6.19.1Overview........................................................................................................................683
6.19.2Features.........................................................................................................................683
6.19.3Block Diagram...............................................................................................................684
6.19.4Basic Configuration......................................................................................................684
6.19.5Functional Description .................................................................................................684
6.19.6Register Map.................................................................................................................692
6.19.7Register Description.....................................................................................................694
6.20 Digital to Analog Converter (DAC) .................................................................... 708
6.20.1Overview........................................................................................................................708
6.20.2Features.........................................................................................................................708
6.20.3Block Diagram...............................................................................................................708
6.20.4Basic Configuration......................................................................................................709
6.20.5Functional Description .................................................................................................709
6.20.6Register Map.................................................................................................................713
6.20.7Register Description.....................................................................................................714
6.21 Analog Comparator Controller (ACMP)............................................................ 721
6.21.1Overview........................................................................................................................721
6.21.2Features.........................................................................................................................721
6.21.3Block Diagram...............................................................................................................721
6.21.4Basic Configuration......................................................................................................722
6.21.5Functional Description .................................................................................................723
6.21.6Register Map.................................................................................................................728
6.21.7Register Description.....................................................................................................729
6.22 Peripherals Interconnection ............................................................................... 736
6.22.1Overview........................................................................................................................736
6.22.2Peripherals Interconnect Matrix Table.......................................................................736
6.22.3Functional Description .................................................................................................736
7APPLICATION CIRCUIT..............................................................................738
7.1 Power Supply Scheme ............................................................................................. 738
7.2 Peripheral Application Scheme ............................................................................... 739
8ELECTRICAL CHARACTERISTICS............................................................740
9PACKAGE DIMENSIONS............................................................................741
9.1 SSOP 20 (5.3x7.2x1.75 mm)................................................................................... 741
9.2 TSSOP 28 (4.4x9.7x1.0 mm)................................................................................... 742
10ABBREVIATIONS........................................................................................743
10.1 Abbreviations........................................................................................................ 743

M0A21/M0A23 Series
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M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
11REVISION HISTORY ...................................................................................745

M0A21/M0A23 Series
May 06, 2022 Page 8of 746 Rev 1.02
M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
LIST OF FIGURES
Figure 4.1-1 M0A21 Series SSOP 20-pin Diagram ....................................................................... 29
Figure 4.1-2 M0A21 Series TSSOP 28-pin Diagram..................................................................... 30
Figure 4.1-3 M0A23 Series SSOP 20-pin Diagram ....................................................................... 38
Figure 4.1-4 M0A23 Series TSSOP 28-pin Diagram..................................................................... 39
Figure 4.2-1 NuMicro®M0A21/M0A23 Block Diagram.................................................................. 98
Figure 6.1-1 Functional Block Diagram.......................................................................................... 99
Figure 6.2-1 System Reset Sources............................................................................................ 102
Figure 6.2-2 nRESET Reset Waveform....................................................................................... 104
Figure 6.2-3 nRESET Reset Mode Enable Control Waveform.................................................... 104
Figure 6.2-4 Power-on Reset (POR) Waveform.......................................................................... 105
Figure 6.2-5 Low Voltage Reset (LVR) Waveform....................................................................... 105
Figure 6.2-6 Brown-out Detector (BOD) Waveform..................................................................... 106
Figure 6.2-7 NuMicro®M0A21/M0A23 Power Distribution Diagram............................................ 107
Figure 6.2-8 Power Mode State Machine .................................................................................... 109
Figure 6.2-9 SRAM Memory Organization................................................................................... 113
Figure 6.2-10 NuMicro®M0A21/M0A23 Bus Matrix Diagram...................................................... 114
Figure 6.3-1 Clock Generator Global View Diagram.................................................................... 183
Figure 6.3-2 Clock Generator Block Diagram.............................................................................. 184
Figure 6.3-3 System Clock Block Diagram .................................................................................. 185
Figure 6.3-4 HXT Stop Protect Procedure................................................................................... 186
Figure 6.3-5 SysTick Clock Control Block Diagram..................................................................... 186
Figure 6.3-6 Clock Output Block Diagram ................................................................................... 187
Figure 6.4-116/32 KB Flash Memory Control Block Diagram...................................................... 209
Figure 6.4-2 Data Flash Shared with APROM............................................................................. 210
Figure 6.4-3 16/32 Kbytes Flash Memory Map............................................................................ 216
Figure 6.4-4 16/32 Kbytes Flash System Memory Map with IAP Mode ...................................... 217
Figure 6.4-5 LDROM with IAP Mode............................................................................................ 218
Figure 6.4-6 APROM with IAP Mode ........................................................................................... 218
Figure 6.4-7 16/32 Kbytes Flash System Memory Map without IAP Mode ................................. 219
Figure 6.4-8 Boot Source Selection............................................................................................. 220
Figure 6.4-9 ISP Procedure Example.......................................................................................... 222
Figure 6.4-10 Example for Accelerating Interrupt by VECMAP................................................... 223
Figure 6.4-11 ISP 32-bit Programming Procedure....................................................................... 224
Figure 6.4-12 CRC-32 Checksum Calculation............................................................................. 225
Figure 6.4-13 CRC-32 Checksum Calculation Flow.................................................................... 226
Figure 6.5-1 GPIO Controller Block Diagram............................................................................... 238

M0A21/M0A23 Series
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M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
Figure 6.5-2 Input Mode............................................................................................................... 239
Figure 6.5-3 Push-Pull Output...................................................................................................... 239
Figure 6.5-4 Open-Drain Output .................................................................................................. 240
Figure 6.5-5 Quasi-Bidirectional I/O Mode................................................................................... 240
Figure 6.5-6 GPIO Rising Edge Trigger Interrupt ........................................................................ 241
Figure 6.5-7 GPIO Falling Edge Trigger Interrupt........................................................................ 242
Figure 6.6-1 PDMA Controller Block Diagram............................................................................. 259
Figure 6.6-2 Descriptor Table Entry Structure............................................................................. 260
Figure 6.6-3 Basic Mode Finite State Machine............................................................................ 261
Figure 6.6-4 Descriptor Table Link List Structure ........................................................................ 262
Figure 6.6-5 Scatter-Gather Mode Finite State Machine............................................................. 263
Figure 6.6-6 Example of Single Transfer Type and Burst Transfer Type in Basic Mode ............ 264
Figure 6.6-7 Example of PDMA Channel 0 Time-out Counter Operation.................................... 265
Figure 6.7-1 Timer Controller Block Diagram .............................................................................. 295
Figure 6.7-2 Clock Source of Timer Controller ............................................................................ 296
Figure 6.7-3 Continuous Counting Mode..................................................................................... 298
Figure 6.7-4 External Capture Mode............................................................................................ 299
Figure 6.7-5 Reset Counter Mode................................................................................................ 300
Figure 6.7-6 Internal Timer Trigger.............................................................................................. 301
Figure 6.7-7 Inter-Timer Trigger Capture Timing......................................................................... 302
Figure 6.8-1 Watchdog Timer Block Diagram.............................................................................. 317
Figure 6.8-2 Watchdog Timer Clock Control................................................................................ 318
Figure 6.8-3 Watchdog Timer Time-out Interval and Reset Period Timing ................................. 319
Figure 6.9-1 WWDT Block Diagram............................................................................................. 326
Figure 6.9-2 WWDT Clock Control............................................................................................... 326
Figure 6.9-3 WWDT Reset and Reload Behavior........................................................................ 328
Figure 6.9-4 WWDT Reload Counter When CNTDAT > CMPDAT ............................................. 328
Figure 6.9-5 WWDT Reload Counter When WWDT_CNT < WINCMP....................................... 329
Figure 6.9-6 WWDT Interrupt and Reset Signals ........................................................................ 329
Figure 6.10-1 PWM Generator Overview Block Diagram............................................................ 338
Figure 6.10-2 PWM System Clock Source Control...................................................................... 339
Figure 6.10-3 PWM Clock Source Control................................................................................... 340
Figure 6.10-4 PWM Independent Mode Architecture Diagram.................................................... 340
Figure 6.10-5 PWM Complementary Mode Architecture Diagram .............................................. 341
Figure 6.10-6 PWM0_CH0 Prescaler Waveform in Up Counter Type......................................... 344
Figure 6.10-7 PWMx Counter Waveform When Setting Clear Counter....................................... 344
Figure 6.10-8 PWM Up Counter Type.......................................................................................... 345

M0A21/M0A23 Series
May 06, 2022 Page 10 of 746 Rev 1.02
M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
Figure 6.10-9 PWM Down Counter Type..................................................................................... 345
Figure 6.10-10 PWM Up-Down Counter Type............................................................................. 346
Figure 6.10-11 PWM Compared point Events in Up-Down Counter Type .................................. 347
Figure 6.10-12 PWM Double Buffering Illustration....................................................................... 348
Figure 6.10-13 Period Loading in Up-Count Mode...................................................................... 348
Figure 6.10-14 Immediately Loading in Up-Count Mode............................................................. 349
Figure 6.10-15 Center Loading in Up-Down-Count Mode........................................................... 350
Figure 6.10-16 PWM Pulse Generation....................................................................................... 351
Figure 6.10-17 PWM 0% to 100% Pulse Generation................................................................... 351
Figure 6.10-18 PWM Independent Mode Waveform................................................................... 352
Figure 6.10-19 PWM Complementary Mode Waveform.............................................................. 353
Figure 6.10-20 PWMx_CH0 Output Control in Independent Mode ............................................. 353
Figure 6.10-21 PWMx_CH0 and PWMx_CH1 Output Control in Complementary Mode............ 354
Figure 6.10-22 Dead-Time Insertion............................................................................................ 354
Figure 6.10-23 Illustration of Mask Control Waveform................................................................. 355
Figure 6.10-24 Brake Noise Filter Block Diagram........................................................................ 355
Figure 6.10-25 Brake Block Diagram for PWMx_CH0 and PWMx_CH1 Pair ............................. 356
Figure 6.10-26 Edge Detector Waveform for PWMx_CH0 and PWMx_CH1 Pair....................... 357
Figure 6.10-27 Level Detector Waveform for PWMx_CH0 and PWMx_CH1 Pair ...................... 357
Figure 6.10-28 Brake Source Block Diagram .............................................................................. 358
Figure 6.10-29 Brake System Fail Block Diagram....................................................................... 358
Figure 6.10-30 Initial State and Polarity Control with Rising Edge Dead-Time Insertion ............ 359
Figure 6.10-31 PWM_CH0 and PWM_CH1 Pair Interrupt Architecture Diagram........................ 360
Figure 6.10-32 PWMx_CH0 and PWMx_CH1 Pair Trigger ADC Block Diagram........................ 361
Figure 6.10-33 PWM Trigger ADC in Up-Down Counter Type Timing Waveform....................... 361
Figure 6.10-34 PWM_CH0 Capture Block Diagram .................................................................... 362
Figure 6.10-35 Capture Operation Waveform.............................................................................. 363
Figure 6.10-36 Capture PDMA Operation Waveform of Channel 0............................................. 364
Figure 6.11-1 UART Clock Control Diagram................................................................................ 418
Figure 6.11-2 UART Block Diagram............................................................................................. 419
Figure 6.11-3 Auto-Baud Rate Measurement.............................................................................. 425
Figure 6.11-4 Transmit Delay Time Operation............................................................................. 425
Figure 6.11-5 UART nCTS Wake-up Case1................................................................................ 426
Figure 6.11-6 UART nCTS Wake-up Case2................................................................................ 426
Figure 6.11-7 UART Data Wake-up............................................................................................. 427
Figure 6.11-8 UART Received Data FIFO Reached Threshold Wake-up................................... 427
Figure 6.11-9 UART RS-485 AAD Mode Address Match Wake-up............................................. 428

M0A21/M0A23 Series
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M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
Figure 6.11-10 UART Received Data FIFO threshold time-out wake-up .................................... 428
Figure 6.11-11 Auto-Flow Control Block Diagram ....................................................................... 432
Figure 6.11-12 UART nCTS Auto-Flow Control Enabled............................................................. 432
Figure 6.11-13 UART nRTS Auto-Flow Control Enabled............................................................. 433
Figure 6.11-14 UART nRTS Auto-Flow with Software Control.................................................... 433
Figure 6.11-15 IrDA Control Block Diagram ................................................................................ 434
Figure 6.11-16 IrDA TX/RX Timing Diagram ............................................................................... 435
Figure 6.11-17 Structure of LIN Frame........................................................................................ 435
Figure 6.11-18 Structure of LIN Byte ........................................................................................... 436
Figure 6.11-19 Break Detection in LIN Mode............................................................................... 438
Figure 6.11-20 LIN Frame ID and Parity Format ......................................................................... 438
Figure 6.11-21 LIN Sync Field Measurement.............................................................................. 440
Figure 6.11-22 UART_BAUD Update Sequence in AR mode if SLVDUEN is 1 ......................... 441
Figure 6.11-23 UART_BAUD Update Sequence in AR mode if SLVDUEN is 0 ......................... 441
Figure 6.11-24 RS-485 nRTS Driving Level in Auto Direction Mode........................................... 443
Figure 6.11-25 RS-485 nRTS Driving Level with Software Control............................................. 444
Figure 6.11-26 Structure of RS-485 Frame ................................................................................. 444
Figure 6.12-1 USCI Block Diagram.............................................................................................. 485
Figure 6.12-2 Input Conditioning for USCIx_DAT[1:0] and USCIx_CTL[1:0] .............................. 486
Figure 6.12-3 Input Conditioning for USCIx_CLK........................................................................ 487
Figure 6.12-4 Block Diagram of Data Buffering........................................................................... 488
Figure 6.12-5 Data Access Structure........................................................................................... 489
Figure 6.12-6 Transmit Data Path................................................................................................ 489
Figure 6.12-7 Receive Data Path................................................................................................. 490
Figure 6.12-8 Protocol-Relative Clock Generator........................................................................ 491
Figure 6.12-9 Basic Clock Divider Counter.................................................................................. 492
Figure 6.12-10 Block of Timing Measurement Counter............................................................... 492
Figure 6.12-11 Sample Time Counter.......................................................................................... 493
Figure 6.12-12 Event and Interrupt Structure .............................................................................. 494
Figure 6.13-1 USCI-UART Mode Block Diagram......................................................................... 496
Figure 6.13-2 UART Signal Connection for Full-Duplex Communication.................................... 498
Figure 6.13-3 UART Standard Frame Format ............................................................................. 499
Figure 6.13-4 UART Bit Timing (data sample time)..................................................................... 501
Figure 6.13-5 UART Auto Baud Rate Control.............................................................................. 503
Figure 6.13-6 Incoming Data Wake-Up ....................................................................................... 504
Figure 6.13-7 nCTS Wake-Up Case 1......................................................................................... 504
Figure 6.13-8 nCTS Wake-Up Case 2......................................................................................... 504

M0A21/M0A23 Series
May 06, 2022 Page 12 of 746 Rev 1.02
M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
Figure 6.14-1 SPI Master Mode Application Block Diagram........................................................ 529
Figure 6.14-2 SPI Slave Mode Application Block Diagram.......................................................... 529
Figure 6.14-3 USCI SPI Mode Block Diagram............................................................................. 530
Figure 6.14-44-Wire Full-Duplex SPI Communication Signals (Master Mode) ........................... 532
Figure 6.14-54-Wire Full-Duplex SPI Communication Signals (Slave Mode).............................. 532
Figure 6.14-6 SPI Communication with Different SPI Clock Configuration (SCLKMODE=0x0).. 533
Figure 6.14-7 SPI Communication with Different SPI Clock Configuration (SCLKMODE=0x1).. 534
Figure 6.14-8 SPI Communication with Different SPI Clock Configuration (SCLKMODE=0x2).. 534
Figure 6.14-9 SPI Communication with Different SPI Clock Configuration (SCLKMODE=0x3).. 535
Figure 6.14-1016-bit Data Length in One Word Transaction with MSB First Format.................. 536
Figure 6.14-11 Word Suspend Interval between Two Transaction Words.................................. 536
Figure 6.14-12 Auto Slave Select (SUSPITV ≧0x3).................................................................. 537
Figure 6.14-13 Auto Slave Select (SUSPITV < 0x3) ................................................................... 537
Figure 6.14-14 One Output Data Channel Half-duplex (SPI Master Mode) ................................ 538
Figure 6.14-15 One Input Data Channel Half-duplex (SPI Master Mode)................................... 539
Figure 6.14-16 SPI Timing in Master Mode ................................................................................. 540
Figure 6.14-17 SPI Timing in Master Mode (Alternate Phase of Serial Bus Clock) .................... 541
Figure 6.14-18 SPI Timing in Slave Mode................................................................................... 541
Figure 6.14-19 SPI Timing in Slave Mode (Alternate Phase of Serial Bus Clock) ...................... 542
Figure 6.15-1 I2C Bus Timing....................................................................................................... 567
Figure 6.15-2 USCI I²C Mode Block Diagram.............................................................................. 568
Figure 6.15-3 I2C Protocol............................................................................................................ 569
Figure 6.15-4 START and STOP Conditions............................................................................... 570
Figure 6.15-5 Bit Transfer on the I2C Bus.................................................................................... 571
Figure 6.15-6 Acknowledge on the I2C Bus................................................................................. 571
Figure 6.15-7 Arbitration Lost....................................................................................................... 572
Figure 6.15-8 Control I2C Bus According to Current I2C Status................................................... 575
Figure 6.15-9 Master Transmits Data to Slave with a 7-bit Address ........................................... 575
Figure 6.15-10 Master Reads Data from Slave with a 7-bit Address........................................... 575
Figure 6.15-11 Master Transmits Data to Slave by 10-bit Address............................................. 575
Figure 6.15-12 Master Reads Data from Slave by 10-bit Address .............................................. 576
Figure 6.15-13 Master Transmitter Mode Control Flow with 7-bit Address ................................. 576
Figure 6.15-14 Master Receiver Mode Control Flow with 7-bit Address ..................................... 577
Figure 6.15-15 Master Transmitter Mode Control Flow with 10-bit Address ............................... 578
Figure 6.15-16 Master Recevier Mode Control Flow with 10-bit Address ................................... 579
Figure 6.15-17 Save Mode Control Flow with 7-bit Address ....................................................... 580
Figure 6.15-18 Save Mode Control Flow with 10-bit Address ..................................................... 581

M0A21/M0A23 Series
May 06, 2022 Page 13 of 746 Rev 1.02
M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
Figure 6.15-19 GC Mode with 7-bit Address................................................................................ 582
Figure 6.15-20 Setup Time Wrong Adjustment............................................................................ 584
Figure 6.15-21 Hold Time Wrong Adjustment.............................................................................. 584
Figure 6.15-22 I2C Time-out Count Block Diagram ..................................................................... 585
Figure 6.15-23 EEPROM Random Read..................................................................................... 586
Figure 6.15-24 Protocol of EEPROM Random Read................................................................... 586
Figure 6.16-1 CAN Peripheral Block Diagram............................................................................. 608
Figure 6.16-2 CAN Core in Silent Mode ...................................................................................... 610
Figure 6.16-3 CAN Core in Loop Back Mode .............................................................................. 611
Figure 6.16-4 CAN Core in Loop Back Mode Combined with Silent Mode ................................. 611
Figure 6.16-5 Data Transfer between IFn Registers and Message............................................. 613
Figure 6.16-6 Application Software Handling of a FIFO Buffer.................................................... 618
Figure 6.16-7 Bit Timing............................................................................................................... 620
Figure 6.16-8 Propagation Time Segment................................................................................... 621
Figure 6.16-9 Synchronization on “late” and “early” Edges ......................................................... 622
Figure 6.16-10 Filtering of Short Dominant Spikes...................................................................... 623
Figure 6.16-11 Structure of the CAN Core’s CAN Protocol Controller ........................................ 624
Figure 6.17-1 CRC Generator Block Diagram............................................................................. 667
Figure 6.17-2 CHECKSUM Bit Order Reverse Functional Block................................................. 668
Figure 6.17-3 Write Data Bit Order Reverse Functional Block.................................................... 669
Figure 6.18-1 Hardware Divider Operation Flow ......................................................................... 676
Figure 6.19-1 AD Controller Block Diagram................................................................................. 684
Figure 6.19-2 ADC Peripheral Clock Control............................................................................... 685
Figure 6.19-3 Single Mode Conversion Timing Diagram............................................................. 686
Figure 6.19-4 Burst Mode Conversion Timing Diagram............................................................... 687
Figure 6.19-5 Single-Cycle Scan Mode on Enabled Channels Timing Diagram......................... 688
Figure 6.19-6 Continuous Scan Mode on Enabled Channels Timing Diagram........................... 689
Figure 6.19-7 A/D Conversion Result Monitor Logic Diagram..................................................... 690
Figure 6.19-8 A/D Controller Interrupt.......................................................................................... 691
Figure 6.19-9 Conversion Result Mapping Diagram of ADC Single-end Input............................ 695
Figure 6.19-10 Conversion Result Mapping Diagram of ADC Differential Input.......................... 696
Figure 6.20-1 Digital-to-Analog Converter Block Diagram........................................................... 708
Figure 6.20-2 DAC Conversion Started by Software Write Trigger............................................. 709
Figure 6.20-3 DAC Conversion Started by Hardware Trigger Event........................................... 710
Figure 6.20-4 DAC PDMA Underrun Condition Example............................................................ 711
Figure 6.20-5 DAC Continuous Conversion with Software PDMA Mode .................................... 711
Figure 6.20-6 DAC Interrupt Source ............................................................................................ 712

M0A21/M0A23 Series
May 06, 2022 Page 14 of 746 Rev 1.02
M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
Figure 6.21-1 Analog Comparator Block Diagram....................................................................... 722
Figure 6.21-2 Comparator Hysteresis Function of ACMP0 ......................................................... 723
Figure 6.21-3 Window Latch Mode.............................................................................................. 724
Figure 6.21-4 Filter Function Example......................................................................................... 724
Figure 6.21-5 Comparator Controller Interrupt............................................................................. 725
Figure 6.21-6 Comparator Reference Voltage Block Diagram.................................................... 725
Figure 6.21-7 Example of Window Compare Mode..................................................................... 726
Figure 6.21-8 Example of Window Compare Mode..................................................................... 727

M0A21/M0A23 Series
May 06, 2022 Page 15 of 746 Rev 1.02
M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
List of Tables
Table 1-1 NuMicro®M0A21/M0A23 Series Key Features Table................................................... 17
Table 6.2-1 Reset Value of Registers.......................................................................................... 103
Table 6.2-2 Power Mode Table.................................................................................................... 108
Table 6.2-3 Power Mode Difference Table.................................................................................. 108
Table 6.2-4 Power Mode Difference Table.................................................................................. 108
Table 6.2-5 Clocks in Power Modes............................................................................................ 110
Table 6.2-6 Condition of Entering Power-down Mode Again....................................................... 111
Table 6.2-7 Address Space Assignments for On-Chip Controllers.............................................. 112
Table 6.2-8 Exception Model ....................................................................................................... 157
Table 6.2-9 Interrupt Number Table............................................................................................. 158
Table 6.2-10 Priority Grouping..................................................................................................... 177
Table 6.4-1 Vector Mapping Support........................................................................................... 220
Table 6.4-2 ISP Command List.................................................................................................... 221
Table 6.4-3 FMC Control Registers for Flash Programming........................................................ 223
Table 6.6-1 Channel Priority Table .............................................................................................. 261
Table 6.7-1 Timer0 ~ Timer3 MFP Table..................................................................................... 297
Table 6.8-1 Watchdog Timer Time-out Interval Period Selection................................................ 319
Table 6.9-1 WWDT Prescaler Value Selection............................................................................ 327
Table 6.9-2 CMPDAT Setting Limitation...................................................................................... 330
Table 6.10-1 PWM Clock Source Control Registers Setting Table ............................................. 339
Table 6.10-2 PWM Pulse Generation Event Priority for Up-Counter........................................... 351
Table 6.10-3 PWM Pulse Generation Event Priority for Down-Counter...................................... 352
Table 6.10-4 PWM Pulse Generation Event Priority for Up-Down-Counter................................ 352
Table 6.11-1 NuMicro®M0A21/M0A23 Series UART Features................................................... 417
Table 6.11-2 UART Interrupt........................................................................................................ 420
Table 6.11-3 UART Interface Controller Pin................................................................................ 421
Table 6.11-4 UART Controller Baud Rate Equation Table.......................................................... 422
Table 6.11-5 UART Controller Baud Rate Parameter Setting Example Table............................ 422
Table 6.11-6 UART Controller Baud Rate Register Setting Example Table................................ 423
Table 6.11-7 Baud Rate Compensation Example Table 1 .......................................................... 423
Table 6.11-8 Baud Rate Compensation Example Table 2 .......................................................... 424
Table 6.11-9 UART controller Interrupt Source and Flag List...................................................... 430
Table 6.11-10 UART Line Control of Word and Stop Length Setting.......................................... 431
Table 6.11-11 UART Line Control of Parity Bit Setting................................................................ 431
Table 6.11-12 LIN Header Selection in Master Mode.................................................................. 436
Table 6.12-1 Input Signals for Different Protocols....................................................................... 486

M0A21/M0A23 Series
May 06, 2022 Page 16 of 746 Rev 1.02
M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
Table 6.12-2 Output Signals for Different Protocols .................................................................... 487
Table 6.12-3 Data Transfer Events and Interrupt Handling......................................................... 494
Table 6.12-4 Protocol-specific Events and Interrupt Handling..................................................... 494
Table 6.13-1 Input Signals for UART Protocol............................................................................. 499
Table 6.13-2 Output Signals for Different Protocol...................................................................... 499
Table 6.14-1 Serial Bus Clock Configuration............................................................................... 533
Table 6.15-1 Relationship between I2C Baud Rate and PCLK.................................................... 584
Table 6.16-1 Initialization of a Transmit Object............................................................................ 615
Table 6.16-2 Initialization of a Receive Object............................................................................. 616
Table 6.16-3 CAN Bit Time Parameters ...................................................................................... 620
Table 6.16-4 CAN Register Map for Each Bit Function............................................................... 632
Table 6.16-5 Last Error Code....................................................................................................... 636
Table 6.16-6 Source of Interrupts ................................................................................................ 639
Table 6.16-7 IF1 and IF2 Message Interface Register................................................................ 642
Table 6.16-8 Structure of a Message Object in the Message Memory........................................ 656
Table 6.21-1 Truth Table of Window Compare Logic.................................................................. 726
Table 6.22-1 Peripherals Interconnect Matrix Table.................................................................... 736
Table 10.1-1 List of Abbreviations................................................................................................ 744

M0A21/M0A23 Series
May 06, 2022 Page 17 of 746 Rev 1.02
M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
1 GENERAL DESCRIPTION
The NuMicro®M0A21/M0A23 series is a 32-bit microcontroller based on Arm®Cortex®-M0 core. It
provides compact package with highly flexible digital pin function assignment, rich analog peripherals, -
40°C to 125°C operating temperature, 2.4V ~ 5.5V operating voltage, CAN 2.0B and LIN interface for
robust communication. The NuMicro®M0A23/M0A21 series targets robust and high operating
temperature applications, such as 24 GHz mmWave radar, Battery Management System (BMS), car
lighting, electric window lifter, and power seat.
The NuMicro®M0A21/M0A23 series provide SSOP20 and TSSOP28 package with rich analog and
digital functions, which are especially suitable for small form factor applications. SSOP20 provides up
to 18 IO pins and TSSOP28 provides up to 26 IO pins. Each IO pin of the M0A21/M0A23 series can be
arbitrarily assigned to digital peripherals, such as UART, SPI, and PWM. The M0A21/M0A23 series
provides rich analog functions including 17-ch 12-bit 500 KSPS ADC, 1 set of 5-bit DAC and 2 sets of
ACMP in both SSOP20 and TSSOP28 package. Moreover, it provides low voltage reset (LVR) and
brown-out detector (BOD) to ensure the system safety.
The NuMicro®M0A21/M0A23 series runs up to 48 MHz and supports hardware divider. It provides 32
Kbytes Flash memory, 4 Kbytes SRAM and 2 Kbytes LDROM for ISP (In-System Programming) feature
for easily firmware update. It is equipped with plenty of peripherals including up to four 32-bit timers, 6-
ch 16-bit PWM generators, 1 set of CAN 2.0B controller, 2 sets of LIN functions, 5-ch PDMA, 2 sets of
UART with One-Wire mode, IrDA and RS485 functions. Besides, the M0A21/M0A23 series provides
two sets of Universal Serial Control Interfaces (USCI) that can be configured as UART, SPI or I2C.
The package types of the M0A21/M0A23 series are included SSOP20 (5.3x7.2x1.75 mm) and
TSSOP28 (4.4x9.7x1.0 mm).
Product Line
CAN
UART
LIN
USCI
Timer
PWM
PDMA
ADC
ACMP
Divider
M0A21
0
2
2
2
4
6
5
17
2
1
M0A23
1
2
2
2
4
6
5
17
2
1
Table 1-1 NuMicro®M0A21/M0A23 Series Key Features Table
The M0A21/M0A23 is targeted at applications such as:
24GHz mmWave radar
BMS (Battery Management System)
Car lighting
Car windows
Power seat

M0A21/M0A23 Series
May 06, 2022 Page 18 of 746 Rev 1.02
M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
2 FEATURES
Core and System
Arm® Cortex®-M0
Arm®Cortex®-M0 core, running up to 48 MHz
Built-in Nested Vectored Interrupt Controller (NVIC)
24-bit system tick timer
Programmble and maskable interrupt
Low Power Sleep mode by WFI and WFE instructions
Brown-out Detector
(BOD)
Four-level BOD with brown-out interrupt and reset option.
(4.4V/3.7V/2.7V/2.3V)
Low Voltage Reset (LVR)
LVR with 2.22V threshold voltage level
Security
96-bit Unique ID (UID).
128-bit Unique Customer ID (UCID).
One built-in temperature sensor.
32-bit H/W Divider(HDIV)
Signed (two’s complement) integer calculation
32-bit dividend with 16-bit divisor calculation capacity
32-bit quotient and 32-bit remainder outputs (16-bit remainder
with sign extends to 32-bit)
6 HCLK clocks taken for one cycle calculation
Memories
Boot Loader
Nuvoton ISP (In-System-Programming) tool for firmware
upgrade via UART
ISP/IAP libraries
Flash
Up to 32 KB application ROM (APROM)
2 KB on-chip Flash for user-defined loader (LDROM)
All on-chip Flash support 512 bytes page erase
Fast Flash programming verification with CRC
On-chip Flash programming with In-Chip Programming (ICP),
In-System Programming (ISP) and In-Application Programming
(IAP) capabilities
Configurable boot up sources including boot loader, user-
defined loader (LDROM) or Application ROM (APROM)

M0A21/M0A23 Series
May 06, 2022 Page 19 of 746 Rev 1.02
M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
Data Flash with configurable memory size
2-wired ICP Flash updating through SWD interface
32-bit and multi-word Flash programming function
SRAM
Up to 4 KB embedded SRAM
Supports byte-, half-word- and word-access
Supports PDMA mode
Cyclic Redundancy
Calculation (CRC)
Supports CRC-CCITT, CRC-8, CRC-16 and CRC-32
polynomials
Programmable initial value
Programmable order reverse setting and one’s complement
setting for input data and CRC checksum
8-bit, 16-bit, and 32-bit data width
8-bit write mode with 1-AHB clock cycle operation
16-bit write mode with 2-AHB clock cycle operation
32-bit write mode with 4-AHB clock cycle operation
Uses DMA to write data with performing CRC operation
Peripheral DMA (PDMA)
Supports up to 5 independent configurable channels for
automatic data transfer between memories and peripherals
Basic and Scatter-Gather transfer modes
Each channel supports circular buffer management using
Scatter-Gather Transfer mode
Stride function for rectangle image data movement
Fixed-priority and Round-robin priorities modes
Single and burst transfer types
Byte-, half-word- and word tranfer unit with count up to 65536
Request source can be from software, UART, ADC, PWM and
Timer
Clocks
External Clock Source
4~24 MHz High-speed eXternal crystal oscillator (HXT) for
precise timing operation
32.768 kHz Low-speed eXternal crystal oscillator (LXT) for low-
power system operation
Supports clock failure detection for external crystal oscillators
and exception generatation (NMI)
Internal Clock Source
48 MHz High-speed Internal RC oscillator (HIRC) trimmed to

M0A21/M0A23 Series
May 06, 2022 Page 20 of 746 Rev 1.02
M0A21/M0A23SERIES TECHNICAL REFERENCE MANUAL
±0.25% accuracy that can optionally be used as a system clock
38.4 kHz Low-speed Internal RC oscillator (LIRC) for watchdog
timer and wakeup operation
Timers
32-bit Timer
Four sets of 32-bit timers with 24-bit up counter and one 8-bit
pre-scale counter from independent clock source
One-shot, Periodic, Toggle and Continuous Counting operation
modes
Supports event counting function to count the event from
external pins
Supports external capture pin for enhanced interval
measurement and resetting 24-bit up counter
Supports chip wake-up from Idle/Power-down mode if a timer
interrupt signal is generated
Timer interrupt flag or external capture interrupt flag to trigger
PWM, ADC and PDMA.
PWM
Three 16-bit counters with 12-bit prescale for six 48 MHz PWM
output channels.
Supports independent mode for PWM output/Capture input
channel
Supports complementary mode for 3 complementary paired
PWM output channel
Dead-time insertion with 12-bit resolution
Two compared values during one period
Supports 16-bit resolution PWM counter
Up, down or up-down PWM counter type
Supports mask function and tri-state enable for each PWM pin
Supports brake function
Up to 6 independent input capture channels with 16-bit
resolution counter
Counter synchronous start function
Able to trigger ADC to start conversion.
Watchdog
20-bit free running up counter for WDT time-out interval.
Selectable time-out interval (24 ~ 220) and the time-out interval
is 416us ~ 27.3 s if WDT_CLK = 38.4 kHz (LIRC).
System kept in reset state for a period of (1 / WDT_CLK) * 63.
Able to wake up from Power-down or Idle mode