Nuvoton NuMicro NUC126 Series Product manual

NUC126
Aug. 08, 2018 Page 1of 943 Rev 1.03
NUC126 SERIES TECHNICAL REFERENCE MANUAL
ARM CORTEX®-M
32-BIT MICROCONTROLLER
NuMicro®Family
NUC126 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

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TABLE OF CONTENTS
1GENERAL DESCRIPTION.............................................................................19
1.1 Key Feature and Application ......................................................................................19
2FEATURES.....................................................................................................20
2.1 NuMicro® NUC126 Features ......................................................................................20
3ABBREVIATIONS ..........................................................................................28
3.1 Abbreviations................................................................................................................28
4PARTS INFORMATION LIST AND PIN CONFIGURATION..........................30
4.1 NuMicro® NUC126 Selection Guide..........................................................................30
4.1.1 NuMicro® NUC126 Naming Rule ................................................................................. 30
4.1.2 NuMicro® NUC126 USB Series (M452 Compatible) Selection Guide ................... 31
4.2 Pin Configuration..........................................................................................................32
4.2.1 NuMicro® NUC126 USB Series QFN48 Pin Diagram............................................... 32
4.2.2 NuMicro® NUC126 USB Series LQFP48 Pin Diagram............................................. 33
4.2.3 NuMicro® NUC126 USB Series LQFP64 Pin Diagram............................................. 34
4.2.4 NuMicro® NUC126 USB Series LQFP100 Pin Diagram .......................................... 35
4.3 Pin Description .............................................................................................................36
4.3.1 NUC126 USB Series Pin Description ......................................................................... 36
4.3.2 GPIO Multi-function Pin Summary .............................................................................. 53
5BLOCK DIAGRAM.........................................................................................69
5.1 NuMicro® NUC126 Block Diagram............................................................................69
6FUNCTIONAL DESCRIPTION.......................................................................70
6.1 ARM® Cortex®-M0 Core ..............................................................................................70
6.2 System Manager..........................................................................................................72
6.2.1 Overview ......................................................................................................................... 72
6.2.2 System Reset ................................................................................................................. 72
6.2.3 Power Modes and Wake-up Sources.......................................................................... 79
6.2.4 System Power Distribution ........................................................................................... 82
6.2.5 System Memory Map..................................................................................................... 84
6.2.6 SRAM Memory Orginization......................................................................................... 86
6.2.7 Register Lock.................................................................................................................. 87
6.2.8 Auto Trim ......................................................................................................................... 87
6.2.9 UART1_TXD modulation with PWM ........................................................................... 88
6.2.10Voltage Detector (VDET) .............................................................................................. 89
6.2.11Register Map .................................................................................................................. 90
6.2.12Register Description ...................................................................................................... 92
6.2.13System Timer (SysTick) .............................................................................................. 133
6.2.14Nested Vectored Interrupt Controller (NVIC) ........................................................... 138

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6.2.15System Control............................................................................................................. 161
6.3 Clock Controller..........................................................................................................169
6.3.1 Overview ....................................................................................................................... 169
6.3.2 System Clock and SysTick Clock .............................................................................. 172
6.3.3 Peripherals Clock......................................................................................................... 173
6.3.4 Power-down Mode Clock............................................................................................ 174
6.3.5 Clock Output ................................................................................................................. 174
6.3.6 Register Map ................................................................................................................ 176
6.3.7 Register Description .................................................................................................... 177
6.4 Flash Memeory Controller (FMC)............................................................................205
6.4.1 Overview ....................................................................................................................... 205
6.4.2 Features ........................................................................................................................ 205
6.4.3 Block Diagram .............................................................................................................. 206
6.4.4 Functional Description................................................................................................. 207
6.4.5 Register Map ................................................................................................................ 229
6.4.6 Register Description .................................................................................................... 230
6.5 Analog Comparator Controller (ACMP)..................................................................247
6.5.1 Overview ....................................................................................................................... 247
6.5.2 Features ........................................................................................................................ 247
6.5.3 Block Diagram .............................................................................................................. 248
6.5.4 Basic Configuration...................................................................................................... 249
6.5.5 Functional Description................................................................................................. 249
6.5.6 Register Map ................................................................................................................ 254
6.5.7 Register Description .................................................................................................... 255
6.6 Analog-to-Digital Converter (ADC)..........................................................................262
6.6.1 Overview ....................................................................................................................... 262
6.6.2 Features ........................................................................................................................ 262
6.6.3 Block Diagram .............................................................................................................. 263
6.6.4 Basic Configuration...................................................................................................... 263
6.6.5 Functional Description................................................................................................. 264
6.6.6 Register Map ................................................................................................................ 272
6.6.7 Register Description .................................................................................................... 274
6.7 CRC Controller (CRC)...............................................................................................289
6.7.1 Overview ....................................................................................................................... 289
6.7.2 Features ........................................................................................................................ 289
6.7.3 Block Diagram .............................................................................................................. 289
6.7.4 Basic Configuration...................................................................................................... 290
6.7.5 Functional Description................................................................................................. 290
6.7.6 Register Map ................................................................................................................ 292
6.7.7 Register Description .................................................................................................... 293
6.8 External Bus Interface (EBI).....................................................................................298

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6.8.1 Overview ....................................................................................................................... 298
6.8.2 Features ........................................................................................................................ 298
6.8.3 Block Diagram .............................................................................................................. 299
6.8.4 Basic Configuration...................................................................................................... 299
6.8.5 Functional Description................................................................................................. 300
6.8.6 Register Map ................................................................................................................ 308
6.8.7 Register Description .................................................................................................... 309
6.9 General Purpose I/O (GPIO)....................................................................................313
6.9.1 Overview ....................................................................................................................... 313
6.9.2 Features ........................................................................................................................ 313
6.9.3 Block Diagram .............................................................................................................. 314
6.9.4 Basic Configuration...................................................................................................... 315
6.9.5 Functional Description................................................................................................. 315
6.9.6 Register Map ................................................................................................................ 318
6.9.7 Register Description .................................................................................................... 321
6.10 Hardware Divider (HDIV) ....................................................................................336
6.10.1Overview ....................................................................................................................... 336
6.10.2Features ........................................................................................................................ 336
6.10.3Blcok Diagram .............................................................................................................. 336
6.10.4Basic Configuration...................................................................................................... 336
6.10.5Functional Description................................................................................................. 336
6.10.6Register Map ................................................................................................................ 338
6.10.7Register Description .................................................................................................... 339
6.11 I2C Serial Interface Controller (I2C) ...................................................................344
6.11.1 Overview ....................................................................................................................... 344
6.11.2 Features ........................................................................................................................ 344
6.11.3 Block Diagram .............................................................................................................. 345
6.11.4 Basic Configuration...................................................................................................... 345
6.11.5 Functional Description................................................................................................. 346
6.11.6 Register Map ................................................................................................................ 362
6.11.7 Register Description .................................................................................................... 363
6.12 PDMA Controller (PDMA) ...................................................................................376
6.12.1Overview ....................................................................................................................... 376
6.12.2Features ........................................................................................................................ 376
6.12.3Block Diagram .............................................................................................................. 376
6.12.4Basic Configuration...................................................................................................... 376
6.12.5Functional Description................................................................................................. 377
6.12.6Register Map ................................................................................................................ 384
6.12.7Register Description .................................................................................................... 386
6.13 PWM Generator and Capture Timer (PWM)....................................................413
6.13.1Overview ....................................................................................................................... 413

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6.13.2Features ........................................................................................................................ 413
6.13.3Block Diagram .............................................................................................................. 415
6.13.4Basic Configuration...................................................................................................... 418
6.13.5Functional Description................................................................................................. 419
6.13.6Register Map ................................................................................................................ 450
6.13.7Register Description .................................................................................................... 454
6.14 Real Time Clock (RTC) .......................................................................................518
6.14.1Overview ....................................................................................................................... 518
6.14.2Features ........................................................................................................................ 518
6.14.3Block Diagram .............................................................................................................. 518
6.14.4Basic Configuration...................................................................................................... 519
6.14.5Functional Description................................................................................................. 519
6.14.6Register Map ................................................................................................................ 525
6.14.7Register Description .................................................................................................... 526
6.15 Smart Card Host Interface (SC).........................................................................546
6.15.1Overview ....................................................................................................................... 546
6.15.2Features ........................................................................................................................ 546
6.15.3Block Diagram .............................................................................................................. 546
6.15.4Basic Configuration...................................................................................................... 548
6.15.5Functional Description................................................................................................. 549
6.15.6Register Map ................................................................................................................ 559
6.15.7Register Description .................................................................................................... 560
6.16 Serial Peripheral Interface (SPI)........................................................................586
6.16.1Overview ....................................................................................................................... 586
6.16.2Features ........................................................................................................................ 586
6.16.3Block Diagram .............................................................................................................. 587
6.16.4Basic Configuration...................................................................................................... 587
6.16.5Functional Description................................................................................................. 589
6.16.6Timing Diagram ............................................................................................................ 602
6.16.7Programming Examples.............................................................................................. 604
6.16.8Register Map ................................................................................................................ 606
6.16.9Register Description .................................................................................................... 607
6.17 Timer Controller (TMR) .......................................................................................626
6.17.1Overview ....................................................................................................................... 626
6.17.2Features ........................................................................................................................ 626
6.17.3Block Diagram .............................................................................................................. 628
6.17.4Basic Configuration...................................................................................................... 632
6.17.5Timer Functional Description...................................................................................... 633
6.17.6PWM Functional Description...................................................................................... 638
6.17.7Register Map ................................................................................................................ 654
6.17.8Register Description .................................................................................................... 659
6.18 USB Device Controller (USBD)..........................................................................703

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6.18.1Overview ....................................................................................................................... 703
6.18.2Features ........................................................................................................................ 703
6.18.3Block Diagram .............................................................................................................. 704
6.18.4Basic Configuration...................................................................................................... 704
6.18.5Functional Description................................................................................................. 704
6.18.6Register Map ................................................................................................................ 710
6.18.7Register Description .................................................................................................... 712
6.19 USCI - Universal Serial Control Interface Controller ......................................731
6.19.1Overview ....................................................................................................................... 731
6.19.2Features ........................................................................................................................ 731
6.19.3Block Diagram .............................................................................................................. 731
6.19.4Functional Description................................................................................................. 731
6.20 USCI – UART Mode.............................................................................................742
6.20.1Overview ....................................................................................................................... 742
6.20.2Features ........................................................................................................................ 742
6.20.3Block Diagram .............................................................................................................. 742
6.20.4Basic Configuration...................................................................................................... 743
6.20.5Functional Description................................................................................................. 744
6.20.6Register Map ................................................................................................................ 753
6.20.7Register Description .................................................................................................... 754
6.21 USCI - SPI Mode..................................................................................................775
6.21.1Overview ....................................................................................................................... 775
6.21.2Features ........................................................................................................................ 775
6.21.3Block Diagram .............................................................................................................. 776
6.21.4Basic Configuration...................................................................................................... 776
6.21.5Functional Description................................................................................................. 778
6.21.6Register Map ................................................................................................................ 792
6.21.7Register Description .................................................................................................... 793
6.22 USCI - I2C Mode...................................................................................................815
6.22.1Overview ....................................................................................................................... 815
6.22.2Features ........................................................................................................................ 815
6.22.3Block Diagram .............................................................................................................. 816
6.22.4Basic Configuration...................................................................................................... 816
6.22.5Functional Description................................................................................................. 818
6.22.6Register Map ................................................................................................................ 835
6.22.7Register Description .................................................................................................... 836
6.23 UART Interface Controller (UART) ....................................................................855
6.23.1Overview ....................................................................................................................... 855
6.23.2Features ........................................................................................................................ 855
6.23.3Block Diagram .............................................................................................................. 856
6.23.4Basic Configuration...................................................................................................... 858

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6.23.5Functional Description................................................................................................. 860
6.23.6Register Map ................................................................................................................ 884
6.23.7Register Description .................................................................................................... 886
6.24 Watchdog Timer (WDT).......................................................................................919
6.24.1Overview ....................................................................................................................... 919
6.24.2Features ........................................................................................................................ 919
6.24.3Block Diagram .............................................................................................................. 919
6.24.4Basic Configuration...................................................................................................... 919
6.24.5Functional Description................................................................................................. 920
6.24.6Register Map ................................................................................................................ 922
6.24.7Register Description .................................................................................................... 923
6.25 Window Watchdog Timer (WWDT) ...................................................................927
6.25.1Overview ....................................................................................................................... 927
6.25.2Features ........................................................................................................................ 927
6.25.3Block Diagram .............................................................................................................. 927
6.25.4Basic Configuration...................................................................................................... 928
6.25.5Functional Description................................................................................................. 928
6.25.6Register Map ................................................................................................................ 931
6.25.7Register Description .................................................................................................... 932
7APPLICATION CIRCUIT..............................................................................937
8PACKAGE DIMENSIONS ............................................................................938
8.1 LQFP 100L (14x14x1.4 mm footprint 2.0 mm)......................................................938
8.2 LQFP 64L (7x7x1.4 mm footprint 2.0 mm).............................................................939
8.3 LQFP 48L (7x7x1.4 mm Footprint 2.0 mm) ...........................................................940
8.4 QFN 48L (7x7x0.8 mm).............................................................................................941
9REVISION HISTORY....................................................................................942

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LIST OF FIGURES
Figure 4.2-1 NuMicro®NUC126 USB Series QFN 48-pin Diagram...............................................32
Figure 4.2-2 NuMicro®NUC126 USB Series LQFP 48-pin Diagram .............................................33
Figure 4.2-3 NuMicro®NUC126 USB Series LQFP 64-pin Diagram .............................................34
Figure 4.2-4 NuMicro®NUC126 USB Series LQFP 100-pin Diagram ...........................................35
Figure 5.1-1 NuMicro®NUC126 Block Diagram.............................................................................69
Figure 6.1-1 Functional Block Diagram..........................................................................................70
Figure 6.2-1 System Reset Sources...............................................................................................73
Figure 6.2-2 nRESET Reset Waveform .........................................................................................76
Figure 6.2-3 Power-on Reset (POR) Waveform.............................................................................76
Figure 6.2-4 Low Voltage Reset (LVR) Waveform.........................................................................77
Figure 6.2-5 Brown-out Detector (BOD) Waveform .......................................................................78
Figure 6.2-6 NuMicro®NUC126 Power Mode State Machine........................................................80
Figure 6.2-7 NuMicro®NUC126 Power Distribution Diagram ........................................................83
Figure 6.2-8 SRAM Block Diagram ................................................................................................86
Figure 6.2-9 SRAM Memory Organization .....................................................................................87
Figure 6.2-10 UART1_TXD Modulated with PWM Channel...........................................................88
Figure 6.2-11 VDET Block Diagram...............................................................................................89
Figure 6.3-1 Clock Generator Block Diagram...............................................................................170
Figure 6.3-2 Clock Generator Global View Diagram....................................................................171
Figure 6.3-3 System Clock Block Diagram...................................................................................172
Figure 6.3-4 HXT Stop Protect Procedure....................................................................................173
Figure 6.3-5 SysTick Clock Control Block Diagram .....................................................................173
Figure 6.3-6 Clock Source of Clock Output..................................................................................174
Figure 6.3-7 Clock Output Block Diagram....................................................................................175
Figure 6.4-1 Flash Memory Controller Block Diagram .................................................................206
Figure 6.4-2 Data Flash................................................................................................................208
Figure 6.4-3 SPROM Security Mode............................................................................................213
Figure 6.4-4 Flash Memory Map ..................................................................................................214
Figure 6.4-5 System Memory Map with IAP Mode.......................................................................215
Figure 6.4-6 APROM/LDROM boot with IAP Mode......................................................................216
Figure 6.4-7 VECMAP setting example in IAP Mode...................................................................216
Figure 6.4-8 System Memory Map without IAP mode..................................................................217
Figure 6.4-9 ISP Procedure Example...........................................................................................220
Figure 6.4-10 Example for accelerating interrupt by VECMAP....................................................221
Figure 6.4-11 ISP 32-bit Programming Procedure.......................................................................222
Figure 6.4-12 ISP 64-bit Programming Procedure.......................................................................223

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Figure 6.4-13 Firmware in SRAM for Multi-word Programming ...................................................224
Figure 6.4-14 Multi-word Programming Flow ...............................................................................225
Figure 6.4-15 CRC-32 Checksum Calculation .............................................................................226
Figure 6.4-16 CRC-32 Checksum Calculation Flow.....................................................................227
Figure 6.4-17 All-One Verification Flow........................................................................................228
Figure 6.5-1 Analog Comparator Block Diagram .........................................................................248
Figure 6.5-2 Comparator Hysteresis Function of ACMP0............................................................250
Figure 6.5-3 Window Latch Mode of ACMP0...............................................................................250
Figure 6.5-4 Filter Function Example ...........................................................................................251
Figure 6.5-5 Comparator Controller Interrupt...............................................................................251
Figure 6.5-6 Comparator Reference Voltage Block Diagram.......................................................252
Figure 6.5-7 Example Connection of Window Compare Mode....................................................253
Figure 6.5-8 Example of Window Compare Mode .......................................................................253
Figure 6.6-1 AD Controller Block Diagram ...................................................................................263
Figure 6.6-2 ADC Peripheral Clock Control..................................................................................265
Figure 6.6-3 Single Mode Conversion Timing Diagram ...............................................................266
Figure 6.6-4 Burst Mode Conversion Timing Diagram.................................................................267
Figure 6.6-5 Single-Cycle Scan Mode on Enabled Channels Timing Diagram............................268
Figure 6.6-6 Continuous Scan Mode on Enabled Channels Timing Diagram..............................269
Figure 6.6-7 A/D Conversion Result Monitor Logic Diagram .......................................................270
Figure 6.6-8 A/D Controller Interrupt ............................................................................................271
Figure 6.6-9 Conversion Result Mapping Diagram of ADC Single-end Input..............................275
Figure 6.6-10 Conversion Result Mapping Diagram of ADC Differential Input ............................276
Figure 6.7-1 CRC Generator Block Diagram................................................................................289
Figure 6.7-2 CHECKSUM Bit Order Reverse Functional Block...................................................290
Figure 6.7-3 Write Data Bit Order Reverse Functional Block.......................................................291
Figure 6.8-1 EBI Block Diagram...................................................................................................299
Figure 6.8-2 Connection of 16-bit Device with 16-bit EBI Data Width..........................................301
Figure 6.8-3 Connection of 8-bit Device with 8-bit EBI Data Width..............................................302
Figure 6.8-4 Timing Control Waveform for 16-bit Data Width......................................................304
Figure 6.8-5 Timing Control Waveform for 8-bit Data Width........................................................305
Figure 6.8-6 Timing Control Waveform for Insert Idle Cycle........................................................306
Figure 6.8-7 Timing Control Waveform for Continuous Data Access Mode ................................307
Figure 6.9-1 GPIO Controller Block Diagram...............................................................................314
Figure 6.9-2 GPIO Clock Control Diagram...................................................................................315
Figure 6.10-1 Hardware Divider Block Diagram...........................................................................336
Figure 6.11-1 I2C Controller Block Diagram .................................................................................345

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Figure 6.11-2 I2C Bus Timing .......................................................................................................346
Figure 6.11-3 I2C Protocol ............................................................................................................347
Figure 6.11-4 START and STOP Conditions................................................................................347
Figure 6.11-5 Bit Transfer on the I2C Bus ....................................................................................348
Figure 6.11-6 Acknowledge on the I2C Bus..................................................................................348
Figure 6.11-7 Master Transmits Data to Slave by 7-bit................................................................349
Figure 6.11-8 Master Reads Data from Slave by 7-bit.................................................................349
Figure 6.11-9 Control I2C Bus according to the current I2C Status ..............................................350
Figure 6.11-10 Master Transmitter Mode Control Flow................................................................350
Figure 6.11-11 Master Receiver Mode Control Flow....................................................................351
Figure 6.11-12 Slave Mode Control Flow.....................................................................................352
Figure 6.11-13 GC Mode..............................................................................................................353
Figure 6.11-14 Arbitration Lost.....................................................................................................354
Figure 6.11-15 Timing of Two-level Buffer Transmit in Master Write...........................................355
Figure 6.11-16 Timing of Two-level Buffer Transmit in Slave Read.............................................355
Figure 6.11-17 Setup Time Wrong Adjustment............................................................................356
Figure 6.11-18 Hold Time Wrong Adjustment..............................................................................356
Figure 6.11-19 I2C Data Shifting Direction ...................................................................................357
Figure 6.11-20 I2C Time-out Count Block Diagram......................................................................359
Figure 6.11-21 I2C Wake-Up Related Signals Waveform ............................................................360
Figure 6.11-22 EEPROM Random Read .....................................................................................361
Figure 6.11-23 Protocol of EEPROM Random Read...................................................................361
Figure 6.12-1 PDMA Controller Block Diagram............................................................................376
Figure 6.12-2 Descriptor Table Entry Structure............................................................................377
Figure 6.12-3 Descriptor Table Operation in Basic Mode............................................................378
Figure 6.12-4 Descriptor Table Link List Structure.......................................................................380
Figure 6.12-5 Scatter-Gather Mode Finite State Machine............................................................380
Figure 6.12-6 Example of Single Transfer Type and Burst Transfer Type in Basic Mode...........382
Figure 6.12-7 Example of PDMA Channel 0 Time-out Counter Operation ..................................383
Figure 6.13-1 PWM Generator Overview Block Diagram.............................................................415
Figure 6.13-2 PWM System Clock Source Control ......................................................................415
Figure 6.13-3 PWM Clock Source Control ...................................................................................416
Figure 6.13-4 PWM Independent Mode Architecture Diagram ....................................................417
Figure 6.13-5 PWM Complementary Mode Architecture Diagram...............................................418
Figure 6.13-6 PWM0_CH0 Prescaler Waveform in Up Counter Type.........................................420
Figure 6.13-7 PWM Up Counter Type..........................................................................................420
Figure 6.13-8 PWM Down Counter Type .....................................................................................421

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Figure 6.13-9 PWM Up-Down Counter Type................................................................................421
Figure 6.13-10 PWM Compared point Events in Up-Down Counter Type...................................422
Figure 6.13-11 PWM Double Buffering Illustration.......................................................................423
Figure 6.13-12 Period Loading in Up-Count Mode.......................................................................424
Figure 6.13-13 Immediately Loading in Up-Count Mode..............................................................425
Figure 6.13-14 Window Loading in Up-Count Mode ....................................................................426
Figure 6.13-15 Center Loading in Up-Down-Count Mode............................................................427
Figure 6.13-16 PWM One-shot Mode Output Waveform.............................................................428
Figure 6.13-17 PWM Pulse Generation........................................................................................429
Figure 6.13-18 PWM 0% to 100% Pulse Generation...................................................................429
Figure 6.13-19 PWM Independent Mode Waveform....................................................................430
Figure 6.13-20 PWM Complementary Mode Waveform ..............................................................431
Figure 6.13-21 PWM Group Function Waveform.........................................................................432
Figure 6.13-22 PWM SYNC_IN Noise Filter Block Diagram........................................................432
Figure 6.13-23 PWM Counter Synchronous Function Block Diagram.........................................433
Figure 6.13-24 PWM Synchronous Function with Synchronize source from SYNC_IN Signal ...434
Figure 6.13-25 PWMx_CH0 Output Control in Independent Mode..............................................434
Figure 6.13-26 PWMx_CH0 and PWMx_CH1 Output Control in Complementary Mode ............435
Figure 6.13-27 Dead-Time Insertion.............................................................................................435
Figure 6.13-28 Illustration of Mask Control Waveform.................................................................436
Figure 6.13-29 Brake Noise Filter Block Diagram........................................................................437
Figure 6.13-30 Brake Block Diagram for PWMx_CH0 and PWMx_CH1 Pair..............................438
Figure 6.13-31 Edge Detector Waveform for PWMx_CH0 and PWMx_CH1 Pair.......................439
Figure 6.13-32 Level Detector Waveform for PWMx_CH0 and PWMx_CH1 Pair.......................439
Figure 6.13-33 Brake Source Block Diagram...............................................................................440
Figure 6.13-34 Brake System Fail Block Diagram .......................................................................440
Figure 6.13-35 PWM LEB Function Waveform............................................................................441
Figure 6.13-36 Initial State and Polarity Control with Rising Edge Dead-Time Insertion.............442
Figure 6.13-37 PWMx_CH0 and PWMx_CH1 Pair Accumulate Interrupt Waveform..................443
Figure 6.13-38 PWMx_CH0 and PWMx_CH1 Pair Interrupt Architecture Diagram.....................444
Figure 6.13-39 PWMx_CH0 and PWMx_CH1 Pair Trigger ADC Block Diagram ........................445
Figure 6.13-40 PWM Trigger ADC in Up-Down Counter Type Timing Waveform.......................446
Figure 6.13-41 PWMx_CH0 Capture Block Diagram...................................................................447
Figure 6.13-42 Capture Operation Waveform..............................................................................448
Figure 6.13-43 Capture PDMA Operation Waveform of Channel 0.............................................449
Figure 6.14-1 RTC Block Diagram ...............................................................................................519
Figure 6.14-2 Backup I/O Control Diagram ..................................................................................524

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Figure 6.15-1 SC Clock Control Diagram.....................................................................................547
Figure 6.15-2 SC Controller Block Diagram.................................................................................547
Figure 6.15-3 SC Data Character.................................................................................................549
Figure 6.15-4 SC Activation Sequence ........................................................................................550
Figure 6.15-5 SC Warm Reset Sequence....................................................................................551
Figure 6.15-6 SC Deactivation Sequence....................................................................................552
Figure 6.15-7 Basic Operation Flow.............................................................................................553
Figure 6.15-8 Initial Character TS ................................................................................................554
Figure 6.15-9 SC Error Signal ......................................................................................................554
Figure 6.15-10 Transmit Direction Block Guard Time Operation.................................................557
Figure 6.15-11 Receive Direction Block Guard Time Operation..................................................557
Figure 6.15-12 Extra Guard Time Operation................................................................................558
Figure 6.16-1 SPI Block Diagram (SPI0/1)...................................................................................587
Figure 6.16-2 SPI Peripheral Clock..............................................................................................589
Figure 6.16-3 SPI Full-Duplex Master Mode Application Block Diagram.....................................590
Figure 6.16-4 SPI Full-Duplex Slave Mode Application Block Diagram.......................................590
Figure 6.16-532-Bit in One Transaction ......................................................................................591
Figure 6.16-6 Automatic Slave Selection (SSACTPOL = 0, SUSPITV > 0x2).............................592
Figure 6.16-7 Automatic Slave Selection (SSACTPOL = 0, SUSPITV < 0x3).............................592
Figure 6.16-8 Byte Reorder Function...........................................................................................593
Figure 6.16-9 Timing Waveform for Byte Suspend ......................................................................593
Figure 6.16-10 SPI Half-Duplex Master Mode Application Block Diagram ..................................594
Figure 6.16-11 SPI Half-Duplex Slave Mode Application Block Diagram ....................................594
Figure 6.16-12 FIFO Threshold Comparator................................................................................595
Figure 6.16-13 Transmit FIFO Buffer Example ............................................................................596
Figure 6.16-14 Receive FIFO Buffer Example .............................................................................597
Figure 6.16-15 TX Underflow Event and Slave Under Run Event ...............................................597
Figure 6.16-16 Slave Mode Bit Count Error .................................................................................598
Figure 6.16-17 I2S Data Format Timing Diagram.........................................................................599
Figure 6.16-18 MSB Justified Data Format Timing Diagram........................................................600
Figure 6.16-19 PCM Mode A Timing Diagram .............................................................................600
Figure 6.16-20 PCM Mode B Timing Diagram .............................................................................600
Figure 6.16-21 FIFO Contents for Various I2S Modes .................................................................601
Figure 6.16-22 SPI Timing in Master Mode..................................................................................602
Figure 6.16-23 SPI Timing in Master Mode (Alternate Phase of SPIx_CLK)...............................602
Figure 6.16-24 SPI Timing in Slave Mode....................................................................................603
Figure 6.16-25 SPI Timing in Slave Mode (Alternate Phase of SPIx_CLK).................................603

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Figure 6.17-1 Timer Controller Block Diagram.............................................................................628
Figure 6.17-2 Clock Source of Timer Controller...........................................................................629
Figure 6.17-3 PWM Generator Overview Block Diagram.............................................................630
Figure 6.17-4 PWM System Clock Source Control ......................................................................630
Figure 6.17-5 PWM Counter Clock Source Control .....................................................................631
Figure 6.17-6 PWM Independent Mode Architecture Diagram ....................................................631
Figure 6.17-7 PWM Complementary Mode Architecture Diagram...............................................632
Figure 6.17-8 Continuous Counting Mode....................................................................................635
Figure 6.17-9 External Capture Mode..........................................................................................636
Figure 6.17-10 External Reset Counter Mode..............................................................................636
Figure 6.17-11 Internal Timer Trigger...........................................................................................637
Figure 6.17-12 Inter-Timer Trigger Capture Timing .....................................................................638
Figure 6.17-13 PWM Prescale Waveform in Up Count Type.......................................................638
Figure 6.17-14 PWM Up Count Type...........................................................................................639
Figure 6.17-15 PWM Down Count Type.......................................................................................639
Figure 6.17-16 PWM Up-Down Count Type.................................................................................640
Figure 6.17-17 PWM Comparator Events in Up-Down Count Type.............................................641
Figure 6.17-18 Period Loading Mode with Up Count Type..........................................................642
Figure 6.17-19 Immediately Loading Mode with Up Count Type.................................................643
Figure 6.17-20 PWM Pulse Generation in Up-Down Count Type................................................643
Figure 6.17-21 PWM 0% to 100% Duty Cycle in Up Count Type and Up-Down Count Type .....644
Figure 6.17-22 PWM Independent Mode Output Waveform........................................................645
Figure 6.17-23 PWM Complementary Mode Output Waveform...................................................645
Figure 6.17-24 PWMx_CH0 Output Control in Independent Mode..............................................645
Figure 6.17-25 PWMx_CH0 and PWMx_CH1 Output Control in Complementary Mode ............646
Figure 6.17-26 Dead-Time Insertion.............................................................................................646
Figure 6.17-27 PWM Output Mask Control Waveform.................................................................647
Figure 6.17-28 Brake Pin Noise Filter Block Diagram..................................................................647
Figure 6.17-29 Brake Event Block Diagram for PWMx_CH0 and PWMx_CH1...........................648
Figure 6.17-30 Edge Detector Brake Waveform for PWMx_CH0 and PWMx_CH1....................649
Figure 6.17-31 Level Detector Brake Waveform for PWMx_CH0 and PWMx_CH1....................650
Figure 6.17-32 Brake Source Block Diagram...............................................................................651
Figure 6.17-33 System Fail Brake Block Diagram .......................................................................651
Figure 6.17-34 PWMx_CH0 and PWMx_CH1 Polarity Control with Dead-Time Insertion ..........652
Figure 6.17-35 PWM Interrupt Architecture Diagram...................................................................653
Figure 6.17-36 PWM Trigger ADC Block Diagram.......................................................................653
Figure 6.18-1 USB Block Diagram ...............................................................................................704

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Figure 6.18-2 WKIDLE Interrupt Operation Flow .........................................................................706
Figure 6.18-3 Endpoint SRAM Structure......................................................................................707
Figure 6.18-4 Setup Transaction Followed by Data IN Transaction ............................................707
Figure 6.18-5 Data Out Transfer ..................................................................................................708
Figure 6.19-1 USCI Block Diagram ..............................................................................................731
Figure 6.19-2 Input Conditioning for USCIx_DAT[1:0] and USCIx_CTL[1:0]...............................732
Figure 6.19-3 Input Conditioning for USCIx_CLK ........................................................................733
Figure 6.19-4 Block Diagram of Data Buffering............................................................................734
Figure 6.19-5 Data Access Structure ...........................................................................................735
Figure 6.19-6 Transmit Data Path ................................................................................................735
Figure 6.19-7 Receive Data Path .................................................................................................736
Figure 6.19-8 Protocol-Relative Clock Generator ........................................................................737
Figure 6.19-9 Basic Clock Divider Counter ..................................................................................738
Figure 6.19-10 Block of Timing Measurement Counter................................................................738
Figure 6.19-11 Sample Time Counter..........................................................................................739
Figure 6.19-12 Event and Interrupt Structure...............................................................................740
Figure 6.20-1 USCI UART Mode Block Diagram .........................................................................742
Figure 6.20-2 UART Signal Connection for Full-Duplex Communication ....................................745
Figure 6.20-3 UART Standard Frame Format..............................................................................746
Figure 6.20-4 UART Bit Timing (data sample time) .....................................................................748
Figure 6.20-5 UART Auto Baud Rate Control ..............................................................................749
Figure 6.20-6 Incoming Data Wake-Up........................................................................................750
Figure 6.20-7 nCTS Wake-Up Case 1..........................................................................................750
Figure 6.20-8 nCTS Wake-Up Case 2..........................................................................................751
Figure 6.21-1 SPI Master Mode Application Block Diagram ........................................................775
Figure 6.21-2 SPI Slave Mode Application Block Diagram ..........................................................775
Figure 6.21-3 USCI SPI Mode Block Diagram .............................................................................776
Figure 6.21-4 Wire Full-Duplex SPI Communication Signals (Master Mode) .............................779
Figure 6.21-5 Wire Full-Duplex SPI Communication Signals (Slave Mode) ...............................779
Figure 6.21-6 SPI Communication with Different SPI Clock Configuration (SCLKMODE=0x0)..780
Figure 6.21-7 SPI Communication with Different SPI Clock Configuration (SCLKMODE=0x1)..781
Figure 6.21-8 SPI Communication with Different SPI Clock Configuration (SCLKMODE=0x2)..781
Figure 6.21-9 SPI Communication with Different SPI Clock Configuration (SCLKMODE=0x3)..782
Figure 6.21-1016-bit data Length in One Word Transaction with MSB First Format..................783
Figure 6.21-11 Word Suspend Interval between Two Transaction Words...................................783
Figure 6.21-12 Auto Slave Select (SUSPITV ≧0x3) ..................................................................784
Figure 6.21-13 Auto Slave Select (SUSPITV < 0x3)....................................................................784

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Figure 6.21-14 One Output Data Channel Half-duplex (SPI Master Mode).................................785
Figure 6.21-15 One Input Data Channel Half-duplex (SPI Master Mode)....................................786
Figure 6.21-16 SPI Timing in Master Mode..................................................................................788
Figure 6.21-17 SPI Timing in Master Mode (Alternate Phase of Serial Bus Clock).....................788
Figure 6.21-18 SPI Timing in Slave Mode....................................................................................789
Figure 6.21-19 SPI Timing in Slave Mode (Alternate Phase of Serial Bus Clock).......................789
Figure 6.22-1 I2C Bus Timing .......................................................................................................815
Figure 6.22-2 USCI I²C Mode Block Diagram ..............................................................................816
Figure 6.22-3 I2C Protocol ............................................................................................................818
Figure 6.22-4 START and STOP Conditions................................................................................819
Figure 6.22-5 Bit Transfer on the I2C Bus ....................................................................................820
Figure 6.22-6 Acknowledge on the I2C Bus..................................................................................820
Figure 6.22-7 Arbitration Lost.......................................................................................................821
Figure 6.22-8 Control I2C Bus according to Current I2C Status....................................................824
Figure 6.22-9 Master Transmits Data to Slave with a 7-bit address ............................................825
Figure 6.22-10 Master Reads Data from Slave with a 7-bit address ...........................................825
Figure 6.22-11 Master Transmits Data to Slave by 10-bit address..............................................825
Figure 6.22-12 Master Reads Data from Slave by 10-bit address...............................................826
Figure 6.22-13 Master Transmitter Mode Control Flow with 7-bit Address..................................826
Figure 6.22-14 Master Receiver Mode Control Flow with 7-bit Address......................................827
Figure 6.22-15 Save Mode Control Flow with 7-bit address ........................................................828
Figure 6.22-16 GC Mode with 7-bit address.................................................................................830
Figure 6.22-17 Setup Time Wrong Adjustment............................................................................832
Figure 6.22-18 Hold Time Wrong Adjustment..............................................................................832
Figure 6.22-19 I2C Time-out Count Block Diagram......................................................................833
Figure 6.22-20 EEPROM Random Read .....................................................................................834
Figure 6.22-21 Protocol of EEPROM Random Read...................................................................834
Figure 6.23-1 UART Clock Control Diagram................................................................................856
Figure 6.23-2 UART Block Diagram.............................................................................................856
Figure 6.23-3 Auto-Baud Rate Measurement ..............................................................................863
Figure 6.23-4 Transmit Delay Time Operation.............................................................................864
Figure 6.23-5 UART nCTS Wake-up Case1 ................................................................................864
Figure 6.23-6 UART nCTS Wake-up Case2 ................................................................................865
Figure 6.23-7 UART Data Wake-up .............................................................................................865
Figure 6.23-8 UART Received Data FIFO Reached Threshold Wake-up ...................................866
Figure 6.23-9 UART RS-485 AAD Mode Address Match Wake-up.............................................866
Figure 6.23-10 UART Received Data FIFO Threshold Time-out Wake-up..................................867

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Figure 6.23-11 Auto-Flow Control Block Diagram........................................................................870
Figure 6.23-12 UART nCTS Auto-Flow Control Enabled.............................................................871
Figure 6.23-13 UART nRTS Auto-Flow Control Enabled.............................................................871
Figure 6.23-14 UART nRTS Auto-Flow with Software Control.....................................................872
Figure 6.23-15 IrDA Control Block Diagram.................................................................................872
Figure 6.23-16 IrDA TX/RX Timing Diagram................................................................................873
Figure 6.23-17 Structure of LIN Frame.........................................................................................874
Figure 6.23-18 Structure of LIN Byte............................................................................................874
Figure 6.23-19 Break Detection in LIN Mode...............................................................................876
Figure 6.23-20 LIN Frame ID and Parity Format..........................................................................876
Figure 6.23-21 LIN Sync Field Measurement...............................................................................878
Figure 6.23-22 UART_BAUD Update Sequence in AR Mode if SLVDUEN is 1..........................879
Figure 6.23-23 UART_BAUD Update Sequence in AR mode if SLVDUEN is 0..........................879
Figure 6.23-24 RS-485 nRTS Driving Level in Auto Direction Mode ...........................................881
Figure 6.23-25 RS-485 nRTS Driving Level with Software Control..............................................882
Figure 6.23-26 Structure of RS-485 Frame..................................................................................883
Figure 6.24-1 Watchdog Timer Block Diagram ............................................................................919
Figure 6.24-2 Watchdog Timer Clock Control..............................................................................920
Figure 6.24-3 Watchdog Timer Time-out Interval and Reset Period Timing................................921
Figure 6.25-1 WWDT Block Diagram ...........................................................................................927
Figure 6.25-2 WWDT Clock Control.............................................................................................928
Figure 6.25-3 WWDT Compare Match Interrupt when CMPDAT is 0x3E....................................929
Figure 6.25-4 WWDT Counter Reload and Reset Behavior.........................................................930

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List of Tables
Table 1.1-1 Key Features Support Table .......................................................................................19
Table 3.1-1 List of Abbreviations....................................................................................................29
Table 4.3-1 NUC126 GPIO Multi-function Table............................................................................68
Table 6.2-1 Reset Value of Registers.............................................................................................75
Table 6.2-2 Power Mode Difference Table.....................................................................................79
Table 6.2-3 Clocks in Power Modes...............................................................................................81
Table 6.2-4 Condition of Entering Power-down Mode Again .........................................................82
Table 6.2-5 Address Space Assignments for On-Chip Controllers................................................85
Table 6.2-6 Exception Model........................................................................................................139
Table 6.2-7 Interrupt Number Table.............................................................................................140
Table 6.3-1 Clock Stable Count Value Table ...............................................................................169
Table 6.3-2 Power-down Mode Control Table..............................................................................179
Table 6.4-1 Boot Source Selection Table.....................................................................................218
Table 6.4-2 ISP Command List ....................................................................................................219
Table 6.4-3 FMC control registers for Flash Programming..........................................................222
Table 6.8-1 EBI Memory Mapping of Bank0 and Bank1..............................................................300
Table 6.8-2 EBI Timing Control Setting Table..............................................................................303
Table 6.11-1 Relationship between I2C Baud Rate and PCLK ....................................................356
Table 6.11-2 I2C Status Code Description....................................................................................358
Table 6.12-1 Channel Priority Table.............................................................................................377
Table 6.13-1 PWM System Clock Source Control Registers Setting Table.................................416
Table 6.13-2 PWM Pulse Generation Event Priority for Up-Counter ...........................................429
Table 6.13-3 PWM Pulse Generation Event Priority for Down-Counter.......................................430
Table 6.13-4 PWM Pulse Generation Event Priority for Up-Down-Counter.................................430
Table 6.14-1 RTC Read/Write Access Attribute...........................................................................520
Table 6.14-212/24-Hour Time Scale Selection ...........................................................................521
Table 6.14-3 Registers Default Value After Powered On.............................................................522
Table 6.14-4 Registers Power Domain.........................................................................................523
Table 6.15-1 SC Host Controller Pin Description.........................................................................548
Table 6.15-2 UART Pin Description .............................................................................................548
Table 6.15-3 Timer0/Timer1/Timer2 Operation Mode..................................................................557
Table 6.16-1 SPI/I2S Interface Controller Pin...............................................................................589
Table 6.17-1 PWM Pulse Generation Event Priority in Up Count Type.......................................644
Table 6.17-2 PWM Pulse Generation Event Priority in Down Count Type ..................................644
Table 6.17-3 PWM Pulse Generation Event Priority in Up-Down Count Type.............................644
Table 6.19-1 Input Signals for Different Protocols........................................................................732

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Table 6.19-2 Output Signals for Different Protocols.....................................................................733
Table 6.19-3 Data Transfer Events and Interrupt Handling..........................................................740
Table 6.19-4 Protocol-specific Events and Interrupt Handling.....................................................741
Table 6.20-1 Input Signals for UART Protocols ...........................................................................745
Table 6.20-2 Output Signals for Different Protocols.....................................................................746
Table 6.21-1 SPI Communication Signals....................................................................................778
Table 6.21-2 Serial Bus Clock Configuration................................................................................780
Table 6.22-1 Relationship between I2C Baud Rate and PCLK ....................................................831
Table 6.23-1 UART Interrupt ........................................................................................................858
Table 6.23-2 UART Interface Controller Pin.................................................................................858
Table 6.23-3 UART Controller Baud Rate Equation Table...........................................................860
Table 6.23-4 UART Controller Baud Rate Parameter Setting Example Table.............................861
Table 6.23-5 UART Controller Baud Rate Register Setting Example Table................................861
Table 6.23-6 Baud Rate Compensation Example Table 1...........................................................862
Table 6.23-7 Baud Rate Compensation Example Table 2...........................................................862
Table 6.23-8 UART Controller Interrupt Source and Flag List .....................................................869
Table 6.23-9 UART Line Control of Word and Stop Length Setting.............................................869
Table 6.23-10 UART Line Control of Parity Bit Setting ................................................................870
Table 6.23-11 LIN Header Selection in Master Mode ..................................................................875
Table 6.24-1 Watchdog Timer Time-out Interval Period Selection ..............................................920
Table 6.25-1 WWDT Prescale Value Selection and Time-out Period..........................................929
Table 6.25-2 CMPDAT Setting Limitation.....................................................................................930

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1 GENERAL DESCRIPTION
The NuMicro®NUC126 series microcontroller based on the ARM®Cortex®-M0 core operates at up to
72 MHz. With its crystal-less USB 2.0 FS interface, it is able to generate precise frequency required by
USB protocol without the need of external crystal. It features adjustable VDDIO pins for specific I/O pins
with a wide range of voltage from 1.8V to 5.5V for various operating voltages of external components,
a unique high-speed PWM with clock frequency up to 144 MHz for precision control, and an integrated
hardware divider to speed up the calculation for the control algorithms. Apart from that, the NUC126
also integrates SPROM (Security Protection ROM) which provides a secure code execution area to
protect the intelligent property of developers. The NUC126 series is ideal for industrial control, motor
control and metering applications.
The NUC126 series supports the wide voltage range from 2.5V to 5.5V and temperature ranging from -
40℃to 105℃, up to 256 Kbytes of Flash memory, 20 Kbytes of SRAM, 4 Kbytes of ISP (In-System
Programming) ROM as well as ICP (In-Circuit Programming) ROM and IAP (In-Application
Programming) ROM in 48-, 64- or 100-pin packages. It also supports high immunity of 8KV ESD
(HBM)/4KV EFT. It is also equipped with plenty of peripherals such as USB interface, Timers,
Watchdog Timers, RTC, PDMA, EBI, UART, Smart Card Interface, SPI, I²S, I²C, GPIO, up to 12
channels of 16-bit PWM, up to 20 channels of 12-bit ADC, analog comparator, temperature sensor,
low voltage reset, brown-out detector, 96-bit UID (Unique Identification), and 128-bit UCID (Unique
Customer Identification).
1.1 Key Feature and Application
Product
Line
USB
USCI
UART
I2C
SPI/I2S
ISO
7816
PWM
EBI
PDMA
ADC
ACMP
RTC
VBAT
VDDIO
NUC126
2.0 FS
Device
3
3
2
2
2
12
Y
5
20
2
Y
Y
Table 1.1-1 Key Features Support Table
The NuMicro®NUC126 series is suitable for a wide range of applications such as:
Industrial Automation
PLCs
Inverters
Home Automation
Security Alarm System
Power Metering
Portable Data Collector
Portable RFID Reader
System Supervisors
Smart Card Reader
Printer
Bar Code Scanner
Motor Control
Digital Power

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2 FEATURES
2.1 NuMicro®NUC126 Features
Core
–ARM®Cortex®-M0 core running up to 72 MHz
–One 24-bit system timer
–Supports low power sleep mode
–Single-cycle 32-bit hardware multiplier
–NVIC for the 32 interrupt inputs, each with 4-levels of priority
–Supports programmable mask-able interrupts
–Serial Wire Debug supports with 2 watch-points/4 breakpoints
Built-in LDO for wide operating voltage ranged from 2.5V to 5.5V
Flash Memory
–Supports 256/128 KB application ROM (APROM)
–Supports 4 KB Flash for loader (LDROM)
–Supports 2 KB Security Protection Rom (SPROM)
–Supports 12 bytes User Configuration block to control system initiation
–Supports Data Flash with configurable memory size
–Supports 2 KB page erase for all embedded flash
–Supports In-System-Programming (ISP), In-Application-Programming (IAP) update
embedded flash memory
–Supports CRC-32 checksum calculation function
–Supports flash all one verification function
–Hardware external read protection of whole flash memory by Security Lock Bit
–Supports 2-wired ICP update through SWD/ICE interface
SRAM Memory
–20 KB embedded SRAM
–Supports byte-, half-word- and word-access
–Supports PDMA mode
Hardware Divider
–Signed (two’s complement) integer calculation
–32-bit dividend with 16-bit divisor calculation capacity
–32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends to 32-
bit)
–Divided by zero warning flag
–6 HCLK clocks taken for one cycle calculation
–Write divisor to trigger calculation
–Waiting for calculation ready automatically when reading quotient and remainder
PDMA (Peripheral DMA)
–Supports 5 independent configurable channels for automatic data transfer between
memories and peripherals
–Supports single and burst transfer type
–Supports Normal and Scatter-Gather Transfer modes
–Supports two types of priorities modes: Fixed-priority and Round-robin modes
–Supports byte-, half-word- and word-access
–Supports incrementing mode for the source and destination address for each channel
–Supports time-out function for channel 0 and channel 1
–Supports software and SPI/I2S, UART, USCI, USB, ADC, PWM and TIMER request
Clock Control