Nvidia JETSON XAVIER NX Guide

DG-09693-001_v1.7 | November 2022
NVIDIA Jetson Xavier NX
Design Guide

NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | ii
Document History
DG-09693-001_v1.7
Version
Date
Description of Change
0.9 November 6, 2019 Preliminary Information
0.91 February 7, 2020 •Updated Table 2-2
•Removed >1 min recommendation for power rail charging
•Updated Table 3-1
•Added PCIe x1 interface support for Root Port operation
•Updated Table 4-1
•Corrected controller # for PCIE0 pins, updated x1 PCIe to come from
Xavier PEX Lane 11, and updated PEX lane changes in Table 4-2
•Updated Table 4-3
•Updated USB2 pin numbers and removed 4.7uF cap on VDD_5V_USB
to match P3509 implementation in Figure 4-1
•Moved PCIe x1 to Lane 11, corrected PCIE0_TX3 and RX0 pin
numbers, corrected x4 controller, and removed AC cap values on TX
lines in Figure 4-8
•Corrected controller # or x4 PCIe I/F, removed AC cap values on TX
lines, and corrected PCIE0_TX3 and RX0 pin numbers in Figure 4-9
•Updated PCIe controller numbers in Table 4-10
•Changed pull ups on RST and INT to go to 3.3V and added level shifter
to INT to SoC in Figure 4-10
•Updated ethernet connections in Table 4-13
•Updated DP_AUX_CH0_N and DP_AUX_CH0_N pin type since the
interface can be used for HDMI in Table 5-1
•Updated with 100Kohm PD and series resistors on DPx_HPD on
connector side of level shifter in Figure 5-1
•Updated DPx_HPD pin termination description in Table 5-4
•Updated notes to Table 7-1
•Updated notes to Table 8-1
•Updated Figure 8-1 with Jetson module
•Corrected PM3_PWM3 to GP_PWM6 in the fan section, Section 9.5
•Corrected the Xavier signal connected GPIO14 pin in Table 9-12 and
Figure 9-7
•Updated TX and RX to match module name in Table 9-13
•Updated checklist Table 12-1
•Updated Table 13-1
• Updated Table 13-2
0.92 March 23, 2020 •Removed PMIC part # from Figure 2-1
•Added new chapter on module connector (Chapter 3)
• Added note to Section 5.1 “USB”

NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | iii
Version
Date
Description of Change
•
Updated Section 5.2 “PCIe”
•Updated Figure 5-9 and the note to include open-drain buffers on the
control signals when NX is an Endpoint
•Updated the notes to Table 5-9
•Updated Table 5-10
•Updated eDP and DP pin descriptions in Table 6-1
•Removed series resistor after the level shifter and added related note
to Figure 6-1
•Removed resistor divider on HPD in Figure 6-7
•Removed GPIO08 for card select mention in Table 8-1
•Updated Figure 8-1 with the following: moved load switch enable to
GPIO, moved card detect to generic GPIO, and removed series
resistor on card detect line
•Updated Table 8-3 with generic GPIO
•Replaced FET circuit used for level shifters with generic level shifter
blocks in Figure 10-7
•Removed design checklist and pin descriptions tables and made
them separate attachments to this design guide
1.0 April 21, 2020 •Added note to Table 4-1 regarding direction of CLK_32K_OUT signal
•Added note to Table 5-2 regarding PEX_L4_RST* and PCIE_WAKE*
signals
•Updated Section 5.2 on PCIe
•Added Table 5-10 on PCIe Gen4 routing requirements
•Added note to Table 6-1 regarding DP_AUX_CH[1:0]_HPD direction
•Added note to Table 7-2 regarding CAM[1:0]_MCLK and
CAM[1:0]_PWDN direction
•Added note to Table 8-1 regarding SDMMC_CLK direction
•Added note to Table 9-1 regarding I2S[1:0]_DOUT and _DIN direction
•Added note to Table 10-7 regarding UART pins
•Updated Figure 10-5 to show on module buffers and added related
note
•Added note to Table 10-9 regarding CAN signals
•Added note to Table 10-12 regarding GPIO014 and GPIO008 direction
•
Updated attachments
1.1 May 7, 2020
•
Updated Table 5-5 with the following:
Updated Gen1 and Gen2 values
Removed redundant GND via reference requirement and
accompanying note
Added Gen2 specific requirements to ESD
•Updated Table 6-5 with max trace lengths (more relaxed) and PTH
vias (more restrictive)
•Updated Table 7-4 with the following:
Removed max loading spec

NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | iv
Version
Date
Description of Change
Removed “loosely coupled diff pair” comment from Intra pair
requirement note
Updated max trace delays and added max trace lengths
Added max insertion loss
Changed max DQ to CLK skew for 1 Gbps
1.2 August 13, 2020
•
Added new chapter on developer kit feature considerations (Chapter
3)
•Removed note related to CLK_32K_OUT in Table 5-1
•Updated length/skew in Table 6-9 and Table 6-10
•Added Figure 6-10 and Figure 6-11 on s-parameter plots (SDD21 and
SD11)
•Updated Figure 9-1 and notes related to the VDD supply enable and
current limiting
•Removed reference to CAM_I2C used for on module power monitor in
Section 11.1.1
•Removed mention of SPI2 pins in Table 11-6
•Added bring-up checklist attachment (See reference in Chapter 14)
•Updated design checklist and full pin description attachments
1.3 November 4, 2020
•
Updated USB SS hub design with publicly available part number in
Section 3.2
•Added to note to clarify PCIe clock output and REFCLK input
signaling type to Figure 6-8 and Figure 6-9
•Removed note under Figure 8-3 about CAM_I2C connection to on-
module power monitor
•Updated Table 8-4 based on new guidelines from IOSI after they used
improved model
•Updated Figure 10-1 with simpler more generic example of audio
codec connection
•Added Section 11.7 on USB recovery mode
1.4 August 12, 2021
•
Updated block diagram Figure 2-1
•Added notes to Table 5-1
•Updated power supply and sequencing information in Section 5.1
•Updated Section 6.1 on USB
•Updated USB 2.0 signal connections in Table 6-7
•Made “Gigabit Ethernet” section its own chapter (Chapter 7)
•Added section on test points for high-speed interfaces (Section 17.6
•Updated pin description attachment
1.5 September 20, 2021 •Removed WiFi/BT/Modem row in Table 2-1”Jetson Xavier NX
Interfaces”
•Updated Section 5.1 “Power Supply and Sequencing” text
•Updated Figure 5-2 “Power Up Sequence (No Power Button – Auto
Power On)”
•
Added Figure 5-3 “Power Up Sequence (With Power Button)”

NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | v
Version
Date
Description of Change
•
Simplified pin types for PCIe and USB SS differential signals and
updated PCIE_WAKE_N pull-up on module value in Table 6-2 “USB
3.1 and PCIe Pin Description”
•Added note related to load switch to Figure 6-2 “USB SS Type A
Example”
•Reversed order of pins in Module Pin #s column to match [1:0] order
in Module Pin Name column in Table 8-2 “DP and HDMI Pin
Mapping”
•Simplified HDMI/DP Pin Types Table 8-1 “eDP and DP Pin
Descriptions”
1.6 February 25, 2022 •
Updated descriptions for SHUTDOWN_REQ* and POWER_EN in
Power Supply and Sequencing section.
•Update power on sequence to include minimum delay from VDD_IN
valid to POWER_EN active.
•Correct PCIe/USB SS mapping table that has the wrong UPHY lanes
(should be NVHS lanes)
•Correct reference to PEX_CLK3 in Table 6-11 (PCIe Signal
Connections). Should be PEX_CLK5.
•Correct PCIe guidelines where loss should just be dB, not dB/in.
•Update CSI to support all 14 lanes (3x4 +1x2, 2x4 + 3x2, 1x4 + 5x2)
•Updated USB Recovery sections to include minimum requirement for
entering Force Recovery mode.
• Add USB SS and Wireless Coexistence section
1.7 November 16, 2022 •Chapter 1 Intro: Added notes related to USB 3.2 and updated
document to use USB 3.2 throughout
•Chapter 1 Intro: Added note related to replacing Master/Slave
terminology and updated throughout document
•Section 5.1: Added additional description for SHUTDOWN_REQ*
•Figure 5-5: Added power off initiated by de-asserting POWER_EN
•Section 6.2: Added text related to PCIe polarity inversion support
•Table 6-11: Corrected pull-up value on-module for PCIE_WAKE*
•Figure 8-7: Corrected DP_AUX connections
•Figure 11-1: Corrected I2C pull-up voltage in note 2 under figure.
•Table 13-1: Removed SYS_RESET*
•Table 13-2: Corrected pull-up value on-module for PCIE_WAKE*
•
Section 18.2/18.3/18.4: Updated text to use mm instead of in/mils

NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | vi
Table of Contents
Chapter 1. Introduction ....................................................................................................... 1
1.1 References........................................................................................................................ 1
1.2 Abbreviations and Definitions .......................................................................................... 1
Chapter 2. Jetson Xavier NX................................................................................................3
Chapter 3. Developer Kit Feature Considerations .............................................................. 7
3.1 Button Power MCU........................................................................................................... 7
3.2 USB SuperSpeed Hub ...................................................................................................... 8
3.3 Power over Ethernet......................................................................................................... 8
3.4 TI TXB0108 Level Shifters ................................................................................................ 8
3.5 Features Not to be Implemented .................................................................................... 8
Chapter 4. Modular Connector............................................................................................9
4.1 Module Connector Details ............................................................................................... 9
4.2 Module to Mounting Hardware ........................................................................................ 9
4.3 Module Installation and Removal .................................................................................. 10
Chapter 5. Power............................................................................................................... 11
5.1 Power Supply and Sequencing ...................................................................................... 12
Chapter 6. USB and PCIe................................................................................................... 17
6.1 USB.................................................................................................................................. 19
6.1.1 USB 2.0 Design Guidelines .................................................................................... 21
6.1.2 USB 3.2 Design Guidelines .................................................................................... 21
6.1.2.1 Common USB Routing Guidelines................................................................... 25
6.2 PCIe ................................................................................................................................. 26
6.2.1 PCIe Design Guidelines.......................................................................................... 29
Chapter 7. Gigabit Ethernet............................................................................................... 35
Chapter 8. Display ............................................................................................................. 38
8.1 eDP and DP..................................................................................................................... 40
8.1.1 eDP and DP Routing Guidelines............................................................................ 41
8.2 HDMI................................................................................................................................ 45
Chapter 9. MIPI CSI Video Input ........................................................................................ 54
9.1 CSI Design Guidelines .................................................................................................... 59
Chapter 10. SD Card and SDIO ............................................................................................ 61
Chapter 11. Audio................................................................................................................ 64
Chapter 12. Miscellaneous Interfaces ................................................................................ 67
12.1 I2C.................................................................................................................................... 67

NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | vii
12.1.1 I2C Design Guidelines ............................................................................................ 68
12.2 SPI ................................................................................................................................... 70
12.2.1 SPI Design Guidelines............................................................................................ 71
12.3 UART................................................................................................................................ 72
12.4 CAN ................................................................................................................................. 74
12.5 Fan................................................................................................................................... 75
12.6 Debug .............................................................................................................................. 76
12.7 USB Recovery Mode ....................................................................................................... 77
Chapter 13. PADS................................................................................................................ 78
13.1 Internal Pull-ups for Dual Voltage Block Pins Power at 1.8V...................................... 78
13.2 Schmitt Trigger Usage ................................................................................................... 78
13.3 Pins Pulled or Driven High During Power-ON.............................................................. 79
Chapter 14. Unused Interface Terminations....................................................................... 81
14.1 Unused Multi-purpose Standard CMOS Pad Interfaces .............................................. 81
14.2 Unused Dedicated Special Purpose Pad Interfaces..................................................... 81
Chapter 15. USB 3.2 and Wireless Coexistence .................................................................. 82
15.1 Mitigation Techniques .................................................................................................... 82
Chapter 16. Design and Bring-Up Checklists...................................................................... 84
Chapter 17. Jetson Xavier NX Pin Descriptions .................................................................. 85
Chapter 18. General Routing Guidelines............................................................................. 86
18.1 Signal Name Conventions.............................................................................................. 86
18.2 Routing Guideline Format.............................................................................................. 87
18.3 Signal Routing Conventions ........................................................................................... 87
18.4 Routing Guidelines ......................................................................................................... 87
18.4.1 General PCB Routing Guidelines .......................................................................... 88
18.5 Common High-Speed Interface Requirements ............................................................ 89
18.6 Test Points for High-Speed Interfaces.......................................................................... 90

NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | viii
List of Figures
Figure 2-1. Jetson Xavier NX Block Diagram...........................................................................4
Figure 4-1. Jetson Xavier NX Module Installed in SODIMM Connector..................................9
Figure 4-2. Module to Connector Assembly Diagram ...........................................................10
Figure 5-1. System Power and Control Block Diagram........................................................13
Figure 5-2. Power Up Sequence (No Power Button – Auto Power On) ................................14
Figure 5-3. Power Up Sequence (With Power Button) ..........................................................14
Figure 5-4. Power Down (Initiated by SHUTDOWN_REQ* Assertion)...................................15
Figure 5-5. Power Down (Initiated by POWER_EN De-assertion) ........................................15
Figure 5-6. Power Down (Sudden Power Loss) .....................................................................16
Figure 6-1. USB 3.2 Micro B USB Device and Recovery Connection Example ....................20
Figure 6-2. USB 3.2 Type A Host Only Connection Example.................................................20
Figure 6-3. IL/NEXT Plot (GEN1).............................................................................................23
Figure 6-4. IL/NEXT Plot (GEN2).............................................................................................24
Figure 6-5. Via Topology..........................................................................................................24
Figure 6-6. Component Order.................................................................................................24
Figure 6-7. Component Placement ........................................................................................25
Figure 6-8. ESD Layout Recommendations...........................................................................25
Figure 6-9. PCIe Root Port Connections Example.................................................................27
Figure 6-10. PCIe Endpoint Connections Example..................................................................28
Figure 6-11. Insertion Loss S-Parameter Plot (SDD21)..........................................................30
Figure 6-12. Insertion Loss S-Parameter Plot (SDD11)..........................................................31
Figure 6-13. AC Cap Voiding .....................................................................................................31
Figure 6-14. Connector Voiding ................................................................................................31
Figure 6-15. Example Zig-Zag Routing ....................................................................................33
Figure 7-1. Ethernet Connections ..........................................................................................36
Figure 7-2. Gigabit Ethernet Magnetics and RJ45 Connections...........................................36
Figure 8-1. DP and eDP Connection Example .......................................................................40
Figure 8-2. eDP and DP Differential Main Link Topology .....................................................41
Figure 8-3. S-Parameter (up to HBR2)...................................................................................43
Figure 8-4. S-Parameter (up to HBR3)...................................................................................44
Figure 8-5. Via Topology #1 ....................................................................................................44
Figure 8-6. Via Topology #2 ....................................................................................................44
Figure 8-7. HDMI Connection Example..................................................................................46
Figure 8-8. HDMI Clk and Data Topology...............................................................................47
Figure 8-9. IL/FEXT Plot..........................................................................................................50
Figure 8-10. TDR Plot................................................................................................................50
Figure 8-11. HDMI Via Topology ...............................................................................................51

NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | ix
Figure 8-12. Add-On Components – Top..................................................................................51
Figure 8-13. Add-on Components – Bottom ............................................................................51
Figure 8-14. AC Cap Void ..........................................................................................................51
Figure 8-15. RPD/Choke, FET Placement................................................................................52
Figure 8-16. ESD Footprint .......................................................................................................52
Figure 8-17. ESD Void................................................................................................................52
Figure 8-18. SMT Pad Trace Entering ......................................................................................52
Figure 8-19. SMT Pad Trace Between......................................................................................53
Figure 8-20. Connector Voiding ................................................................................................53
Figure 9-1. 4 Lane CSI Camera Connection Example...........................................................56
Figure 9-2. CSI Connection Options .......................................................................................58
Figure 9-3. Available Camera Control Pins ...........................................................................59
Figure 10-1. SD Card Connection Example .............................................................................62
Figure 11-1. Audio Codec Connection Example ......................................................................65
Figure 12-1. I2C Connections....................................................................................................68
Figure 12-2. SPI Connections ...................................................................................................70
Figure 12-3. Basic SPI Initiator and Target Connections........................................................71
Figure 12-4. SPI Topologies ......................................................................................................71
Figure 12-5. UART Connections ...............................................................................................73
Figure 12-6. CAN Connections .................................................................................................74
Figure 12-7. Fan Connections...................................................................................................75
Figure 12-8. Debug UART Connections....................................................................................76
Figure 18-1. General PCB Routing Guidelines ........................................................................88
Figure 18-2. Common Mode Choke..........................................................................................89
Figure 18-3. Serpentine ............................................................................................................90

NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | x
List of Tables
Table 1-1. Abbreviations and Definitions................................................................................2
Table 2-1. Jetson Xavier NX Interfaces...................................................................................3
Table 2-2. Jetson Xavier NX Connector (260-Pin SO-DIMM) Pin Out Matrix ........................5
Table 5-1. Power and System Pin Description.....................................................................11
Table 6-1. USB 2.0 Pin Description.......................................................................................17
Table 6-2. USB 3.2 and PCIe Pin Description.......................................................................18
Table 6-3. USB 3.2 and PCIe Lane Mapping.........................................................................19
Table 6-4. USB 2.0 Interface Signal Routing Requirements ...............................................21
Table 6-5. USB 3.1 Interface Signal Routing Requirements ...............................................21
Table 6-6. USB 2.0 Signal Connections ................................................................................25
Table 6-7. Miscellaneous USB Signal Connections.............................................................26
Table 6-8. USB 3.2 Signal Connections ................................................................................26
Table 6-9. PCIe Interface Signal Routing Requirements to Gen3.......................................29
Table 6-10. PCIe Gen4 Interface Signal Routing Requirements ...........................................32
Table 6-11. PCIe Signal Connections......................................................................................33
Table 7-1. Gigabit Ethernet Pin Descriptions.......................................................................35
Table 7-2. Ethernet MDI Interface Signal Routing Requirements ......................................37
Table 7-3. Ethernet Signal Connections...............................................................................37
Table 8-1. eDP and DP Pin Descriptions ..............................................................................38
Table 8-2. DP and HDMI Pin Mapping ..................................................................................39
Table 8-3. ePD and DP Main Link Signal Requirements Including DP_AUX......................41
Table 8-4. eDP and DP Signal Connections .........................................................................45
Table 8-5. HDMI Interface Signal Routing Requirements ...................................................47
Table 8-6. HDMI Signal Connections ....................................................................................53
Table 9-1. CSI Pin Descriptions ............................................................................................54
Table 9-2. Camera Miscellaneous Pin Descriptions............................................................56
Table 9-3. CSI Configurations ...............................................................................................57
Table 9-4. MIPI CSI Interface Signal Routing Requirements ..............................................59
Table 9-5. MIPI CSI Signal Connections ...............................................................................60
Table 9-6. Miscellaneous Camera Connections ..................................................................60
Table 10-1. SDIO Pin Descriptions..........................................................................................61
Table 10-2. SD Card and SDIO Interface Signal Routing Requirements ..............................62
Table 10-3. SD Card and SDIO Signal Connections ...............................................................63
Table 11-1. Audio Pin Descriptions.........................................................................................64
Table 11-2. I2S Interface Signal Routing Requirements .......................................................65
Table 11-3. Audio Signal Connection......................................................................................66
Table 12-1. I2C Pin Descriptions.............................................................................................67

NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | xi
Table 12-2. I2C Interface Signal Routing Requirements .......................................................69
Table 12-3. I2C Signal Connections ........................................................................................69
Table 12-4. SPI Pin Descriptions.............................................................................................70
Table 12-5. SPI Interface Signal Routing Requirements.......................................................71
Table 12-6. SPI Signal Connections........................................................................................72
Table 12-7. UART Pin Descriptions.........................................................................................72
Table 12-8. UART Signal Connections ....................................................................................73
Table 12-9. CAN Pin Descriptions...........................................................................................74
Table 12-10. CAN Interface Signal Routing Requirements.....................................................74
Table 12-11. CAN Signal Connections......................................................................................75
Table 12-12. Fan Pin Descriptions............................................................................................75
Table 12-13. Debug UART Pin Descriptions.............................................................................76
Table 12-14. Debug UART Connections....................................................................................76
Table 13-1. Pins Pulled or Driven High by Xavier Prior to SYS_RESET* Inactive.................79
Table 13-2. Pins with External Pull-ups to Supply on before SYS_RESET* Inactive ...........80
Table 14-1. Unused MPIO Pins and Pin Group.......................................................................81
Table 18-1. Signal Type Codes ................................................................................................86
Table 18-2. Common High-Speed Interface Requirements..................................................89

NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 1
Chapter 1. Introduction
This design guide contains recommendations and guidelines for engineers to follow to create
a product that is optimized to achieve the best performance from the interfaces supported by
the NVIDIA®Jetson™Xavier™NX System-on-Module (SOM).
This design guide provides detailed information on the capabilities of the hardware module,
which may differ from supported configurations by provided software. Refer to software
release documentation for information on supported capabilities.
Note: All occurrences of USB 3.2 refer to "USB 3.2 Gen 1x1: SuperSpeed USB 5Gbps" and "USB
3.2 Gen 2x1: SuperSpeed USB 10Gbps" only. Also note that Gen 1x1 and Gen 2x1 are referred to
simply as Gen1 and Gen2 in this design guide.
!
IMPORTANT: Throughout the design guide, references to “master” and “slave” configurations
have been updated to “initiator” and “target” respectively.
1.1 References
Refer to the following list of documents or models for more information. Use the latest
revision of all documents.
Jetson Xavier NX Data Sheet
Xavier (SoC) Technical Reference Manual
Jetson Xavier NX Module Pinmux
Jetson Xavier NX Thermal Design Guide
Jetson Xavier NX SCL (Supported Component List)
1.2 Abbreviations and Definitions
Table 1-1 lists the abbreviations that may be used throughout this design and guide and their
definitions.

Introduction
NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 2
Table 1-1. Abbreviations and Definitions
Abbreviation
Definition
CAN Controller Area Network
CEC Consumer Electronic Control
CSI Camera Serial Interface
Diff Differential
DP DisplayPort
eDP Embedded DisplayPort
ESD Electrostatic Discharge
eMMC Embedded MMC
EMI Electromagnetic Interference
FET Field Effect Transistor
GPIO General Purpose Input Output
HDCP High-bandwidth Digital Content Protection
HDMI High Definition Multimedia Interface
I2C Inter IC Interface
I2S Inter IC Sound Interface
LCD Liquid Crystal Display
LDO Low Dropout (voltage regulator)
LPDDR4x Low Power Double Data Rate DRAM, Fourth generation
MDI Medium-Dependent Interface
MIL 1/1000th of an inch
MIPI Mobile Industry Processor Interface
mm Millimeter
PCIe Peripheral Component Interconnect Express interface
PCM Pulse Code Modulation
PHY Physical Interface (that is, USB PHY)
ps Pico-Seconds
PMIC Power Management Integrated Circuit
RJ45 8P8C modular connector used in Ethernet and other data links
RTC Real Time Clock
SD Card Secure Digital Card
SDIO Secure Digital I/O Interface
SE Single-Ended
SPI Serial Peripheral Interface
TMDS Transition-Minimized Differential Signaling
UART Universal Asynchronous Receiver-Transmitter
USB Universal Serial Bus

NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 3
Chapter 2. Jetson Xavier NX
The Jetson Xavier NX resides at the center of the embedded system solution and includes:
Power (PMIC/Regulators, etc.)
DRAM (8 GB, 128-bit LPDDR4x)
eMMC (16 GB)
Gigabit Ethernet Controller
Power Monitor
QSPI NOR (32 MB – Boot device)
In addition, a wide range of interfaces are available at the main connector for use on the
carrier board as shown in Table 2-1 and Figure 2-1.
Table 2-1. Jetson Xavier NX Interfaces
Category Function Category Function
USB USB 2.0 interface (3x) LAN Gigabit ethernet
USB 3.2 (1x) I2C 4x
PCIe PCIe (x1 and x4) UART 3x
Camera CSI (14 lanes: 3 x4 + 1 x2 or 6 x2) SPI 2x
Control, clock CAN 1x
Display HDMI/eDP/DP (2x) Fan FAN PWM and tach input
DP_AUX/HPD (2x), CEC (1x) Debug UART
Audio I2S interface (2x) System Power control, reset, alerts
Initiator clock Power Main input and battery back-up for RTC
SD Card/SDIO SD Card or SDIO interface (1x)

Jetson Xavier NX
NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 4
Figure 2-1. Jetson Xavier NX Block Diagram
Jetson Xavier NX
Gig abi t
Ethernet
LPDDR4x
8GB
eMMC
16GB
VDD_IN USB 2.0 3x
GBE_M DI
I2S 2x
I2C 1x–1.8V
CSI: 14 L ane s
3 x4 + 1 x2 or 6 x2
[E]DP/HDMI 2x
SD CARD/SDIO
USB 3.1 1x
SPI 2x
I2C 3x–3.3V
PCIe x1 + x4
CAM MCLK 2x
Power
Subsystem
PMIC
CPU /GP U & Co re R egs
Xavier
Power & Voltage
Mon i to rs
UART 3x
DP_AUX/DDC 2x
HPD 2x, CEC
CAN 1x
AUDIO MCLK
QS PI N OR
32M B
General Purpose
Clock s 2 x
PWM 3x

Jetson Xavier NX
NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 5
Table 2-2. Jetson Xavier NX Connector (260-Pin SO-DIMM) Pin Out
Matrix
Module Signal Name Pin # Pin # Module Signal Name Module Signal Name Pin # Pin # Module Signal Name
GND 1 2 GND PCIE0_RX0_P 133 134 PCIE0_TX0_N
CSI1_D0_N 3 4 CSI0_D0_N GND 135 136 PCIE0_TX0_P
CSI1_D0_P 5 6 CSI0_D0_P PCIE0_RX1_N 137 138 GND
GND 7 8 GND PCIE0_RX1_P 139 140 PCIE0_TX1_N
CSI1_CLK_N 9 10 CSI0_CLK_N GND 141 142 PCIE0_TX1_P
CSI1_CLK_P 11 12 CSI0_CLK_P CAN_RX 143 144 GND
GND 13 14 GND KEY KEY KEY KEY
CSI1_D1_N 15 16 CSI0_D1_N CAN_TX 145 146 GND
CSI1_D1_P 17 18 CSI0_D1_P GND 147 148 PCIE0_TX2_N
GND 19 20 GND PCIE0_RX2_N 149 150 PCIE0_TX2_P
CSI3_D0_N 21 22 CSI2_D0_N PCIE0_RX2_P 151 152 GND
CSI3_D0_P 23 24 CSI2_D0_P GND 153 154 PCIE0_TX3_N
GND 25 26 GND PCIE0_RX3_N 155 156 PCIE0_TX3_P
CSI3_CLK_N 27 28 CSI2_CLK_N PCIE0_RX3_P 157 158 GND
CSI3_CLK_P 29 30 CSI2_CLK_P GND 159 160 PCIE0_CLK_N
GND 31 32 GND USBSS_RX_N 161 162 PCIE0_CLK_P
CSI3_D1_N 33 34 CSI2_D1_N USBSS_RX_P 163 164 GND
CSI3_D1_P 35 36 CSI2_D1_P GND 165 166 USBSS_TX_N
GND 37 38 GND PCIE1_RX0_N 167 168 USBSS_TX_P
DP0_TXD0_N 39 40 CSI4_D2_N PCIE1_RX0_P 169 170 GND
DP0_TXD0_P 41 42 CSI4_D2_P GND 171 172 PCIE1_TX0_N
GND 43 44 GND PCIE1_CLK_N 173 174 PCIE1_TX0_P
DP0_TXD1_N 45 46 CSI4_D0_N PCIE1_CLK_P 175 176 GND
DP0_TXD1_P 47 48 CSI4_D0_P GND 177 178 MOD_SLEEP*
GND 49 50 GND PCIE_WAKE* 179 180 PCIE0_CLKREQ*
DP0_TXD2_N 51 52 CSI4_CLK_N PCIE0_RST* 181 182 PCIE1_CLKREQ*
DP0_TXD2_P 53 54 CSI4_CLK_P PCIE1_RST* 183 184 GBE_MDI0_N
GND 55 56 GND I2C0_SCL 185 186 GBE_MDI0_P
DP0_TXD3_N 57 58 CSI4_D1_N I2C0_SDA 187 188 GBE_LED_LINK
DP0_TXD3_P 59 60 CSI4_D1_P I2C1_SCL 189 190 GBE_MDI1_N
GND 61 62 GND I2C1_SDA 191 192 GBE_MDI1_P
DP1_TXD0_N 63 64 CSI4_D3_N I2S0_DOUT 193 194 GBE_LED_ACT
DP1_TXD0_P 65 66 CSI4_D3_P I2S0_DIN 195 196 GBE_MDI2_N
GND 67 68 GND I2S0_FS 197 198 GBE_MDI2_P
DP1_TXD1_N 69 70 DSI_D0_N I2S0_SCLK 199 200 GND
DP1_TXD1_P 71 72 DSI_D0_P GND 201 202 GBE_MDI3_N
GND 73 74 GND UART1_TXD 203 204 GBE_MDI3_P

Jetson Xavier NX
NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 6
Module Signal Name Pin # Pin # Module Signal Name Module Signal Name Pin # Pin # Module Signal Name
DP1_TXD2_N 75 76 DSI_CLK_N UART1_RXD 205 206 GPIO07
DP1_TXD2_P 77 78 DSI_CLK_P UART1_RTS* 207 208 GPIO08
GND 79 80 GND UART1_CTS* 209 210 CLK_32K_OUT
DP1_TXD3_N 81 82 DSI_D1_N GPIO09 211 212 GPIO10
DP1_TXD3_P 83 84 DSI_D1_P CAM_I2C_SCL 213 214 FORCE_RECOVERY*
GND 85 86 GND CAM_I2C_SDA 215 216 GPIO11
GPIO00 87 88 DP0_HPD GND 217 218 GPIO12
SPI0_MOSI 89 90 DP0_AUX_N SDMMC_DAT0 219 220 I2S1_DOUT
SPI0_SCK 91 92 DP0_AUX_P SDMMC_DAT1 221 222 I2S1_DIN
SPI0_MISO 93 94 HDMI_CEC SDMMC_DAT2 223 224 I2S1_FS
SPI0_CS0* 95 96 DP1_HPD SDMMC_DAT3 225 226 I2S1_SCLK
SPI0_CS1* 97 98 DP1_AUX_N SDMMC_CMD 227 228 GPIO13
UART0_TXD 99 100 DP1_AUX_P SDMMC_CLK 229 230 GPIO14
UART0_RXD 101 102 GND GND 231 232 I2C2_SCL
UART0_RTS* 103 104 SPI1_MOSI SHUTDOWN_REQ* 233 234 I2C2_SDA
UART0_CTS* 105 106 SPI1_SCK PMIC_BBAT 235 236 UART2_TXD
GND 107 108 SPI1_MISO POWER_EN 237 238 UART2_RXD
USB0_D_N 109 110 SPI1_CS0* SYS_RESET* 239 240 SLEEP/WAKE*
USB0_D_P 111 112 SPI1_CS1* GND 241 242 GND
GND 113 114 CAM0_PWDN GND 243 244 GND
USB1_D_N 115 116 CAM0_MCLK GND 245 246 GND
USB1_D_P 117 118 GPIO01 GND 247 248 GND
GND 119 120 CAM1_PWDN GND 249 250 GND
USB2_D_N 121 122 CAM1_MCLK VDD_IN 251 252 VDD_IN
USB2_D_P 123 124 GPIO02 VDD_IN 253 254 VDD_IN
GND 125 126 GPIO03 VDD_IN 255 256 VDD_IN
GPIO04 127 128 GPIO05 VDD_IN 257 258 VDD_IN
GND 129 130 GPIO06 VDD_IN 259 260 VDD_IN
PCIE0_RX0_N 131 132 GND
Legend
Ground Power

NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 7
Chapter 3. Developer Kit Feature
Considerations
The Jetson Xavier NX Developer Kit Carrier Board design files are provided as a reference
design. This chapter describes details necessary for designers to know to replicate certain
features if desired. In addition, aspects of the design that are specific to the NVIDIA Developer
Kit usage but not useful or supported on a custom carrier board are also identified.
Most of the features implemented on the Jetson Xavier NX Developer Kit carrier board design
can be duplicated by copying the connections from the P3509 carrier board reference design.
Some of the following features have aspects that would require additional information.
Button Power MCU (EFM8SB10F2G)
USB SuperSpeed Hub (Realtek RTS5489)
Power over Ethernet (PoE)
TI TXB0108 level shifters
ID EEPROM (Not to be copied from reference design)
3.1 Button Power MCU
The Developer Kit carrier board implements a button power MCU (EFM8SB10F2G). This device
is programmed with firmware that is available on the Jetson Download Center. The posting is
titled “Jetson AGX Xavier and Jetson Xavier NX Power Button Supervisor Firmware.” The
connections used on the reference design must be followed exactly and the firmware provided
must be used to ensure correct functionality.

Developer Kit Feature Considerations
NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 8
3.2 USB SuperSpeed Hub
The USB SS hub design uses a Realtek RTS5420 device. The hub circuit includes a SPI FLASH
device which holds configuration information. A design intending to duplicate the developer kit
hub implementation should include the same SPI FLASH programmed to match, or the hub
should be customized with fuses with the same settings. The configuration in the SPI FLASH
includes the following:
Power enables (DPS1/2/3/4_PWR) set to be active high
Charging feature disabled
SSC valid
3.3 Power over Ethernet
The P3509 carrier board includes a 4-pin Power over Ethernet (PoE) header (J19) which brings
out the VC power pins of the Ethernet connector. In order to use this alternate PoE power
mechanism to power a custom carrier board, the design would require a power converter to
take the high voltage PoE supply (38V-60V) and convert it to the correct voltage for the custom
carrier board.
3.4 TI TXB0108 Level Shifters
The P3509 carrier board uses these level shifters to shift many of the signals going to the 40-
pin header from 1.8V to 3.3V. The design of these level shifters supports bidirectional signaling
without the use of a direction signal but has some side effects that should be considered. See
the
Jetson Nano Developer Kit 40-Pin Expansion Header GPIO Usage Considerations
Applications Note
for details.
3.5 Features Not to be Implemented
The Jetson Xavier NX Developer Kit carrier board features that should not be copied as they
are not required or useful for a custom carrier board design. The ID EEPROM (P3509 - U17) is
a feature that is used for NVIDIA internal purposes, but not useful on a custom design. A
similar function may be desired for a custom design, but the NVIDIA software will not interact
with these devices and the I2C address used by the developer kit carrier board ID EEPROM on
the I2C2 interface (7’h57) should be avoided.

NVIDIA Jetson Xavier NX DG-09693-001_v1.7 | 9
Chapter 4. Modular Connector
4.1 Module Connector Details
Jetson Xavier NX modules connect to the carrier board using a 260-pin SODIMM connector.
The mating connector used on the developer kit carrier board is listed in the Jetson Xavier NX
SCL (Supported Components List). This connector is a DDR4 SODIMM, 260-pin, right-angle,
standard key type. The full height of the connector is 9.2 mm. Refer to the connector
specification for details. Other heights are available.
4.2 Module to Mounting Hardware
The Jetson Xavier NX module is installed in the SODIMM connector which has latching
mechanisms to hold the board in place. In addition, it is required that the module is mounted
to the main carrier board PCB using metal standoffs and screws (or equivalent), both for
mechanical integrity and to provide additional grounding points. The developer kit uses
threaded standoffs that are hex, 4.5 mm widths (narrow diameter) x 6.57 ± 0.1 mm length.
These have M2.5 threads. The screws used are M2.5 x 3.7 mm, pad head.
Other SODIMM connector heights are available. If a different height connector is used, the
standoff height will have to be adjusted accordingly to account for the difference in height from
main PCB to module PCB.
Figure 4-1. Jetson Xavier NX Module Installed in SODIMM Connector
Standoffs
SO-DIMM
Connector
Jetson Xavier
NX Module
(Envelop view)
Mounting Screws