Nvidia Jetson TX2 NX User manual

DG-10141-001_v1.1 | September 2021
NVIDIA Jetson TX2 NX
Product Design Guide

NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | ii
Document History
DG-10141-001_v1.1
Version Date Description of Change
1.0 February 24, 2021 Initial Release
1.1 September 28, 2021 •Removed mention of interfaces for WiFi/BT in Table 2-1
“Jetson TX2 NX Interfaces”
•Updated Usage/Descriptions for PMIC_BBAT,
SHUTDOWN_REQ*, POWER_EN, SYS_RESET* and
MOD_SLEEP* in Table 5-1 “Jetson TX2 NX Power and
System Pin Descriptions”
•Updated SHUTDOWN_REQ* pull-up and MOD_SLEEP*
usage in Figure 5-1 “Jetson TX2 NX Power and Control
Block Diagram”
•Replaced much of the existing text with more detail per
power handshake signals in Section 5.1.1 “Power
Handshake Signals”
•Updated to include timing relationships in Figure 5-3
“Power Up Sequence (No Power Button – Auto-Power-
On)”
•Added sequence in Figure 5-4 “Power-up Sequence
(With Power Button)”
•Updated to include timing relationships in Figure 5-5
“Power Down – Initiated by SHUTDOWN_REQ*
Assertion”
•Updated to move GPIO00 to load switch and USB VBUS
Detect to available GPIO in Figure 6-1 “USB Connection
Example”
•Added box and note reference related to AC Caps on
Tegra RX lines in Figure 6-7 “Example PCIe
Connections”

NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | iii
Table of Contents
Chapter 1. Introduction...........................................................................................1
1.1 References.......................................................................................................................... 1
1.2 Abbreviations and Definitions............................................................................................ 2
Chapter 2. Jetson TX2 NX .......................................................................................4
Chapter 3. Developer Kit Feature Considerations ..................................................7
3.1 Button Power MCU............................................................................................................. 7
3.2 USB SuperSpeed Hub ........................................................................................................ 8
3.3 Power over Ethernet .......................................................................................................... 8
3.4 TI TXB0108 Level Shifters .................................................................................................. 8
3.5 Features Not to be Implemented ...................................................................................... 8
Chapter 4. Module Connector.................................................................................9
4.1 Module Connector Details ................................................................................................. 9
4.2 Module to Mounting Hardware.......................................................................................... 9
4.3 Module Installation and Removal.................................................................................... 10
Chapter 5. Power ..................................................................................................11
5.1 Power Supply and Sequencing ........................................................................................ 12
5.1.1 Power Handshake Signals......................................................................................... 12
5.1.2 Power Sequencing ..................................................................................................... 14
Chapter 6. USB and PCI Express..........................................................................16
6.1 USB ................................................................................................................................... 18
6.1.1 USB 2.0 Design Guidelines........................................................................................ 19
6.1.2 USB 3.0 Design Guidelines........................................................................................ 19
6.1.3 Common USB Routing Guidelines ............................................................................ 22
6.2 PCIe................................................................................................................................... 23
6.2.1 PCIe Design Guidelines ............................................................................................. 25
6.3 Gigabit Ethernet ............................................................................................................... 27
Chapter 7. Display.................................................................................................30
7.1 MIPI DSI ............................................................................................................................ 30
7.1.1 MIPI DSI and CSI Design Guidelines......................................................................... 31
7.1.2 MIPI DSI and CSI Connection Guidelines.................................................................. 32
7.2 HDMI, eDP, and DP .......................................................................................................... 32
7.2.1 eDP and DP ................................................................................................................ 33
7.2.1.1 eDP and DP Routing Guidelines......................................................................... 34
7.2.2 HDMI ........................................................................................................................... 38
7.2.2.1 HDMI Routing Guidelines ................................................................................... 39

NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | iv
Chapter 8. MIPI CSI Video Input............................................................................46
8.1 CSI Design Guidelines...................................................................................................... 50
Chapter 9. SD Card and SDIO ...............................................................................51
Chapter 10. Audio ...................................................................................................54
Chapter 11. Miscellaneous Interfaces....................................................................57
11.1 I2C ................................................................................................................................. 57
11.1.1 I2C Design Guidelines................................................................................................ 58
11.2 SPI ................................................................................................................................. 60
11.2.1 SPI Design Guidelines................................................................................................ 61
11.3 CAN ................................................................................................................................. 62
11.4 Fan ................................................................................................................................. 62
11.5 UART ................................................................................................................................. 63
11.6 Debug................................................................................................................................ 64
11.6.1 Debug UART ............................................................................................................... 65
Chapter 12. PADS ...................................................................................................66
12.1 Internal Pull-ups for Dual-Voltage Block Pins Powered at 1.8V................................... 66
12.2 Schmitt Trigger Usage..................................................................................................... 66
12.3 Pins Pulled and Driven High During Power-ON............................................................. 67
Chapter 13. Unused Interface Terminations ..........................................................69
13.1 Unused Multi-purpose Standard CMPS Pad Interfaces ................................................ 69
Chapter 14. Jetson TX2 NX Pin Descriptions and Design Checklist.......................70
Chapter 15. General Routing Guidelines ................................................................71
15.1 Signal Name Conventions................................................................................................ 71
15.2 Routing Guideline Format................................................................................................ 72
15.3 Signal Routing Conventions............................................................................................. 72
15.4 General Routing Guidelines............................................................................................. 72
15.5 General PCB Routing Guidelines .................................................................................... 73
15.6 Common High-Speed Interface Requirements.............................................................. 74

NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | v
List of Figures
Figure 2-1. Jetson TX2 NX Block Diagram...............................................................................5
Figure 4-1. Jetson TX2 NX Module Installed in SODIMM Connector......................................9
Figure 4-2. Module to Connector Assembly Diagram ...........................................................10
Figure 5-1. Jetson TX2 NX Power and Control Block Diagram ............................................12
Figure 5-2. System Power and Control Block Diagram........................................................14
Figure 5-3. Power Up Sequence (No Power Button – Auto Power-On) ...............................14
Figure 5-4. Power-Up Sequence (With Power Button)..........................................................15
Figure 5-5. Power Down – Initiated by SHUTDOWN_REQ* Assertion..................................15
Figure 5-6. Power Down – Sudden Power Loss ....................................................................15
Figure 6-1. USB Connection Example....................................................................................18
Figure 6-2. IL/NEXT Plot .........................................................................................................21
Figure 6-3. Trace Spacing for TX/RX Non-Interleaving.........................................................21
Figure 6-4. Via Structures.......................................................................................................22
Figure 6-5. ESD Layout Recommendations...........................................................................22
Figure 6-6. Component Order.................................................................................................22
Figure 6-7. Example PCIe Connections..................................................................................24
Figure 6-8. AC Cap Voiding .....................................................................................................26
Figure 6-9. Jetson TX2 NX Ethernet Connections .................................................................28
Figure 6-10. Gigabit Ethernet Magnetics and RJ45 Connections...........................................28
Figure 7-1. DSI 1 x 2 Lane Connection Example....................................................................31
Figure 7-2. DP and eDP Connection Example on DP0 Pins..................................................34
Figure 7-3. eDP Differential Main Link Topology...................................................................34
Figure 7-4. S-parameter .........................................................................................................37
Figure 7-5. Via Topology #1 ....................................................................................................37
Figure 7-6. Via Topology #2 ....................................................................................................37
Figure 7-7. HDMI Connection Example..................................................................................38
Figure 7-8. HDMI CLK and Data Topology .............................................................................39
Figure 7-9. IL and FEXT Plot ...................................................................................................42
Figure 7-10. TDR Plot................................................................................................................42
Figure 7-11. HDMI Via Topology ...............................................................................................43
Figure 7-12. Add-on Components – Top ..................................................................................43
Figure 7-13. Add-on Components – Bottom ............................................................................43
Figure 7-14. AC Cap Void ..........................................................................................................43
Figure 7-15. RPD, Chock, FET Placement ...............................................................................43
Figure 7-16. ESD Footprint .......................................................................................................44
Figure 7-17. ESD Void................................................................................................................44
Figure 7-18. SMT Pad Trace Entering ......................................................................................44

NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | vi
Figure 7-19. SMT Pad Trace Between......................................................................................44
Figure 7-20. Connector Voiding ................................................................................................44
Figure 8-1. 4 Lane CSI Camera Connection Example...........................................................47
Figure 8-2. Available Camera Control Pins ...........................................................................48
Figure 8-3. CSI Connection Options .......................................................................................49
Figure 9-1. SD Card Connection Example .............................................................................52
Figure 10-1. Audio Connections................................................................................................55
Figure 10-2. Audio Codec Connections ....................................................................................55
Figure 11-1. I2C Connections....................................................................................................58
Figure 11-2. SPI Connections ...................................................................................................60
Figure 11-3. Basic SPI Master and Slave Connections ...........................................................61
Figure 11-4. SPI Topologies ......................................................................................................61
Figure 11-5. Jetson TX2 NX CAN Connections ........................................................................62
Figure 11-6. Jetson TX2 NX Fan Connections..........................................................................63
Figure 11-7. Jetson TX2 NX UART Connections ......................................................................64
Figure 11-8. Debug UART Connections....................................................................................65
Figure 15-1. GSSG Stack-Up.....................................................................................................73
Figure 15-2. Common Mode Choke..........................................................................................75
Figure 15-3. Serpentine ............................................................................................................75

NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | vii
List of Tables
Table 1-1. Abbreviations and Definitions................................................................................2
Table 2-1. Jetson TX2 NX Interfaces.......................................................................................4
Table 2-2. Jetson TX2 NX Connector Pinout Matrix...............................................................5
Table 5-1. Jetson TX2 NX Power and System Pin Descriptions ..........................................11
Table 6-1. Jetson TX2 NX USB 2.0 Pin Descriptions............................................................16
Table 6-2. Jetson TX2 NX USB 3.0 and PCIe Pin Descriptions............................................16
Table 6-3. Jetson TX2 NX USB 3.0 and PCIe Lane Mapping Configurations......................17
Table 6-4. USB 2.0 Interface Signal Routing Requirements ...............................................19
Table 6-5. USB 3.0 Interface Signal Routing Requirements ...............................................19
Table 6-6. USB 2.0 Signal Connections ................................................................................23
Table 6-7. Miscellaneous USB 2.0 Signal Connections .......................................................23
Table 6-8. USB 3.0 Signal Connections ................................................................................23
Table 6-9. PCIe Interface Signal Routing Requirements.....................................................25
Table 6-10. PCIe Signal Connections......................................................................................26
Table 6-11. Jetson TX2 NX Gigabit Ethernet Pin Description................................................27
Table 6-12. Ethernet MDI Interface Signal Routing Requirements ......................................29
Table 6-13. Ethernet Signal Connections...............................................................................29
Table 7-1. Jetson TX2 NX Display General Pin Description.................................................30
Table 7-2. Jetson TX2 NX DSI Pin Description .....................................................................30
Table 7-3. MIPI DSI and CSI Interface Signal Routing Requirements ................................31
Table 7-4. MIPI DSI Signal Connections ...............................................................................32
Table 7-5. Jetson TX2 NX eDP and DP Pin Description.......................................................32
Table 7-6. DisplayPort and HDMI Pin Mapping....................................................................33
Table 7-7. eDP/DP Main Link Signal Routing Requirements including DP_AUX...............35
Table 7-8. eDP and DP Signal Connections .........................................................................37
Table 7-9. HDMI Interface Signal Routing Requirements ...................................................39
Table 7-10. HDMI Signal Connections ....................................................................................45
Table 8-1. Jetson TX2 NX CSI Pin Description .....................................................................46
Table 8-2. Jetson TX2 NX Camera Miscellaneous Pin Description.....................................47
Table 8-3. CSI Configuration .................................................................................................48
Table 8-4. MIPI CSI Signal Connections ...............................................................................50
Table 8-5. Miscellaneous Camera Connections ..................................................................50
Table 9-1. Jetson TX2 NX SDIO Pin Description...................................................................51
Table 9-2. SD Card and SDIO Interface Signal Routing Requirements ..............................52
Table 9-3. SD Card and SDIO Signal Connections ...............................................................53
Table 10-1. Jetson TX2 NX Audio Pin Description..................................................................54
Table 10-2. Interface Signal Routing Requirements..............................................................56

NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | viii
Table 10-3. Audio Signal Connections ....................................................................................56
Table 11-1. Jetson TX2 NX I2C Pin Description......................................................................57
Table 11-2. I2C Interface Signal Routing Requirements .......................................................59
Table 11-3. I2C Signal Connections ........................................................................................59
Table 11-4. Jetson TX2 NX SPI Pin Description .....................................................................60
Table 11-5. SPI Interface Signal Routing Requirements.......................................................61
Table 11-6. Jetson TX2 NX CAN Pin Description....................................................................62
Table 11-7. Jetson TX2 NX Fan Pin Description.....................................................................63
Table 11-8. Jetson TX2 NX UART Pin Description..................................................................63
Table 11-9. UART Signal Connections ....................................................................................64
Table 11-10. Jetson TX2 NX Debug UART Description ............................................................64
Table 11-11. Debug UART Connections....................................................................................65
Table 12-1. Pins Pulled and Driven High by Tegra X2 Prior to SYS_RESET* Inactive..........67
Table 12-2. Pins Pulled High on Module with External Resistors Prior to SYS_RESET_IN*
Inactive..................................................................................................................68
Table 13-1. Unused MPIO Pins and Pin Groups.....................................................................69
Table 15-1. Signal Type Codes ................................................................................................71
Table 15-2. Common High-Speed Interface Requirements..................................................74

NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | 1
Chapter 1. Introduction
This design guide contains recommendations and guidelines for engineers to follow in
creating a product that is optimized to achieve the best performance from the interfaces
supported by the NVIDIA®Jetson™TX2 NX System-on-Module (SOM).
This design guide provides detailed information on the capabilities of the hardware module,
which may differ from supported configurations by provided software. Refer to software
release documentation for information on supported capabilities.
Note: Most of the interface usage noted in this design guide is based on the NVIDIA®Jetson™
Xavier™NX developer kit carrier board design. References to the “DevKit carrier board” in the pin
descriptions and elsewhere are referring to the Jetson Xavier NX developer kit carrier board.
1.1 References
Refer to the following list of documents or models for more information. Always use the latest
revision of all documents.

Jetson TX2 NX Module Data Sheet
 Tegra X2 (SoC) Technical Reference Manual
 Jetson Xavier NX Developer Kit Carrier Board Specification
 Jetson TX2 NX Module Pinmux
 Jetson TX2 NX Thermal Design Guide
 Jetson Xavier NX Developer Kit Carrier Board Design Files
 Jetson Xavier NX Developer Kit Carrier Board BOM
 Jetson TX2 NX SCL (Supported Component List)

Introduction
NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | 2
1.2 Abbreviations and Definitions
Table 1-1 lists abbreviations that may be used throughout this design guide and their
definitions.
Table 1-1. Abbreviations and Definitions
Abbreviation Definition
CAN Controller Area Network
CEC Consumer Electronic Control
CSI Camera Serial Interface
Diff Differential
DP VESA®DisplayPort™(output)
DSI Display Serial Interface
eDP Embedded DisplayPort
ESD Electrostatic Discharge
eMMC Embedded MMC
EMI Electromagnetic Interference
FET Field Effect Transistor
GPIO General Purpose Input Output
HDCP High-bandwidth Digital Content Protection
HDMI™High-Definition Multimedia Interface
I2C Inter IC Interface
I2S Inter IC Sound Interface
LCD Liquid Crystal Display
LDO Low Dropout (voltage regulator)
LPDDR4 Low Power Double Data Rate DRAM, Fourth generation
MDI Medium-Dependent Interface
MIL 1/1000th of an inch
MIPI Mobile Industry Processor Interface
mm Millimeter
PCIe Peripheral Component Interconnect Express interface
PCM Pulse Code Modulation
PHY Physical Interface (i.e. USB PHY)
ps Pico-Seconds
PMU Power Management Unit
RJ45 8P8C modular connector used in Ethernet and other data
links

Introduction
NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | 3
Abbreviation Definition
RTC Real Time Clock
SD Card Secure Digital Card
SDIO Secure Digital I/O Interface
SE Single-Ended
SODIMM Small Outline Dual In-line Memory Module
SPI Serial Peripheral Interface
TMDS Transition-minimized differential signaling
UART Universal Asynchronous Receiver-Transmitter
USB Universal Serial Bus

NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | 4
Chapter 2. Jetson TX2 NX
The Jetson TX2 NX module resides at the center of the embedded system solution and
includes the following:
Power (PMIC/Regulators, etc.)
DRAM (LPDDR4)
eMMC
Gigabit Ethernet Controller
Power Monitor
In addition, a wide range of interfaces are available at the main connector for use on the
carrier board as shown Table 2-1 and Figure 2-1.
Table 2-1. Jetson TX2 NX Interfaces
Category
Function
Category
Function
USB USB 2.0 Interface (3x) CAN 1x
USB 3.0 (1x) LAN Gigabit Ethernet
PCIe PCIe (1 x1 + 1 x2) I2C 4x
Camera CSI (3 x4 or 2 x4 + 2 x2, 1 x4 + 4 x2, or 5 x2), Control,
Clock
UART 3x
Display
eDP/DP SPI 2x
HDMI/DP Interface (w/CEC) Fan FAN PWM and Tach Input
DSI (1, 2-lane), Display/Backlight Control Debug UART
Audio I2S Interface (4x) and Clock System Power Control, Reset, alerts
SD Card/SDIO SD Card or SDIO Interface (1x) Power Main Input and battery back-up for RTC

Jetson TX2 NX
NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | 5
Figure 2-1. Jetson TX2 NX Block Diagram
Jetson TX2 NX
Giga bi t
Ethernet
LPDDR4
4GB
eMMC
16GB
VDD_IN USB 2.0 x3
GBE_M DI
AUDIO MCLK
I2S x4
I2C x1–1.8V
CSI: 3 x4 or 5 x2
(e)DP/HDMI x2
SD CARD/SDIO
USB 3 .0 x1
SPI x2
I2C x3–3.3V
DSI, 2-lane x1
PCIe 1 x1 + 1 x2
CAM MCLK x2
Misc. Clocks 2x
P owe r
Su bs yst em
PMIC
CPU /GP U & Co re R egs
Tegra X2
Power & Vo ltage
Mon i to rs
UART x3
DP_AUX/DDC 2x
HPD 2x, CEC
CANPWM 3x
Table 2-2 lists the 260-pin SODIMM description for the Jetson TX2 NX connector.
Table 2-2. Jetson TX2 NX Connector Pinout Matrix
Module Signal Name
Pin #
Pin #
Module Signal Name
Module Signal Name
Pin #
Pin #
Module Signal Name
GND
1
2
GND
PCIE0RX0P
133
134
PCIE0TX0N
CSI1D0N
3
4
CSI0D0N
GND
135
136
PCIE0TX0P
CSI1D0P
5
6
CSI0D0P
PCIE0 RX1 N
137
138
GND
GND
7
8
GND
PCIE0RX1P
139
140
PCIE0TX1N
CSI1 CLK N
9
10
CSI0 CLK N
GND
141
142
PCIE0TX1P
CSI1 CLK P
11
12
CSI0 CLK P
(CAN RX) RSVD
143
144
GND
GND
13
14
GND
KEY
KEY
KEY
KEY
CSI1D1N
15
16
CSI0D1N
(CAN TX) RSVD
145
146
GND
CSI1D1P
17
18
CSI0D1P
GND
147
148
PCIE0TX2N
GND
19
20
GND
PCIE0 RX2 N
149
150
PCIE0TX2P
CSI3D0N
21
22
CSI2D0N
PCIE0RX2P
151
152
GND
CSI3D0P
23
24
CSI2D0P
GND
153
154
PCIE0TX3N
GND
25
26
GND
PCIE0 RX3 N (RSVD)
155
156
PCIE0TX3P
CSI3 CLK N
27
28
CSI2 CLK N
PCIE0 RX3 P (RSVD)
157
158
GND
CSI3 CLK P
29
30
CSI2 CLK P
GND
159
160
PCIE0 CLK N
GND
31
32
GND
USBSSRXN
161
162
PCIE0 CLK P
CSI3D1N
33
34
CSI2D1N
USBSSRXP
163
164
GND
CSI3D1P
35
36
CSI2D1P
GND
165
166
USBSS TX N
GND
37
38
GND
(PCIE1 RX0 N) RSVD
167
168
USBSSTXP
DP0 TXD0 N
39
40
CSI4D2N
(PCIE1 RX0 P) RSVD
169
170
GND
DP0 TXD0 P
41
42
CSI4D2P
GND
171
172
(PCIE1 TX0 N) RSVD
GND
43
44
GND
RSVD
173
174
(PCIE1 TX0 N) RSVD
DP0 TXD1 N
45
46
CSI4D0N
RSVD
175
176
GND
DP0 TXD1 P
47
48
CSI4D0P
GND
177
178
MOD SLEEP*
GND
49
50
GND
PCIE WAKE*
179
180
PCIE0 CLKREQ*
DP0 TXD2 N
51
52
CSI4 CLK N
PCIE0 RST*
181
182
(PCIE1 CLKREQ*) RSVD
DP0 TXD2 P
53
54
CSI4 CLK P
(PCIE1 TX0 N) RSVD
183
184
GBE MDI0 N
GND
55
56
GND
I2C0 SCL
185
186
GBE MDI0 P
DP0 TXD3 N
57
58
CSI4D1N
I2C0 SDA
187
188
GBE LED LINK
DP0 TXD3 P
59
60
CSI4D1P
I2C1 SCL
189
190
GBE MDI1 N
GND
61
62
GND
I2C1 SDA
191
192
GBE MDI1 P
DP1 TXD0 N
63
64
CSI4D3N
I2S0 DOUT
193
194
GBE LED ACT
DP1 TXD0 P
65
66
CSI4D3P
I2S0 DIN
195
196
GBE MDI2 N
GND
67
68
GND
I2S0 FS
197
198
GBE MDI2 P
DP1 TXD1 N
69
70
DSI D0 N
I2S0 SCLK
199
200
GND
DP1 TXD1 P
71
72
DSI D0 P
GND
201
202
GBE MDI3 N
GND
73
74
GND
UART1 TXD
203
204
GBE MDI3 P
DP1 TXD2 N
75
76
DSI CLK N
UART1 RXD
205
206
GPIO07

Jetson TX2 NX
NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | 6
Module Signal Name
Pin #
Pin #
Module Signal Name
Module Signal Name
Pin #
Pin #
Module Signal Name
DP1 TXD2 P
77
78
DSI CLK P
UART1 RTS*
207
208
GPIO08
GND
79
80
GND
UART1 CTS*
209
210
CLK 32K OUT
DP1 TXD3 N
81
82
DSI D1 N
GPIO09
211
212
GPIO10
DP1 TXD3 P
83
84
DSI D1 P
CAM I2C SCL
213
214
FORCE RECOVERY*
GND
85
86
GND
CAM I2C SDA
215
216
GPIO11
GPIO00
87
88
DP0 HPD
GND
217
218
GPIO12
SPI0 MOSI
89
90
DP0 AUX N
SDMMC DAT0
219
220
I2S1 DOUT
SPI0 SCK
91
92
DP0 AUX P
SDMMC DAT1
221
222
I2S1 DIN
SPI0 MISO
93
94
HDMI CEC
SDMMC DAT2
223
224
I2S1 FS
SPI0 CS0*
95
96
DP1 HPD
SDMMC DAT3
225
226
I2S1 SCLK
SPI0 CS1*
97
98
DP1 AUX N
SDMMC CMD
227
228
GPIO13
UART0 TXD
99
100
DP1 AUX P
SDMMC CLK
229
230
GPIO14
UART0 RXD
101
102
GND
GND
231
232
I2C2 SCL
UART0 RTS*
103
104
SPI1 MOSI
SHUTDOWN REQ*
233
234
I2C2 SDA
UART0 CTS*
105
106
SPI1 SCK
PMIC BBAT
235
236
UART2 TXD
GND
107
108
SPI1 MISO
POWER EN
237
238
UART2 RXD
USB0 D N
109
110
SPI1 CS0*
SYS RESET*
239
240
SLEEP/WAKE*
USB0 D P
111
112
SPI1 CS1*
GND
241
242
GND
GND
113
114
CAM0 PWDN
GND
243
244
GND
USB1 D N
115
116
CAM0 MCLK
GND
245
246
GND
USB1 D P
117
118
GPIO01
GND
247
248
GND
GND
119
120
CAM1 PWDN
GND
249
250
GND
USB2 D N
121
122
CAM1 MCLK
VDD IN
251
252
VDD IN
USB2 D P
123
124
GPIO02
VDD IN
253
254
VDD IN
GND
125
126
GPIO03
VDD IN
255
256
VDD IN
GPIO04
127
128
GPIO05
VDD IN
257
258
VDD IN
GND
129
130
GPIO06
VDD IN
259
260
VDD IN
PCIE0 RX0 N
131
132
GND
Legend
Ground
Power
Reserved - must be left unconnected
Note: Refer to the Jetson TX2 NX pin description spreadsheet attached to this design guide for
more details.

NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | 7
Chapter 3. Developer Kit Feature
Considerations
The Jetson TX2 NX module is compatible with the NVIDIA Jetson Xavier NX Developer Kit. The
Jetson Xavier NX Developer Kit carrier board design files are provided as a reference design.
This chapter describes details necessary for designers to know to replicate certain features if
desired. In addition, aspects of the design that are specific to the NVIDIA developer kit usage
but not useful or supported on a custom carrier board are also identified.
Most of the features implemented on the Jetson Xavier NX Developer Kit carrier board design
can be duplicated by copying the connections from the P3509 carrier board reference design.
Some of the following features have aspects that would require additional information.
Button Power MCU (EFM8SB10F2G)
USB SuperSpeed Hub (Realtek RTS5420)
Power over Ethernet (PoE)
TI TXB0108 level shifters
ID EEPROM (Not recommended to be copied from reference design)
3.1 Button Power MCU
The developer kit carrier board implements a button power MCU (EFM8SB10F2G). This device
is programmed with firmware that is available on the Jetson Download Center. The posting is
titled
Jetson AGX Xavier and Jetson Xavier NX Power Button Supervisor Firmware . The
connections used on the reference design must be followed exactly and the firmware provided
must be used to ensure correct functionality.

Developer Kit Feature Considerations
NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | 8
3.2 USB SuperSpeed Hub
The USB SS hub design uses a Realtek RTS5420 device. The hub circuit includes an SPI FLASH
device which holds configuration information. A design intending to duplicate the developer kit
hub implementation should include the same SPI FLASH programmed to match, or the hub
should be customized with fuses with the same settings. The configuration in the SPI FLASH
includes the following:
Power enables (DPS1/2/3/4_PWR) set to be active high
Charging feature disabled
SSC valid
3.3 Power over Ethernet
The P3509 carrier board includes a 4-pin Power over Ethernet (PoE) header (J19) which brings
out the VC power pins of the Ethernet connector. To use this alternate PoE power mechanism
to power a custom carrier board, the design would require a power converter to take the high
voltage PoE supply (38V-60V) and convert it to the correct voltage for the custom carrier board.
3.4 TI TXB0108 Level Shifters
The P3509 carrier board uses these level shifters to shift many of the signals going to the 40-
pin header from 1.8V to 3.3V. The design of these level shifters supports bidirectional signaling
without the use of a direction signal but has some side effects that should be considered. See
the
Jetson Nano Developer Kit 40-Pin Expansion Header GPIO Usage Considerations
Application Note
for details.
3.5 Features Not to be Implemented
The Jetson Xavier NX Developer Kit carrier board has some features that should not be copied
as they are not required or useful for a custom carrier board design. The ID EEPROM (P3509 -
U17) is a feature that is used for NVIDIA internal purposes, but not useful on a custom design.
A similar function may be desired for a custom design, but the NVIDIA software will not
interact with these devices and the I2C address used by the developer kit carrier board ID
EEPROM on the I2C2 interface (7’h57) should be avoided.

NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | 9
Chapter 4. Module Connector
4.1 Module Connector Details
Jetson TX2 NX modules connect to the carrier board using a 260-pin SODIMM connector. The
mating connector used on the developer kit carrier board is listed in the Jetson TX2 NX
Supported Components List (SCL). This connector is a DDR4 SODIMM, 260-pin, right-angle,
standard key type. The full height of the connector is 9.2 mm. Refer to the connector
specification for details. Other heights are available.
4.2 Module to Mounting Hardware
The Jetson TX2 NX module is installed in the SODIMM connector which has latching
mechanisms to hold the board in place. In addition, it is required that the module is mounted
to the main carrier board PCB using metal standoffs and screws (or equivalent), both for
mechanical integrity and to provide additional grounding points. The developer kit uses
threaded standoffs that are hex, 4.5 mm widths (narrow diameter) x 6.57 ± 0.1 mm length.
These have M2.5 threads. The screws used are M2.5 x 3.7 mm, pan head.
Other SODIMM connector heights are available. If a different height connector is used, the
standoff height will have to be adjusted accordingly to account for the difference in height from
main PCB to module PCB.
Figure 4-1. Jetson TX2 NX Module Installed in SODIMM Connector
Standoffs
SO-DIMM
Connector
Jetson TX2 NX
Module
(Envelope view)
Mounting
Screws

Module Connector
NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | 10
4.3 Module Installation and Removal
To install the Jetson TX2 NX module correctly, follow the sequence and mounting hardware
instructions:
Here are some suggested assembly guidelines.
1. Assemble any required thermal solution on the module.
2. Install the Jetson TX2 NX module
a). Baseboard with suitable standoff for as per SODIMM connector height defined.
b). Insert module fully at an angle of 25-35 degree into the SODIMM connector.
c). Arc down the module board until the SODIMM connector latch engages.
d). Secure the Jetson TX2 NX module to the baseboard with screws into the
standoff/spacer. The developer kit (shown in Figure 4 2) uses a standoff and screws to
secure the module to the system/base- board.
Figure 4-2. Module to Connector Assembly Diagram
To remove the Jetson TX2 NX module correctly, follow the reverse of the installation sequence.

NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | 11
Chapter 5. Power
Power for the module is supplied on the VDD_IN pins and is nominally 5.0V (see the Jetson TX2
NX Data Sheet
for supply tolerance and maximum current).
!
CAUTION: Jetson TX2 NX is not hot-pluggable. When installing the module, the main power
supply should not be connected. Before removing the module, the main power supply (to VDD_IN
pins) must be disconnected and allowed to discharge below 0.6V.
Table 5-1. Jetson TX2 NX Power and System Pin Descriptions
Pin # Module Pin
Name
Tegra X2 Signal Usage/Description Usage on DevKit
Carrier Board
Direction Pin Type
251
↓
260
VDD_IN − Main power – Supplies PMIC and other regulators Main DC input Input 5.0V
235 PMIC_BBAT − PMIC Battery Back-up. Optionally used to provide back-up
power for the Real-Time-Clock (RTC). Connects to
Lithium Cell or super capacitor on Carrier Board. PMIC is
source when charging cap or coin cell. Super cap or coin
cell is source when system is disconnected from power.
Charging is enabled by default in software. If non-
rechargeable battery is to be used, charging should be
disabled.
Battery Back-up
using Super-
capacitor
Bidir Input
Range:
1.65V-5.5V
Output
Options:
2.5V, 3.0V,
3.3V, 3.5V
214
FORCE_
RECOVERY*
BUTTON_VOL_UP
Force Recovery strap pin. Held low when SYS_RESET*
goes high (i.e. during power-on) places system in USB
recovery mode.
Automation header
Input
CMOS –
1.8V
240
SLEEP/WAKE* BUTTON_PWR_ON Sleep/Wake. Configured as GPIO for optional use to
indicate the system should enter or exit sleep mode.
Automation header Input CMOS –
5.0V
233 SHUTDOWN_
REQ*
− Used by the module to request the carrier board to shut
down. ~5kΩ pull-up to VDD_IN (5V) on the module.
System Output Open Drain,
5.0V
237
POWER_EN (PMIC EN0
through converter
logic)
Signal for module on/off: high level on, low level off.
Connects to module PMIC EN0 through converter logic.
POWER_EN is routed to a Schmitt trigger buffer on the
module. 100kΩ pulldown on the module.
System Input Analog 5.0V
239 SYS_RESET* SYS_RESET_IN_N Module Reset. Reset to the module when driven low by the
carrier board. Used as carrier board supply enable when
driven high by the module when module power sequence
is complete. Used to ensure proper power on/off
sequencing for between module and carrier board
supplies. 10kΩ pull-up to 1.8V on the module.
Automation header Bidir Open Drain,
1.8V
178 MOD_SLEEP* GPIO_PA6 Module Sleep. When active (low), indicates module has
gone to Sleep (SC7) mode. This pin is controlled by system
software and should not be modified.
HDMI termination
pull-down FET
control disable
Output CMOS –
1.8V

Power
NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | 12
Pin # Module Pin
Name
Tegra X2 Signal Usage/Description Usage on DevKit
Carrier Board
Direction Pin Type
210 CLK_32K_OUT − Sleep/Suspend clock M.2 Key E Output CMOS –
1.8V
Notes:
1. In the Type/Dir column, Output is from Jetson TX2 NX. Input is to Jetson TX2 NX. Bidir is for Bidirectional signals.
2. The directions for FORCE_RECOVERY* and SLEEP/WAKE* signals are true when used for those functions. Otherwise as GPIOs,
the direction is bidirectional.
Figure 5-1. Jetson TX2 NX Power and Control Block Diagram
Jetson
Main 5V
Power
Source
255
256
257
258
259
260
235
Memory/Peripherals
LPDDR4, eMMC,
Ethernet
Power Subsystem
Tegra X2
PMIC_BBAT
VDD_IN
233
240
239
237
POWER_EN
SYS_RESET*
SLEEP/WAKE*
MOD_SLEEP *
SHUTDOWN_REQ*
To Carrier Board – Used to force
power off if shutdown request
(T he rm al S hu tdo wn , P owe r B ad o r
Software Shutdown, etc.) is received
From Carrier Board power
ON/ OF F c ont r ol l o gic
System Reset from Carrier
Board. Carrier Board power
enable f rom M odule.
Optional Sleep/Wake Button
SLE EP/W AKE
Super
Cap or
Li Cell
251
252
253
254
178
Indicates Module is entering
Sleep (SC7) mode
10 0k Ω10 kΩ
VDD_1V8
4. 7kΩ
VDD_1V8
10 0k Ω
VDD_1V8
Lev el
Shifter
~5kΩ
VDD_IN (5V)
5.1 Power Supply and Sequencing
This section details the power supply and sequencing for the Jetson TX2 NX module.
5.1.1 Power Handshake Signals
The carrier board receives the main power source and uses this to generate the enable to
Jetson TX2 NX (POWER_EN) after the carrier board has ensured the main supply is stable and
the associated decoupling capacitors have charged. The carrier board supplies are not
enabled at this time. Once POWER_EN is driven active (high), the module begins to Power-ON.
When the module Power-ON sequence has completed, the SYS_RESET* signal is released
(pulled high on module) and this is used by the carrier board to enable its various supplies.
Note: The carrier board cannot drive high or pull high any signals that are associated with the
module when the module rails are off. If the designer cannot guarantee a signal will not be
driven or pulled high, then either the power rail related to that signal should be left off, or the
signals would need to be buffered to isolate them from the module pins. The buffers should only
be enabled towards the module when SYS_RESET* goes high.