NXP Semiconductors QorIQ LS1012A User manual

QorIQ LS1012A Reference Manual
Document Number: LS1012ARM
Rev. 1, 01/2018

QorIQ LS1012A Reference Manual, Rev. 1, 01/2018
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Contents
Section number Title Page
Chapter 1
Overview
1.1 Introduction...................................................................................................................................................................171
1.2 Features summary......................................................................................................................................................... 172
1.3 Application examples....................................................................................................................................................174
1.3.1 Entry-level broadband Ethernet gateway.......................................................................................................174
1.3.2 Consumer NAS/DAS and battery-powered NAS applications......................................................................175
1.3.3 IoT gateways..................................................................................................................................................178
1.4 Chip features ................................................................................................................................................................ 180
1.4.1 Arm Cortex-A53 core.................................................................................................................................... 180
1.4.2 Arm CoreLink CCI-400 cache coherent interconnect................................................................................... 180
1.4.3 PreBoot loader and non-volatile memory interfaces......................................................................................181
1.4.4 Multi-mode DDR controller (MMDC).......................................................................................................... 181
1.4.5 Enhanced direct memory access (eDMA) and direct memory access multiplexer (DMAMUX)................. 181
1.4.6 DUART..........................................................................................................................................................182
1.4.7 FlexTimer module (FTM)..............................................................................................................................182
1.4.8 Universal serial bus (USB) 3.0 controller and PHY...................................................................................... 183
1.4.9 USB 2.0 controller with ULPI interface........................................................................................................ 183
1.4.10 High-speed I/O interfaces.............................................................................................................................. 184
1.4.10.1 Serial advanced technology attachment (SATA) controller...................................................... 184
1.4.10.2 PCI Express 2.0 interface...........................................................................................................185
1.4.10.3 SGMII........................................................................................................................................ 185
1.4.11 Integrated interchip sound (I2S) / synchronous audio interface (SAI).......................................................... 185
1.4.12 Enhanced secure digital host controller and SDIO........................................................................................ 186
1.4.13 Integrated security engine (SEC)................................................................................................................... 186
1.4.14 Inter-integrated circuit (I2C) controller......................................................................................................... 187
1.4.15 Quad serial peripheral interface (QuadSPI)...................................................................................................187
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Section number Title Page
1.4.16 Serial peripheral interface (SPI).....................................................................................................................188
1.4.17 Watchdog timer (WDOG)..............................................................................................................................188
Chapter 2
Memory Map
2.1 Overview.......................................................................................................................................................................189
2.2 System memory map.....................................................................................................................................................189
2.3 CCSR address map....................................................................................................................................................... 191
Chapter 3
Signal Descriptions
3.1 Signals Introduction......................................................................................................................................................195
3.2 Signals Overview..........................................................................................................................................................195
3.3 Configuration signals sampled at reset......................................................................................................................... 209
3.4 Signal multiplexing details........................................................................................................................................... 209
3.4.1 Ethernet controller 1, SAI, USB 2.0, and GPIO2 signal multiplexing.......................................................... 210
3.4.2 Ethernet management interface 1 and GPIO2 signal multiplexing................................................................212
3.4.3 eSDHC1 and GPIO1 signal multiplexing...................................................................................................... 212
3.4.4 eSDHC2, GPIO1, FTM, SAI, and SPI signal multiplexing...........................................................................214
3.4.5 GPIO1 and FTM signal multiplexing............................................................................................................ 215
3.4.6 I2C1, GPIO1, and FTM signal multiplexing................................................................................................. 215
3.4.7 QuadSPI, I2C, and GPIO1 signal multiplexing............................................................................................. 216
3.4.8 UART1 and GPIO signal multiplexing..........................................................................................................217
3.4.9 UART2, GPIO, and SAI signal multiplexing................................................................................................ 217
3.4.10 USB, ASLEEP, and GPIO1 signal multiplexing........................................................................................... 218
3.4.11 TA_TMP_DETECT_B and GPIO2 signal multiplexing...............................................................................218
3.5 Output Signal States During Reset............................................................................................................................... 219
Chapter 4
Reset, Clocking, and Initialization
4.1 Reset, clocking, and initialization overview.................................................................................................................221
4.2 External Signal Descriptions.........................................................................................................................................221
4.2.1 System control signals................................................................................................................................... 222
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4.2.1.1 RESET_REQ_B behavior..........................................................................................................223
4.2.2 External Clock Signals...................................................................................................................................223
4.3 Clocking register descriptions.......................................................................................................................................224
4.3.1 Clocking Memory map.................................................................................................................................. 224
4.3.2 Core cluster n clock control/status register (CLKC1CSR)............................................................................ 224
4.3.2.1 Offset..........................................................................................................................................224
4.3.2.2 Function..................................................................................................................................... 225
4.3.2.3 Diagram......................................................................................................................................225
4.3.2.4 Fields..........................................................................................................................................225
4.3.3 PLL cluster n general status register (PLLC1GSR).......................................................................................226
4.3.3.1 Offset..........................................................................................................................................226
4.3.3.2 Function..................................................................................................................................... 226
4.3.3.3 Diagram......................................................................................................................................226
4.3.3.4 Fields..........................................................................................................................................227
4.3.4 Platform clock domain control/status register (CLKPCSR)..........................................................................227
4.3.4.1 Offset..........................................................................................................................................227
4.3.4.2 Function..................................................................................................................................... 228
4.3.4.3 Diagram......................................................................................................................................228
4.3.4.4 Fields..........................................................................................................................................228
4.3.5 Platform PLL general status register (PLLPGSR).........................................................................................229
4.3.5.1 Offset..........................................................................................................................................229
4.3.5.2 Function..................................................................................................................................... 229
4.3.5.3 Diagram......................................................................................................................................229
4.3.5.4 Fields..........................................................................................................................................229
4.4 Functional description...................................................................................................................................................230
4.4.1 Power-on reset sequence................................................................................................................................230
4.4.2 Core Soft Reset.............................................................................................................................................. 233
4.4.3 Reset state timing...........................................................................................................................................233
4.4.4 Power-on reset configuration.........................................................................................................................234
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4.4.4.1 Reset configuration word (RCW) source...................................................................................235
4.4.4.2 Transconductance selection control...........................................................................................235
4.4.5 Reset configuration word (RCW).................................................................................................................. 235
4.4.5.1 RCW Field Definitions.............................................................................................................. 236
4.4.5.2 Hard-coded RCW options..........................................................................................................245
4.4.5.3 RCW settings for hard-coded options........................................................................................245
4.4.6 Clocking.........................................................................................................................................................247
4.4.6.1 Clocking mode........................................................................................................................... 247
4.4.6.1.1 Crystal based (internal oscillator mode) clocking.............................................. 248
4.4.6.1.2 External clock oscillator/generator based clocking (on-chip oscillator
bypassed).............................................................................................................248
4.4.6.2 Guidelines for crystal or external clock oscillator/generator usage with different interfaces....249
4.4.6.2.1 PCI Express use cases (with TX_CLK)..............................................................250
4.4.6.2.2 RGMII-only use cases.........................................................................................250
4.4.6.2.3 SGMII use cases................................................................................................. 251
4.4.6.2.4 SATA use cases.................................................................................................. 252
4.4.6.3 IP Logic Clock Distribution and Configuration.........................................................................253
4.4.6.4 CLK_OUT configuration...........................................................................................................255
Chapter 5
Interrupt Assignments
5.1 Introduction...................................................................................................................................................................257
5.2 Internal interrupt sources.............................................................................................................................................. 257
Chapter 6
Arm Modules
6.1 Introduction...................................................................................................................................................................261
6.2 Arm® Cortex®-A53 core............................................................................................................................................. 261
6.3 Arm generic interrupt controller (GIC-400)................................................................................................................. 262
6.4 On-Chip RAM memory controller (OCRAM)............................................................................................................. 263
Chapter 7
CSU, OCRAM, and MSCM
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7.1 Central Security Unit.................................................................................................................................................... 265
7.1.1 CSU Memory Map/Register Definition.........................................................................................................265
7.1.1.1 Config Security Level (CSU_CSL)........................................................................................... 266
7.1.1.2 Secure Access register (CSU_SAn)...........................................................................................271
7.1.2 Initialization Policy........................................................................................................................................275
7.2 On-Chip RAM memory controller (OCRAM)............................................................................................................. 275
7.3 Miscellaneous System Control Module (MSCM)........................................................................................................ 276
7.3.1 MSCM Access Control and TrustZone Security (ACTZS)Memory Map/Register Definition.....................276
7.3.1.1 ACTZS CSL Interrupt Enable Register (MSCM_ACTZS_CSLIER)....................................... 277
7.3.1.2 ACTZS CSL Interrupt Register (MSCM_ACTZS_CSLIR)......................................................279
7.3.1.3 ACTZS CSL Interrupt Overrun Register (MSCM_ACTZS_CSOVR)..................................... 281
7.3.2 ACTZS CSLn Fail Status Capture Registers (Memory Map/Register Definition)....................................... 284
7.3.2.1 ACTZS CSLn Fail Status Address (Low) Register (MSCM_CSFARn)...................................286
7.3.2.2 ACTZS CSLn Fail Status Control Register (MSCM_CSFCRn)...............................................287
7.3.2.3 ACTZS CSLn Fail Status Master ID Register (MSCM_CSFIRn)............................................ 288
7.3.2.4 ACTZS CSLn Fail Status Address (Low) Register (MSCM_CSFARn)...................................289
7.3.2.5 ACTZS CSLn Fail Status Control Register (MSCM_CSFCRn)...............................................290
7.3.2.6 ACTZS CSLn Fail Status Master ID Register (MSCM_CSFIRn)............................................ 291
7.3.2.7 ACTZS CSLn Fail Status Address (Low) Register (MSCM_CSFARn)...................................292
7.3.2.8 ACTZS CSLn Fail Status Control Register (MSCM_CSFCRn)...............................................293
7.3.2.9 ACTZS CSLn Fail Status Master ID Register (MSCM_CSFIRn)............................................ 294
7.3.2.10 ACTZS CSLn Fail Status Address (Low) Register (MSCM_CSFARn)...................................295
7.3.2.11 ACTZS CSLn Fail Status Control Register (MSCM_CSFCRn)...............................................296
7.3.2.12 ACTZS CSLn Fail Status Master ID Register (MSCM_CSFIRn)............................................ 297
Chapter 8
System Counter
8.1 Overview.......................................................................................................................................................................299
8.2 Secure system counter register descriptions................................................................................................................. 299
8.2.1 Secure_System_counter Memory map.......................................................................................................... 299
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8.2.2 Control register (CNTCR)............................................................................................................................. 300
8.2.2.1 Offset..........................................................................................................................................300
8.2.2.2 Function..................................................................................................................................... 300
8.2.2.3 Diagram......................................................................................................................................300
8.2.2.4 Fields..........................................................................................................................................300
8.2.3 LSB of counter count value register (CNTCV1)........................................................................................... 301
8.2.3.1 Offset..........................................................................................................................................301
8.2.3.2 Function..................................................................................................................................... 301
8.2.3.3 Diagram......................................................................................................................................301
8.2.3.4 Fields..........................................................................................................................................301
8.2.4 MSB of counter count value register (CNTCV2).......................................................................................... 302
8.2.4.1 Offset..........................................................................................................................................302
8.2.4.2 Function..................................................................................................................................... 302
8.2.4.3 Diagram......................................................................................................................................302
8.2.4.4 Fields..........................................................................................................................................302
8.2.5 Counter frequency mode table base frequency register (CNTFID0).............................................................303
8.2.5.1 Offset..........................................................................................................................................303
8.2.5.2 Function..................................................................................................................................... 303
8.2.5.3 Diagram......................................................................................................................................303
8.2.5.4 Fields..........................................................................................................................................303
8.3 Non-secure system counter register descriptions..........................................................................................................304
8.3.1 Non_secure_system_counter Memory map...................................................................................................304
8.3.2 LSB of Counter Count Value (CNCTV_RO1)..............................................................................................304
8.3.2.1 Offset..........................................................................................................................................304
8.3.2.2 Function..................................................................................................................................... 304
8.3.2.3 Diagram......................................................................................................................................305
8.3.2.4 Fields..........................................................................................................................................305
8.3.3 MSB of counter count value register (CNCTV2_RO2).................................................................................305
8.3.3.1 Offset..........................................................................................................................................305
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8.3.3.2 Function..................................................................................................................................... 305
8.3.3.3 Diagram......................................................................................................................................305
8.3.3.4 Fields..........................................................................................................................................306
Chapter 9
Cache Coherent Interconnect (CCI-400)
9.1 The Cache coherent interconnect (CCI-400) module as implemented on the chip...................................................... 307
9.2 Register Descriptions....................................................................................................................................................309
9.2.1 CCI400 Registers Memory map.................................................................................................................... 309
9.2.2 Control Override Register (Control_Override_Register).............................................................................. 312
9.2.2.1 Offset..........................................................................................................................................312
9.2.2.2 Function..................................................................................................................................... 312
9.2.2.3 Diagram......................................................................................................................................312
9.2.2.4 Fields..........................................................................................................................................313
9.2.3 Speculation Control Register (Speculation_Control_Register)..................................................................... 314
9.2.3.1 Offset..........................................................................................................................................314
9.2.3.2 Function..................................................................................................................................... 314
9.2.3.3 Diagram......................................................................................................................................314
9.2.3.4 Fields..........................................................................................................................................315
9.2.4 Secure Access Register (Secure_Access_Register).......................................................................................316
9.2.4.1 Offset..........................................................................................................................................316
9.2.4.2 Function..................................................................................................................................... 316
9.2.4.3 Diagram......................................................................................................................................316
9.2.4.4 Fields..........................................................................................................................................317
9.2.5 Status Register (Status_Register)...................................................................................................................317
9.2.5.1 Offset..........................................................................................................................................317
9.2.5.2 Function..................................................................................................................................... 317
9.2.5.3 Diagram......................................................................................................................................318
9.2.5.4 Fields..........................................................................................................................................318
9.2.6 Imprecise Error Register (Imprecise_Error_Register)...................................................................................319
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9.2.6.1 Offset..........................................................................................................................................319
9.2.6.2 Function..................................................................................................................................... 319
9.2.6.3 Diagram......................................................................................................................................319
9.2.6.4 Fields..........................................................................................................................................320
9.2.7 Snoop Control Registers (Snoop_Control_Register_S0 - Snoop_Control_Register_S4)............................. 320
9.2.7.1 Offset..........................................................................................................................................320
9.2.7.2 Function..................................................................................................................................... 320
9.2.7.3 Diagram......................................................................................................................................321
9.2.7.4 Fields..........................................................................................................................................321
9.2.8 Shareable Override Registers (Shareable_Override_Register_S0 - Shareable_Override_Register_S4).......322
9.2.8.1 Offset..........................................................................................................................................322
9.2.8.2 Function..................................................................................................................................... 322
9.2.8.3 Diagram......................................................................................................................................323
9.2.8.4 Fields..........................................................................................................................................323
9.2.9 Read Channel QoS Value Override Register (Read_Qos_Override_Register_S0 - Read_Qos_Override_
Register_S4)...................................................................................................................................................324
9.2.9.1 Offset..........................................................................................................................................324
9.2.9.2 Function..................................................................................................................................... 324
9.2.9.3 Diagram......................................................................................................................................324
9.2.9.4 Fields..........................................................................................................................................325
9.2.10 Write Qos Override Register (Write_Qos_Override_Register_S0 - Write_Qos_Override_Register_S4)....325
9.2.10.1 Offset..........................................................................................................................................325
9.2.10.2 Function..................................................................................................................................... 326
9.2.10.3 Diagram......................................................................................................................................326
9.2.10.4 Fields..........................................................................................................................................326
9.2.11 Qos Control Register (Qos_Control_Register_S0 - Qos_Control_Register_S4).......................................... 327
9.2.11.1 Offset..........................................................................................................................................327
9.2.11.2 Function..................................................................................................................................... 327
9.2.11.3 Diagram......................................................................................................................................327
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