NXP Semiconductors QN9090 User manual

JN-RM-2079
QN9090 module development reference manual
Rev. 1.0 —17 Jan 2020
Reference manual
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Keywords
QN9090, module
Abstract
Reference Manual for QN9090 modules and platform design.

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QN9090 module development reference manual
JN-RM-2079
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For more information, please visit: http://www.nxp.com
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1.0
20200117
Creation

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1. Introduction
This manual describes the hardware for the reference designs for modules based around
the NXP QN9090 wireless microcontroller. The NXP QN9090 modules are small, low-
power and cost-effective evaluation and development board or application prototyping
and demonstration of the QN9090 device.
The QN9090 is an ultra-low-power, highly integrated single-chip device that enables
Standard Bluetooth Low Energy RF connectivity for portable, extremely low-power
embedded systems.
The QN9090 SoC integrates a radio transceiver operating in the 2.4 GHz ISM band
supporting BLE Radio, an ARM Cortex-M4 processor, up to 640 kB flash,152 kB SRAM
and 128 kB ROM, BLE Link layer processing hardware and peripherals optimized to
meet the requirements of the target applications.
The design considerations presented in this manual are equally valid for bespoke
solutions where the QN9090 device is placed directly onto the product PCB.
Three modules models are available:
•QN9090-001-M10
•QN9090-001-M13
The models available are described in Table 1.
In order to complete a successful PCB design by your own the hardware guidelines
described in this reference manual must be followed as strictly as possible. Further
information on the QN9090 characteristics are available in the “QN9090 Bluetooth Low
Energy 5.0 Wireless Microcontroller” datasheet.
The QN9090-001-M10 module has been fitted to a mezzanine board (OM15077) for use
on the QN9090 evaluation kits. The module is known as QN9090-001-T10.
1.1 Audience
This guide is intended for systems designers
1.2 Regulatory approvals
The QN9090-001-M10 and M13 are compliant with:
•RED 2014/53/EU
•CFR 47 FCC part 15

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2. Reference Design
The reference design package includes the following information for each module
variant:
•Reference manual: JN-RM-2079
•Schematics
•Layout
•Bill-of-Materials
Full design databases including schematics and layout source files are available on
request.
The following table provides a summary of the QN9090 Module Reference Design that is
available from the Wireless Connectivity area of the NXP web site.
Table 1. Modules references
Part number
Description
Content
Reference
Manual
JN-RD-6058
QN9090
Module
Reference
Design
Package
OM15069
Standard Power
PCB Antenna
QN9090-001-M10
JN-RM-2079
OM15069
Standard Power
Fl connector
QN9090-001-M13
Note: These reference designs are approved for the operating temperature range of
−40 ºC to +125 ºC.

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3. Block diagram
Fig 1. QN9090-001-M10 & M13 block diagrams
4. Design considerations
To have successful wireless hardware development, the proper device footprint, RF
layout, circuit matching, antenna design, and RF measurement capability are essential.
RF circuit design, layout, and antenna design are specialties requiring investment in tools
and experience. With available hardware reference designs from NXP, RF design
considerations, and the guidelines contained in this application note, hardware engineers
can successfully design BLE radio boards with good performance levels. The following
figures show the QN9090 M10 & M13 reference modules. They contain the QN9090
device and all necessary I/O connections.
QN9090
Matching
µ
Fl
connector
QN9090-001-M10
QN9090
Matching
Printed
antenna
QN9090-001-M13

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Fig 2. QN9090-001-M10 & M13
The device footprint and layout are critical as the RF performance is affected by the
design implementation. For these reasons, use of the NXP recommended RF hardware
reference designs are important for successful board performance. Additionally, the
reference platforms have been optimized for radio performance. Even small changes in
the location of components can mistune the circuit. If the recommended footprint and
design are followed exactly in the RF region of the board, sensitivity, output power,
harmonic and spurious radiation, and range will have a high likelihood of first-time
success.
The following subsections describe important considerations when implementing a
wireless hardware design starting with the device footprint, PCB stack-up, RF circuit
implementation, and antenna selection. The following figure shows an example of a
typical layout with the critical RF section which must be copied exactly for optimal radio
performance. The less critical layout area can be modified without reducing radio
performance.
NOTE:
Exact dimensions are not given in this document, but can be found in the manufacturing
files for the QN9090 modules
4.1 QN9090 device footprint
The performance of the wireless link is largely influenced by the device’s footprint. As a
result, a great deal of care has been put into creating a footprint so that receiver
sensitivity and output power are optimized to enable board matching and minimal
component count. NXP highly recommends copying the die flag exactly as it is shown in

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the following figure; this includes via locations as well. Deviation from these parameters
can cause performance degradation.
Fig 3. Critical Layout of die flag area
Fig 3 shows the critical areas of the device die flag. These are the following:
•Ground vias and locations
•RF output and ground traces
•Die flag shape
4.2 PCB Stack-Up
Complexity is the main factor that will determine whether the design of an application
board can be two-layer, four-layer, or more. From an RF point of view a 4 layers PCB
is preferred to a two layers PCB. Nevertheless, in a very simple application it should
be possible to use a 2 layers PCB.
The recommended board stack-up for either a four-layer or two-layer board design is
as follows:
•4-layer stack-up:
—Top: RF routing of transmission lines
—L2: RF reference ground
—L3: DC power
—Bottom: signal routing
•Two-layer stack-up:
—Top: RF routing of transmission lines, signals, and ground
—Bottom: RF reference ground, signal routing, and general ground
RFIO
GND vias
Die flag

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The QN9090-001-M10 and QN9090-001-M13 (OM15069) modules are built on a
standard 4–layer printed circuit board (PCB) with the individual layers organized as
shown in Fig 4.
Fig 4. PCB stack-up
Note: The NXP PCB layouts assume use of the layers defined above. If a different PCB
stack-up is used, then NXP does not guarantee performance.
NXP strongly recommends the use of the above stack-up.
As shown in Fig 4, regarding transmission lines, it is important to copy not just the
physical layout ofthe circuit, but also the PCB stack-up. Any small change in the
thickness of the dielectric substrate under the transmission line will have a significant
change in impedance; all this information can be found on the fabrication notes for
each board design. As an illustration, consider a 50-ohm microstriptrace that is 18-mils
wide over 10 mils of FR4. If that thickness of FR4 is changed from 10 to 6 mils, the
impedance will only be about 36 ohms.
In any case the width of the RF lines must be re-calculated according to the PCB
characteristics in order to ensure a 50-ohm characteristic impedance.
When the top layer dielectric becomes too thin, the layers will not act as a true
transmission line, even though all the dimensions are correct. There is not universal
industry agreement on which thickness at which this occurs, but NXP prefers to use a
top layer dielectric thickness of no less than 8-10 mils.
There is also a limit to the ability of PCB fabricators to control the minimum width of a
PCB trace and the minimum thickness of a dielectric layer. +/- 1 mil will have less
impact onan 18-mils wide trace and a 10-mil thick dielectric layer, than it will on a much
narrower trace and thinner top layer.
This can be an especially insidious problem. The design will appear to be optimized
with the limited quantityofprototypeandinitialproductionboards,inwhichthebare
PCB'swereallfabricatedinthesame lot.However,whenthe productgoesintomass

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productiontherecanbevariations in PCBfabricationfrom lot-to-lot which can degrade
performance.
The use of a correct substrate like the FR4 with a dielectric constant of 4.4 will assist you
in achieving a good RF design.
While no special measures are required for the board design, it is recommended that
Class 1 tolerances be used.
4.3 RF circuit topology and matching
NXP always recommends that designers start by copying the existing NXP reference
design. This applies to both the circuit portion (schematic) of the design, and the PCB
layout. For all RF designs, particularlyfor designs at frequencies as high as 2.4 GHz, the
PCB traces are a part of the design itself. Even a very short trace has a small amount of
parasitic impedance (usually inductive), which has to be compensated for in the
remainder of the circuit.
What may seem like a minor change to the layout, or what would certainly be a minor
change at a lower frequencyof operation,canactually bea significantchange at 2.4 GHz.
For example, we may consider that a metal trace on a PCB such as the QN9090-001M1x
modules is approximately 0.8 nH per mm. At lower frequencies, this would have no
impact, but at 2.4 GHz this would have a significant impact in any matching circuits.
The circuits used on the NXP reference designs are all tuned and optimized on the
actual layout of the reference design, such that the final component values take into
account the effects of the circuit board traces,andother parasiticeffectsintroducedby
thePCB.Thisincludessuchissuesasparasiticcapacitance between components,
traces, and/or board copper layers, inductance of traces and ground vias, the non-ideal
effects of components, and nearby physical objects.
The layout of the RF portions of QN9090 based modules is critical. It is important that the
reference designs are strictly adhered to, otherwise the following may occur:
•Reduction in RF output
•Excessive spurious RF outputs leading to RF compliance issues
•Unacceptable power slope across the full channel range
•Poor range
•Reduced Rx sensitivity
4.4 Transmission lines
Transmission lines have several shapes such as microstrip, coplanar waveguide,
and strip-line. For BLE applications built on FR4 substrates, the types of
transmission lines typically take the form of microstrip or coplanar waveguide
(CPW). These two structures are defined by the dielectric constant of the board
material, trace width, and the board thickness between the trace and the ground.

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Additionally, for CPW, the transmission line is defined by the gap between the trace
and the top edge ground plane. These parameters are used to define the
characteristic impedance of the transmission line (trace) that is used to convey the
RF energy between the radio and the antenna.
QN9090 has a single ended RF output with a 3-component matching network
composed of a shunt capacitor, a series inductor then another shunt capacitor. In
addition, a 0-ohm resistor has been placed between the RFIO port of the chip and
the first shunt capacitor. These elements transform the device impedance to 50
ohms. The value of these components may vary depending on your specific board
layout. The recommended RF matching network is shown in Fig 5.
Avoid routing traces near or parallel to RF transmission lines or crystal signals.
Maintaining a continuous ground under an RF trace is critical to maintaining the
characteristic impedance of that trace. Avoid any routing on the ground layer that
will result in disrupting the ground under the RF traces.
Keep the RF trace as short as possible.
Fig 5. RF Matching Network
4.5 Components
All electronic components have parasitic characteristics that cause the part to act in a
non-ideal way. Typically, these effects become worse as the frequency of operation is
increased.
Controlled impedance trace
(50 ohm microstrip)
RF Match
Printed antennaµFl connector

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For most component suppliers, this quality is expressed by the Self Resonant
Frequency (SRF) specification. For example, a capacitor has parasitic inductance
introduced by the metal leads of the components. As frequency increases, at some
point the impedance due to the parasitic inductance is greater than the impedance of
the capacitor, and at that frequency and higher, the component no longer acts as a
capacitor and now acts as an inductor. At the point at which the impedance from both
inductive and capacitive components is the same, the part will resonate as a LC
parallel resonant circuit, and this is called the Self Resonant frequency. Fig 6 shows
some typical response curve.
Fig 6. RF Plots for 3pF ceramic capacitor Murata GRM1555 type
The same is true of inductors. There is parasitic capacitance in an inductor, mainly due
to capacitive coupling between the turns of wire. At some point in frequency, this
capacitance will have a higher impedance than the inductance of the part. From this
frequency and higher the part acts as a capacitor and not as an inductor.
The Bill of Materials (BOM) is available for all NXP reference designs. The BOM
shows the specific vendors and part numbers used on NXP designs. It is certainly
possible to substitute another vendor's parts, but it may impact the performance of the
circuit, therefore, it may be necessary to use different component values when parts
from another vendor are used.
If there is a performance issue on a new design, and part substitutions were made on
that design, then it is strongly recommended that components identical to those used
in the NXP reference design be placed on the new design for test purposes. Once the
design is working properly with components that are identical to those used by NXP,
then it will be possible to substitute components from other vendors one at a time, and
test for any impact on circuit performance.

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4.6 GND planes
It is recommended to use a solid (continuous) ground plane on Layer 2, assuming Layer
1 (top) is used for the RF components and transmission lines; avoid cut-outs or slots in
that area.
Keep top ground continuous as possible. This also applies for the other layers.
Connect ground on the components layer to the ground plane beneath with a large
quantity of vias.
Ground pours or fingers can act as antennas that unintentionally radiate. To avoid this,
eliminate any finger that is not connected to the ground reference with a via; put a via in
any trace that doesn’t go anywhere.
4.7 Layers interconnections
Avoid vias in the RF traces. Typically for a 1.6mm thickness PCB material, a single via
can add 1.2nH of inductance and 0.5pF of capacitance, depending upon the via
dimensions and PCB dielectric material.
Provide multiple vias for high current and/or low impedance traces.
Connect carefully all the ground areas of any layer to the reference GND plane
4.8 DCDC components
Be sure that the smallest values capacitors C12 and C10 are placed close to the VBAT
pin.
The impedance of the GND connection between C10/C12 and C19 must be as low as
possible: connect them directly on the component layer (see the red path below)
The R2 footprint on DCDC reference design can be removed if there is constraint on the
layout space as long as the DCDC is used as depicted in the current QN9090 datasheet.

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Fig 7. GND path between C10/C12 and C19
4.9 Reference Oscillator
The NXP QN9090 device contains the necessary on-chip components to build a 32-MHz
reference oscillator with the addition of an external crystal resonator. There is no need to
use external capacitors because the QN9090 includes a bank of switchable capacitors
that can be tuned to adjust the load capacitance (CL) that needs to be seen by the XTAL.
The reference crystal serves many purposes, including the provision of a reference for
the 32-bit ARM processor, PHY controller, radio synthesizer and analogue peripherals. In
addition, the crystal provides timing references for external I/O (e.g. on-chip UARTs) and
timer counters. Thus, it is important that the crystal reference is specified and built
correctly to ensure that the system functions properly.
The choice of crystal resonator is important for the following reasons:
Resonator tolerance: A number of parameters, ranging from on-chip timings to
radio centre-frequency, are derived directly from the tolerance of the crystal. As
indicated in the component list, we recommend that a total tolerance of less than
±25 ppm is used, as the maximum permissible offset specified in BLE 5
specification is ±50 ppm. Also, note that this tolerance should include both
temperature and ageing effects imparted on the resonator.
Resonator load capacitance: The active oscillator components on the QN9090
devices are designed for a crystal resonator with load capacitance (CL) of 6 pF.
This is a standard load and resonators of this type are widely available.
Lay-out recommendations:
Route the connections from the 32 MHz XTAL to the chip oscillator pins with traces as
short as possible. The layout of the oscillator circuit is such that tracks between
components are as short as possible. This improves the performance of the oscillator by
reducing stray capacitance which can introduce frequency errors.
C10 C12
C 19

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The XTAL should be placed away from high frequency devices and traces in order to
reduce the capacitive coupling between XTAL pins and PCB traces.
Keep other digital signal lines, especially clock lines and frequently switching signal lines,
as far away from the crystal connections as possible.
Caution: Adherence to NXP’s recommendations will ensure that the module performs
correctly. The substitution of components is not recommended, as this may lead to both
oscillator start-up and frequency tolerance issues.
4.10 Decoupling
4.10.1 General considerations
Decouple the power supplies or regulated voltages as close as possible to the supply pin
of the IC. The decoupling capacitors must be connected to a localized ground pad on the
top layer that is connected to the main ground plane layer through multiple vias.
Ensure that each decoupling capacitor has its own via connection to ground. When
possible use 2 vias to connect the capacitor to the ground layer.
Fig 8. GND vias placement
The capacitor with a smaller capacitance must be placed nearer to the IC.
The decoupling capacitor must be placed between the main supply line and the supply
pin as shown below:
Best configuration
Wrong configuration:
•There are not enough vias
•The vias are too far from the
decoupling capacitors

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Fig 9. Decoupling capacitors placement
4.10.2 VDD(RADIO), FB, VDD_PMU, VDDE and VBAT decoupling
Copy as much as possible the placement of the decoupling capacitors of all the supply
pins as shown below.
Fig 10. VDD(Radio) decoupling
Fig 11. FB and VDD_PMU decoupling
VDD
Main supply
trace on layer 3
VDD
Gnd
Gnd
Main supply trace
on layer 3
cap
best configuration
via via via
via
Wrong configuration:
The decoupling capacitor is not
placed between the main line and
the VDD pin
C13
C14
VDD(Radio)

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Fig 12. VDDE decoupling
Fig 13. VBAT decoupling
4.11 Traces Isolation
When PCB traces are in close proximity, they can talk to each other through the
capacitor created by these traces.
In order to minimize the effect of this parasitic coupling, identify the most sensitive traces
or areas (RF trace, oscillator, power lines, ...) and separate them from any signal that is
likely to couple with them through parasitics.
Separation between 2 lines can be achieved by increasing the distance from one to the
other.
4.12 GPIOs
The GPIOs traces are generally long lines that can cover long distances. They can
carry undesirable signals that are likely to radiate in any direction. It is recommended to
avoid routing these signals
C100
VDDE
C10
C12
C 1

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4.13 Screening can
The QN9090 doesn’t radiate high spurs and it is very robust to EMC interferers so there
is in principle no need for a screening can (or shielding can). Nevertheless, a footprint for
a can has been added on the NXP modules and NXP recommends adding this footprint
to any PCB. In very specific cases under a very noisy environment it could be helpful to
add a can.
5. Optimal PCB placement of a module
Where the QN9090 is mounted on a module similar to the NXP QN9090-001-M10 care must be
taken when mounting this module onto another PCB.
The area around the antenna must be kept clear of conductors or other metal objects for an
absolute minimum of 20 mm. This is true for all layers of the PCB and not just the top layer. Any
conductive objects close to the antenna could severely disrupt the antenna pattern resulting in
deep nulls and high directivity in some directions.
The diagrams below show various possible scenarios. The top 3 scenarios are correct; ground
plane may be placed beneath QN9090-001-M00 module as long as it does not protrude beyond
the edge of the top layer ground plane on the module PCB.
The bottom 3 scenarios are incorrect; the left-hand side example because there is ground plane
underneath the antenna, the middle example because there is insufficient clearance around the
antenna (it is best to have no conductors anywhere near the antenna), finally the right hand
example has a battery’s metal casing in the recommended keep out area.

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Fig 14. PCB placement of a QN9090 module with a printed antenna
6. Manufacturing considerations
The HVQFN package must be considered carefully when using reflow solder techniques.
Package footprint information can be found in the QN9090 data sheet.
The decal is shown in Fig 15. The pad stacks used are 0.25 mm by 1 mm for the smaller
pads, and a 6.4 mm square pad for the paddle.

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Warning: Solder resist area recommended
Fig 15. Recommended PCB decal for HVQFN40 40-pin QFN
The solder mask used is shown in Fig 17. The pad stacks used are 0.25 mm by 1 mm
for the smaller pads, and four 1.6 mm square pads to apply paste to the paddle. The
solder paste mask has a thickness of 6-thou (0.152 mm). If the paste thickness needs
to deviate from that used NXP then it may be necessary to change the number of pads
that the paste is applied to. Paste thickness may be dictated by additional components
used in a design.
NOTE –Solder resist area:
A specific connection used on NXP production line has to be handled carefully when
the layout is done (see nest figure)
Extra connection Forbidden routing
Fig 16. Extra test pin

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Fig 17. Solder paste mask for HVQFN40 40-pin QFN
Fig 18. Vias on the paddle of the HVQFN40 40-pin QFN
25 vias are applied to the paddle. These allow excess solder paste and heated air to be
vented away from the device, preventing the device from being lifted during soldering.
In addition, these vias ensure that a low impedance ground is maintained, which is vital
for optimum RF performance.