NXP Semiconductors i.MX8 QM Instruction Manual

i.MX8 QM / i.MX8 QXP Hardware Developer’s
Guide
NXP Semiconductors Document identifier: IMX8HWDG
User's Guide Rev. 2.4p, 06/2021

Contents
Chapter 1 Overview............................................................................................... 3
Chapter 2 i.MX8 QM and QXP design checklist.................................................... 7
Chapter 3 i.MX8 layout/routing recommendations...............................................19
Chapter 4 Thermal considerations.......................................................................75
Chapter 5 Avoiding board bring-up problems...................................................... 81
Chapter 6 Using BSDL for board-level testing..................................................... 86
Chapter 7 Revision history...................................................................................87
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Chapter 1
Overview
This document’s purpose is to help hardware engineers design and test their i.MX 8 series processor-based designs. It
provides information on board layout recommendations, design checklists to ensure first-pass success and ways to avoid board
bring-up problems.
Engineers are expected to have a working understanding of board layouts and common board hardware terminology.
This guide is released along with relevant device-specific hardware documentation such as datasheets, reference manuals, and
application notes available at nxp.com.
1.1 Devices supported
This Hardware Developer’s Guide currently supports the i.MX8 QM (29 x 29 mm package) and i.MX8 QXP (21 x 21 and 17 x 17
mm packages) processors.
1.2 Essential reference
This guide is intended as a companion to the i.MX 8 series chip reference manuals and data sheets. For the reflow profile and
thermal limits during soldering, see General Soldering Temperature Process Guidelines (document AN3300). These documents
are available at nxp.com.
1.3 Suggested reading
This section lists additional reading that provides background for the information in this manual as well as general information
about the architecture.
1.3.1 General information
The following documentation provides useful information about the Arm® processor architecture and computer architecture
in general.
• For information about the Arm Cortex®-A35 processor, see: https://www.arm.com/products/processors/cortex-a/cortex-
a35-processor.php
• For information about the Arm Cortex-A53 processor, see: https://www.arm.com/products/processors/cortex-a/cortex-a53-
processor.php
• For information about the Arm Cortex-A72 processor, see: https://www.arm.com/products/processors/cortex-a/cortex-a72-
processor.php
• For information about the Arm Cortex-M4F processor, see: https://www.arm.com/products/processors/cortex-m/cortex-m4-
processor.php
•Computer Architecture: A Quantitative Approach (Fourth Edition) - by John L. Hennessy and David A. Patterson
•Computer Organization and Design: The Hardware/Software Interface (Second Edition), by David A. Patterson and John
L. Hennessy
The following documentation provides useful information about high-speed board design:
•Right the First Time- A Practical Handbook on High Speed PCB and System Design - Volumes I & II - Lee W. Ritchey
(Speeding Edge) - ISBN 0-9741936- 0-72
•Signal and Power Integrity Simplified (Second Edition) - Eric Bogatin (Prentice Hall)- ISBN 0-13-703502-0
•High Speed Digital Design- A Handbook of Black Magic - Howard W. Johnson & Martin Graham (Prentice Hall) - ISBN
0-13-395724-1
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•High Speed Signal Propagation- Advanced Black Magic - Howard W. Johnson & Martin Graham - (Prentice Hall) - ISBN
0-13-084408-X
•High Speed Digital System Design- A handbook of Interconnect Theory and Practice - Hall, Hall and McCall (Wiley
Interscience 2000) - ISBN 0-36090-2
•Signal Integrity Issues and Printed Circuit Design - Doug Brooks (Prentice Hall) ISBN 0-13-141884-X
•PCB Design for Real-World EMI Control - Bruce R. Archambeault (Kluwer Academic Publishers Group) - ISBN
1-4020-7130-2
•Digital Design for Interference Specifications - A Practical Handbook for EMI Suppression -David L. Terrell & R. Kenneth
Keenan (Newnes Publishing) - ISBN 0-7506-7282-X
•Electromagnetic Compatibility Engineering- Henry Ott (First Edition - John Wiley and Sons) - ISBN 0-471-85068-3
•Introduction to Electromagnetic Compatibility - Clayton R. Paul (John Wiley and Sons) - ISBN 978-0-470-18930-6
•Grounding & Shielding Techniques - Ralph Morrison (Fifth Edition - John Wiley & Sons) - ISBN 0-471-24518-6
•EMC for Product Engineers - Tim Williams (Newnes Publishing) - ISBN 0-7506- 2466-3
1.4 Related documentation
NXP documentation is available from the sources listed on the back page of this guide.
Additional literature is published as new NXP products become available. For a current list of documentation, see nxp.com.
1.5 Conventions
This document uses the following notational conventions:
Courier Used to indicate commands, command parameters, code examples, and file and directory names.
Italics Italics indicates command or function parameters.
Bold Function names are written in bold.
cleared/set When a bit takes the value of zero, it is said to be cleared; when it takes a value of one, it is said to be set.
mnemonics Instruction mnemonics are shown in lowercase bold. book titles in text are set in italics.
sig_name Internal signals are written in all lowercase.
nnnn nnnnh Denotes a hexadecimal number.
0b Denotes a binary number.
rA, rB Instruction syntax used to identify a source GPR.
rD Instruction syntax used to identify a destination GPR.
REG[FIELD] Abbreviations for registers are shown in uppercase text. Specific bits, fields, or ranges appear in brackets. For
example, MSR[LE] refers to the little-endian mode enable bit in the machine state register.
x In some contexts, such as signal encodings, an unitalicized “x” indicates a do not care.
x An italicized “ x ” indicates an alphanumeric variable.
n, m An italicized “ n ” indicates a numeric variable.
In this guide, notations for all logical, bit-wise, arithmetic, comparison, and assignment operations follow C Language conventions.
1.6 Acronyms and abbreviations
Table 1 defines the acronyms and abbreviations used in this document.
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Table 1. Definitions and acronyms
Acronym Definition
ARM Advanced RISC Machines processor architecture
BGA Ball Grid Array package
BOM Bill Of Materials
BSDL Boundary Scan Description Language
CAN Flexible Controller Area Network peripheral
CCM Clock Controller Module
CSI MIPI Camera Serial Interface
DDR Dual Data Rate DRAM
DDR3L Low-voltage DDR3 DRAM
DDRC DDR Controller
DFP Downstream Facing Port (USB Type-C)
DRP Dual Role Port (USB Type-C)
ECSPI Enhanced Configurable SPI peripheral
EIM External Interface Module
ENET 10/100/1000 Mbps Ethernet MAC peripheral
EPIT Enhanced Periodic Interrupt Timer peripheral
ESR Equivalent Series Resistance
GND Ground
GPC General Power Controller
GPIO General-Purpose Input/Output
HDCP High-bandwidth Digital Content Protection
I2C Inter-integrated Circuit interface
IBIS Input output Buffer Information Specification
IOMUX i.MX8 chip-level I/O Multiplexing
JTAG Joint Test Action Group
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Table 1. Definitions and acronyms (continued)
Acronym Definition
KPP Keypad Port Peripheral
LDB LVDS Display Bridge
LDO Low Drop-Out regulator
LPCG Low-Power Clock Gating
LPDDR4 Low-Power DDR4 DRAM
LVDS Low-Voltage Differential Signaling
MLB Media Local Bus
ODT On-Die Termination
OTP One-Time Programmable
PCB Printed Circuit Board
PCIe PCI Express
PCISig Peripheral Component Interconnect Special interest group
PDN Power Distribution Network
PMIC Power Management Integrated Circuit
POR Power-On Reset
PTH Plated Through Hole PCB (no microvias)
RGMII Reduced Gigabit Media Independent Interface (Ethernet)
RMII Reduced Media Independent Interface (Ethernet)
ROM Read-Only Memory
UFP Upstream Facing Port (USB Type-C)
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Chapter 2
i.MX8 QM and QXP design checklist
This document provides a design checklist for the i.MX8 QM (29 x 29 mm package) and i.MX8 QXP (21 x 21 mm package)
processors. The design checklist tables contain recommendations for optimal design. Where appropriate, the checklist tables
also provide an explanation of the recommendation so that users have a greater understanding of why certain techniques are
recommended. All supplemental tables referenced by the checklist appear in sections following the design checklist tables.
2.1 Design checklist tables
Table 2. LPDDR4 recommendations (i.MX8 QM)
Checkbox Recommendation Explanation/Supplemental Recommendation
1. Connect the DDR_CHn_ZQ balls on the
processor (balls AF44 and AF10) to individual 240
Ω, 1 % resistors to GND.
This is a reference used during DRAM output buffer
driver calibration.
2. The ZQ0 and ZQ1 balls on each LPDDR4
device should be connected through 240 Ω, 1 %
resistors to the LPDDR4 VDD2 rail.
3. Place a 10 kΩ, 5 % resistor to the ground on
the DRAM reset signal.
This ensures adherence to the JEDEC specification until
the control is configured and starts driving the DDR.
4. The DDR_CHn_VREF balls on the processor
(balls U43 and U11) should be left unconnected.
The reference voltage generator is on the chip, so no
external source is required.
5. The QM balls DDR_CHn_DCF09 and
DDR_CHx_DCF25 should be left unconnected.
The ODT_CA balls on the LPDDR4 device should
be connected directly to the LPDDR4 VDD2 rail.
DDR_CH(0:1)_DCF09 = T52, T2 DDR_CH(0:1)_DCF25
= AF52, AF2 LPDDR4 ODT on the i.MX8 QM is
command-based, making the processor ODT_CA output
balls unnecessary.
6. The architecture for each chip inside the DRAM
package must be x16.
The processor does not support the byte mode specified
in JESD209-4C.
7. The processor balls DDR_CHn_ATO (balls
AF46/AF8), DDR_CHn_DTO0 (balls U45/U9), and
DDR_CHn_DTO1 (balls T44/T10) should be left
unconnected.
These are observability ports for manufacturing and they
are not used otherwise.
Table 3. LPDDR4 recommendations (i.MX8 QXP)
Checkbox Recommendation Explanation/Supplemental Recommendation
1. Connect the DDR_ZQ ball on the processor (ball
G9) to an external 240 Ω, 1 % resistor to GND.
This is a reference used during DRAM output buffer
driver calibration.
2. Connect the ZQ0/ZQ1 balls on the LPDDR4
device through 240 Ω, 1 % resistors to the VDD2
supply of the LPDDR4 device.
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Table 3. LPDDR4 recommendations (i.MX8 QXP) (continued)
Checkbox Recommendation Explanation/Supplemental Recommendation
3. Place a 10 kΩ, 5 % resistor to the ground on the
DRAM reset signal.
This ensures the adherence to the JEDEC specification
until the control is configured and starts driving the DDR.
4. The DDR_VREF ball (AD8) should be left
unconnected.
The reference voltage generator is on the chip, so no
external source is required.
5. The QXP device balls DDR_DCF09 and
DDR_DCF25 should be left unconnected. The
ODT_CA balls on the LPDDR4 device should be
connected directly to the LPDDR4 VDD2 rail.
DDR_DCF09 = ball AB6, DDR_DCF25 = ball K8
The LPDDR4 ODT on the i.MX8 QXP is command-
based, making the processor ODT_CA output
balls unnecessary.
6. The architecture for each chip inside the DRAM
package must be x16.
The processor does not support the byte mode specified
in JESD209-4C.
7. The processor balls DDR_ATO (ball AB8) and
DDR_DTO0:1 (balls AC7, AE7) should be left
unconnected.
These are observability ports for manufacturing and they
are not used otherwise.
Table 4. I2C recommendations
Checkbox Recommendation Explanation/Supplemental Recommendation
1. Verify the target I2C interface clock rates. The I2C bus can only be operated as fast as the slowest
peripheral on the bus. If faster operation is required, move the
slow devices to another I2C port.
2. Verify that there are no I2C address conflicts
on any of the I2C buses utilized.
There are multiple I2C ports available on the chip, so if
a conflict exists, move one of the conflicting devices to a
different I2C bus. If this is not possible, use a I2C bus switch
(NXP part number PCA9646).
3. Do not place more than one set of pull-up
resistors on the I2C lines.
This could result in excessive loading and potential incorrect
operation. Choose the pull-up value commensurate with the
bus speed being utilized.
4. Ensure that the VCC rail powering the i.MX8
I2C interface balls matches the supply voltage
used for the pull-up resistors and the slave I2C
devices.
Prevent device damage or incorrect operation due to
voltage mismatch.
Table 5. Debug recommendations – JTAG and UART
Checkbox Recommendation Explanation/Supplemental Recommendation
1. Do not use external pull-up or pull-down
resistors on JTAG_TDO.
JTAG_TDO is configured with an on-chip keeper circuit such
that the floating condition is actively eliminated if an external
pull resistor is not present.
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Table 5. Debug recommendations – JTAG and UART (continued)
Checkbox Recommendation Explanation/Supplemental Recommendation
2. Follow the recommendations for external pull-
up and pull-down resistors given in Table 15.
3. TEST_MODE_SELECT (ball BC49 on the
QM and ball AE29 on the QXP) should be
connected to the ground.
This ball is for factory use only.
Table 6. Reset and on/off recommendations
Checkbox Recommendation Explanation/Supplemental Recommendation
1. The POR_B input must be asserted at
powerup and remain asserted until the last
power rail for the devices required for system
boot is at its working voltage. This functionality
is controlled by the PMIC (PF8100, PF8200 or
PF7100).
A reset switch may be wired to the chip’s POR_B, which
is a cold-reset negative-logic input that resets all modules
and logic in the IC. POR_B may be used in addition to
internally generated power-on reset signal (logical AND,
both internal and external signals are considered active
low). While POR_B is asserted (low) on the i.MX8, output
PMIC_ON_REQ remains asserted (high).
2. For portable applications, the
ON_OFF_BUTTON input may be connected to
an ON/OFF SPST push-button switch to the
ground. On-chip debouncing is provided, and
this input has an on-chip pullup. If not used,
ON_OFF_BUTTON should be a no-connect.
A brief connection (0.5 sec < press < 4 sec) to GND in the OFF
mode causes the internal power management state machine
to change the state to ON. In the ON mode, a brief connection
to the GND generates an interrupt (intended to initiate
a software-controllable power-down). An approximately 5-
second (or more) connection to GND causes a forced OFF.
3. If PMIC_ON_REQ is not used, the pin
should be left unconnected. -
Table 7. i.MX8 QM power/decoupling recommendations
Checkbox Recommendation Explanation/Supplemental Recommendation
1. Comply with the power-up sequence guidelines,
as described in the datasheet to guarantee reliable
operation of the device.
Any deviation from these sequences may result in the
following situations:
• Excessive current during the power-up phase.
• Prevention of the device from booting.
• Irreversible damage to the processor (worst case
scenario).
2. Maximum ripple voltage requirements. A common requirement for the ripple noise should
be less than 5 % peak-to-peak of the supply voltage
nominal value.
3. The internal LDOs shown below should be
decoupled with individual pairs of 2.2 µF caps:
• VDD_HDMI_TX0_LDO_1P0_CAP
Place at least one capacitor underneath the BGA
package as close as possible to each LDO output
(desired trace length < 50 mils). The HDMI RX LDO
outputs should only be connected to the caps, while the
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Table 7. i.MX8 QM power/decoupling recommendations (continued)
Checkbox Recommendation Explanation/Supplemental Recommendation
• VDD_HDMI_RX0_LDO0_1P0_CAP
• VDD_HDMI_RX0_LDO1_1P0_CAP
• VDD_PCIE_LDO_1P0_CAP
others should be connected to the i.MX8 QM balls, as
shown below:
• VDD_HDMI_TX0_LDO_1P0_CAP
1. VDD_HDMI_TX0_1P0
• VDD_PCIE_LDO_1P0_CAP
1. VDD_PCIE0_1P0
2. VDD_PCIE1_1P0
3. VDD_PCIE_SATA0_1P0
4. The VDD_USB_SS3_LDO_1P0_CAP internal
LDO should be decoupled with three 2.2 µF caps.
Place two capacitors underneath the BGA package as
close as possible to the LDO output (desired trace length
< 50 mils). The other cap should be placed on the back
side as close as possible to the other two capacitors.
This LDO output should only drive:
1. VDD_USB_OTG1_1P0
2. VDD_USB_OTG2_1P0
Table 8. i.MX8 QXP power/decoupling recommendations
Checkbox Recommendation Explanation/Supplemental Recommendation
1. Comply with the power-up sequence
guidelines, as described in the datasheet to
guarantee reliable operation of the device.
Any deviation from these sequences may result in the
following situations:
• Excessive current during the power-up phase.
• Prevention of the device from booting.
• Irreversible damage to the processor (worst case
scenario).
2. Maximum ripple voltage requirements. A common requirement for the ripple noise should be less
than 5 % peak-to-peak of the supply voltage nominal value.
3. The VDD_PCIE_LDO_1P0_CAP internal
LDO should be decoupled with a 2.2 µF cap
and a 0.22 µF cap.
Place the 0.22 μF capacitor underneath the BGA package as
close as possible to the LDO output (desired trace length <
50 mils).
4. The VDD_USB_SS3_LDO_1P0_CAP
internal LDO should be decoupled with a 2.2
µF cap and two 0.22 µF caps.
Place the 0.22 μF capacitors underneath the BGA
package as close as possible to the LDO output (desired
trace length < 50 mils). This LDO output should only
drive VDD_USB_OTG1_1P0.
See the i.MX8QM LPDDR4 MEK layout for the recommended capacitor placement.
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Table 9. Capacitor recommendations to be placed near i.MX8 QM2
Checkbox Supply 1 µF 2.2
µF 22 µF 100 µF Notes
VDD_DDR_CH0_VDDQ
VDD_DDR_CH0_VDDQ_CKE 6 2 --- 2.2 µF caps should be placed under the BGA package.
VDD_DDR_CH0_VDDA_PLL_1P8 2
This rail should be sourced from the
main 1.8 V rail through a 120 Ω
ferrite bead.
VDD_DDR_CH1_VDDQ
VDD_DDR_CH1_VDDQ_CKE 6 2 --- 2.2 µF caps should be placed under the BGA package.
VDD_DDR_CH1_VDDA_PLL_1P8 2
This rail should be sourced from the
main 1.8 V rail through a 120 Ω
ferrite bead.
VDD_A53 5 --- 2 2.2 µF caps should be placed under
the BGA package.
VDD_A72 5 --- 3 2.2 µF caps should be placed under
the BGA package.
VDD_GPU0 6 --- 32.2 µF caps should be placed under
the BGA package.
VDD_GPU1 6 --- 32.2 µF caps should be placed under
the BGA package.
VDD_MEMC 6 --- 3 2.2 µF caps should be placed under
the BGA package.
VDD_MAIN 13 --- 2 2.2 µF caps should be placed under
the BGA package.
VDD_LVDS0_1P0 VDD_LVDS1_1P0
VDD_MIPI_CSI0_1P0
VDD_MIPI_CSI1_1P0
VDD_MIPI_DSI0_1P0
VDD_MIPI_DSI1_1P0
VDD_MIPI_DSI0_PLL_1P0
VDD_MIPI_DSI1_PLL_1P0
5 1 --- These 8 balls are tied to the
VDD_MAIN supply and filtered as
shown (see the development platform
schematic and section 7.11).
VDD_SCU_XTAL _1P8 --- --- --- --- Place a 0.22 µF cap under the
BGA package.
VDD_ANAn_1P8 VDD_SCU_1P8_n
VDD_SCU_ANA_1P8
VDD_CP_1P8
6 --- --- 2.2 µF caps should be placed under
the BGA package.
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Table 9. Capacitor recommendations to be placed near i.MX8 QM2 (continued)
Checkbox Supply 1 µF 2.2
µF 22 µF 100 µF Notes
VDD_M1P8_CAP --- 1 --- --- Placed under the BGA package.
VREFH_ADC VDD_ANA0_1P8_n
VDD_ADC_1P8
VDD_MIPI_CSIn_1P8
VDD_MIPI_DSIn_1P8
VDD_LVDSn_1P8 VDD_MLB_1P8
(Note 4)
VDD_PCIEn_PLL_1P8
VDD_PCIE_SATA0_PLL_1P8
VDD_PCIE_IOB_1P8
VDD_PCIE_LDO_1P8
VDD_USB_HSIC0_1P8
VDD_HDMI_RX0_1P8
VDD_HDMI_TX0_1P8
8--- 2 These 19 balls are tied to the
1.8 V SMPS supply through dual
120 Ω ferrite beads and filtered as
shown (see the i.MX8QM LPDDR4
MEK schematic for illustration). Place
the eight 2.2 µF caps under the
BGA package.
VDD_HDMI_TX0_1P0
VDD_HDMI_TX0_ LDO_1P0_CAP
2 --- --- Balls AW15 and AV16 of
the processor.
VDD_HDMI_RX0_LDOn_
1P0_CAP
4 --- --- Balls AU19 and AU21 of processor (2 x
2.2 µF per ball).
VDD_PCIE_LDO_1P0_CAP
VDD_PCIEn_1P0
VDD_PCIE_SATA0_1P0
2 --- --- Balls N29, M26, N25, and N24,
respectively to the processor.
VDD_USB3_SS3_LDO_
1P0_CAP VDD_USB_OTGn_1P0
3 --- --- Balls M30, M32, and N31, respectively
to the processor. Place two caps under
the BGA package.
VDD_SNVS_4P2 --- --- --- --- Ball AT38, use 0.22 µF.
VDD_SNVS_LDO_1P8_CAP --- 1 --- --- Ball AW39.
VDD_USB_HSIC0_1P2 1 --- --- Ball V26.
VDD_SIM0_1P8_3P3 1 --- --- --- Ball AK42.
VDD_USDHC1_1P8_3P3_n 1 --- --- --- Balls M36 and N37.
VDD_USDHC2_1P8_3P3_1 1 --- --- --- Ball M38.
VDD_ENET0_1P8_2P5_3P3_n 1 --- --- Balls M40 and N39.
VDD_ENET1_1P8_2P5_3P3 1 --- --- --- Ball T38.
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Table 9. Capacitor recommendations to be placed near i.MX8 QM2 (continued)
Checkbox Supply 1 µF 2.2
µF 22 µF 100 µF Notes
VDD_HDMI_RX0_VH_RX_3P3
VDD_USB_OTG1_3P3
VDD_USB_OTG2_3P3
2 1 --- ---
These three balls should be filtered
through a 120 Ω ferrite bead. Place the
two 1 µF caps under the BGA package.
VDD_ENET_MDIO_1P8_2P5_3P3 1 --- --- ---
Ball N17 (if connected to the main 1.8V
or 3.3V, this ball would fall into the
digital power group below).
VDD_EMMC0_1P8_3P3
VDD_PCIE_DIG_1P8_3P3
VDD_LVDS_DIG_1P8_3P3
VDD_MIPI_DSI_DIG_1P8_3P3
VDD_QSPI0_1P8_3P3
VDD_QSPI1A_1P8_3P3
VDD_MLB_DIG_1P8_3P3 (Note 5)
VDD_M4_GPT_UART_1P8_3P3_n
VDD_SPI_SAI_1P8_3P3_n
VDD_ESAI0_MCLK_1P8_3P3_n
VDD_ESAI1_SPDIF_SPI_1P8_3P3
VDD_FLEXCAN_1P8_3P3
VDD_USDHC_VSELECT_1P8_3P3
Digital Power, see note
These power balls can be connected
to either 1.8 V or 3.3 V, depending on
the specific design. The exact number
of caps on each rail (1.8 V or 3.3 V) will
be dependent on the number of balls
connected to that rail, but there should
be a cap for every 1-2 balls and each
ball should have a capacitor relatively
close to it.
Note 1: All capacitors in MEK use the X7S or X7R grades.
Note 2: For PMIC capacitor recommendations, see the PMIC data sheet.
Note 3: Recommended capacitor placement used in the NXP i.MX8QM MEK Customer Board.
Note 4: MLB is not supported on this product. This MLB power rail may be tied to the power supply voltage indicated or
terminated per the Hardware Developer's Guide and power supplies of unused functions.
Note 5: MLB is not supported on this product. The MLB power rail must be tied to the power supply voltage indicated if other I/O
functions are used as determined by the IOMUX selection. Alternately, terminate the MLB supply per the Hardware Developer's
Guide and power supplies of unused functions.
See the i.MX8QXP LPDDR4 MEK layout for recommended capacitor placement.
Table 10. Capacitor recommendations to be placed near i.MX8 QXP2
Checkbox Supply 0.22
µF 1 µF 2.2 µF
10
µF 22 µF Notes
VDD_DDR_VDDQ 8 2 9 --- 3
VDD_MAIN --- --- 12 6 4
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Table 10. Capacitor recommendations to be placed near i.MX8 QXP2 (continued)
Checkbox Supply 0.22
µF 1 µF 2.2 µF
10
µF 22 µF Notes
VDD_A35 3 2 7 3 4
VDD_GPU 11 3 4
VDD_MIPI_1P0 --- --- 1--- ---
These two balls (AD18 and AE19)
are connected to the VDD_MAIN
rail, so there are 13 2.2 µF caps
on VDD_MAIN.
VDD_ANA0_1P8 1 --- 1--- ---
VDD_ANA1_1P8 1 --- 1 --- --- Through LRC filter (see the
development platform schematic).
VDD_SNVS_4P2 2 --- --- --- ---
VDD_SNVS_LDO_1P8_CAP 1 --- 1 --- --- -
VDD_CAN_UART_1P8_3P3 2 --- --- --- ---
VDD_ESAI_SPDIF_1P8_2P5_3P3 2 --- --- --- ---
VDD_SPI_SAI_1P8_3P3 2 --- --- --- ---
VDD_SPI_MCLK_UART_1P8_3P3 2 --- --- --- ---
VDD_ADC_DIG_1P8 2 --- --- --- ---
VDD_ADC_1P8
ADC_VREFH
3 --- --- --- Supply through one 120 Ω
ferrite bead.
VDD_MIPI_1P8_n 2 --- 1 --- --- Supply through one 120 Ω
ferrite bead.
VDD_MIPI_DSI_DIG_1P8_3P3 2 --- --- --- ---
VDD_MIPI_CSI_DIG_1P8 2 --- --- --- ---
VDD_TMPR_CSI_1P8_3P3 1 --- --- --- ---
VDD_CSI_1P8_3P3 4--- --- --- --- Supply through one 120 Ω
ferrite bead.
VDD_DDR_PLL_1P8 1 1 --- 1 --- Supply through one 120 Ω
ferrite bead.
VDD_USDHC1_1P8_3P3 1 --- --- --- --- 2 x 0.1 uF or 1 x 0.22 uF.
VDD_USDHC1_VSELECT_1P8_3P3 2 --- --- --- ---
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Table 10. Capacitor recommendations to be placed near i.MX8 QXP2 (continued)
Checkbox Supply 0.22
µF 1 µF 2.2 µF
10
µF 22 µF Notes
VDD_EMMC0_1P8_3P3 1 --- --- --- ---
VDD_EMMC0_VSELECT_1P8_3P3 1 --- --- --- ---
VDD_QSPI0A_1P8_3P3 2 --- --- --- ---
VDD_QSPI0B_1P8_3P3 2 --- --- --- ---
VDD_ENET0_VSELECT_1P8_2P5_3P
3
1--- --- --- ---
VDD_ENET0_1P8_2P5_3P3 2 --- --- --- ---
VDD_ENET_MDIO_1P8_3P3 2 --- 1 --- ---
VDD_PCIE_1P8 2 --- 1 --- --- Supply through a 120 Ω
ferrite bead.
VDD_PCIE_LDO_1P0_CAP 1 --- 1 --- ---
VDD_PCIE_DIG_1P8_3P3 2 --- --- --- ---
VDD_USB_SS3_LDO_1P0_CAP
VDD_USB_OTG_1P0 2 --- 1 --- ---
VDD_USB_1P8 2 --- 1 --- --- Supply through one 120 Ω
ferrite bead.
VDD_USB_3P3 2 --- 1 --- ---
Note 1: All capacitors in MEK use the X7S or X7R grades.
Note 2: For PMIC capacitor recommendations, see the PMIC data sheet.
Table 11. PCIe recommendations
Checkbox Recommendation Explanation/Supplemental Recommendation
1. The reference clock source should have a HCSL
(High-Speed Current-Steering Logic) differential output.
Resistors of approximately 50 Ω are required to
terminate both traces to GND. Do not AC couple this
clock.
Note: i.MX6 processors used LVDS outputs for the PCIe
interface. The connection requirements are different for
this SOC.
The NXP development platform board design uses
a Micrel DSC557 device. However, NXP does not
recommend one supplier over another and it does
not suggest that this is the only clock generator
supplier. The particular device used should support
all specs (jitter, accuracy, and so on) The internal
PCIe reference clock is good for all standard PCIe
applications. The clock may be connected to one or
two external devices (depending on location). Use
a buffer, distributor, or external clock reference for
additional PCIe destinations.
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Table 11. PCIe recommendations (continued)
Checkbox Recommendation Explanation/Supplemental Recommendation
The internal PCIe reference clock is not
spread spectrum capable. For EMC/EMI sensitive
applications, it is recommended to use an external
reference clock source.
2. The differential transmitters from the processor must
be AC coupled. Use a 0.22 µF cap on both the
PCIE_TXP and PCIE_TXN outputs.
PCIe specification compliance requires AC
coupling at each transmitter. The receiver must
be DC coupled.
3. The PCIE_REF_QR ball should be connected to
ground through a 453 Ω, 1 % resistor.
This signal is ball E23 on the i.MX8 QM and ball F12
on the i.MX8 QXP.
4. The PCIE_REXT ball should be connected to the
PCIE0_PHY_PLL_REF_RETURN ball through an 845 Ω,
0.5 % resistor.
PCIE_REXT is ball D22 (QM) and H12 (QXP).
PCIE_PHY_PLL_REF_RETURN is ball M28 (QM)
and ball G11 (QXP).
Note: The i.MX8 processor packages route
thePCIe RX and TX data pairs (including SATA) as
85- Ω differential impedance traces. NXP
recommends routing PCB differential traces to
match.
5. PCIE_SATA0_PHY_PLL_REF_RETURN,
PCIE0_PHY_PLL_REF_RETURN, and
PCIE1_PHY_PLL_REF_RETURN should be connected
to VDD_PCIE_1V8 by 0.22 µF capacitors (8QM).
See the i.MX8QM LPDDR4 MEK for the
correct implementation.
6. PCIE0_PHY_PLL_REF_RETURN should be
connected to VDD_PCIE_1V8 by 0.22 µF and 22 µF
capacitors (8QXP).
See the i.MX8QXP LPDDR4 MEK for the
correct implementation.
Table 12. USB recommendations
Checkbox Recommendation Explanation/Supplemental Recommendation
1. To comply with the USB OTG specification, the
VBUS supply to the OTG connector should default
to off when the board powers up.
The processor should turn on VBUS if required.
2. Connect a 499 Ω, 1 % resistor to ground on the
USB_OTG2_REXT ball (ball E29 on QM and ball
D14 on QXP.
3. Connect a 499 Ω, 1 % resistor to ground on the
USB_SS3_REXT ball (ball E27 on QM, ball E13 on
QXP).
4. If using USB1 OTG, connect USB_OTG1_VBUS
(ball A39 on QM and ball H18 on QXP) to the 5 V
OTG connector VBUS.
If unused, leave VBUS unconnected.
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Table 12. USB recommendations (continued)
Checkbox Recommendation Explanation/Supplemental Recommendation
5. If using USB_OTG2, connect USB_OTG2_VBUS
via a resistive voltage divider to the VBUS pin of
the connector such that the 5.5 V VBUS voltage is
reduced to 3.3 V On QM (ball A35) and QXP (ball
H16).
On QM and QXP, the OTG1 and OTG2 interfaces are
implemented differently, and while the OTG1 VBUS ball
is 5 V tolerant, the OTG2 VBUS ball is not.
6. Route all USB differential signals with 90 Ω
differential impedance.
USB_OTG1 is not compatible with the SS interface.
7. ESD protection should be implemented at the
connector pins. Choose a low-capacitance device
recommended for high-speed interfaces.
This will prevent potential damage to board components
from ESD.
Table 13. HDMI recommendations (i.MX8 QM only)
Checkbox Recommendation Explanation/Supplemental Recommendation
1. Connect a 499 Ω, 1 % resistor to ground on
the HDMI_RX0_REXT ball (ball BJ11).
2. Connect a 499 Ω, 1 % resistor to ground on
the HDMI_TX0_REXT ball (ball BJ7).
3. Route all HDMI receive and transmit
differential pairs with 100 Ω differential
impedance.
4. To provide a Display Port output on the
i.MX8 QM Display TX output, follow the
implementation details in Figure 31.
5. To provide an HDMI output on the
i.MX8 QM Display TX output, follow the
implementation details in Figure 32.
6. The HDMI_TX0_CEC trace must be pulled
up to the VCC_3V3 rail through a 27 k Ω
resistor in series with a Schottky diode.
Table 14. Oscillator/crystal recommendations
Checkbox Recommendation Explanation/Supplemental Recommendation
1. Connect a 32.768 kHz crystal between
RTC_XTALI and RTC_XTALO.
For the ESR selection, the negative resistance/ESR and drive
level must be considered at the same time. See the processor
datasheet for the general crystal requirements. Follow the
manufacturer’s recommendation for loading capacitance.
Use short traces between the crystal and the processor
with a ground plane under the crystal, load capacitors, and
associated traces.
Internal load capacitors should be used. See Internal load
capacitor trimming (24 MHz and 32.768 kHz).
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Table 14. Oscillator/crystal recommendations (continued)
Checkbox Recommendation Explanation/Supplemental Recommendation
2. Instead of a crystal, the i.MX8 QM/QXP
32.768 kHz can be driven with an external
clock (oscillator) driven into the RTC_XTALI
input (RTC_XTALO floated).
The voltage level of this driving clock should not exceed
the voltage of the VDD_SNVS_LDO_1P8_CAP rail and the
frequency should be <100 kHz under typical conditions.
Do not exceed VDD_SNVS_LDO_1P8_CAP or damage/
malfunction may occur. The RTC_XTALI signal should not
be driven if the VDD_SNVS_CAP supply is off. This can lead
to damage or malfunction. For the RTC_XTALI VIL and VIH
voltage levels, see the latest i.MX8 QM and i.MX 8QXP data
sheet available at www.nxp.com.
3. Connect a 24.00 MHz crystal between
XTALI and XTALO.
For the ESR selection, the negative resistance/ESR and
drive level must be considered at the same time. See the
processor datasheet for the general crystal requirements.
Internal load capacitors should be used. See Internal load
capacitor trimming (24 MHz and 32.768 kHz).
4. Do not connect VSS_SCU_XTAL to
VSS_MAIN.
Follow the implementation of the associated development
platform. To further reduce the oscillator noise, the
VSS_SCU_XTAL pins can be separated from VSS_MAIN.
2.2 JTAG signal termination
Table 15 is a JTAG termination chart showing what terminations should be placed on PCB designs.
Table 15. Recommended JTAG board terminations
JTAG Signal I/O Type External Termination Comment
JTAG_TCK Input 10 kΩ pull-down
JTAG_TMS Input 10 kΩ pull-up
JTAG_TDI Input 10 kΩ pull-up
JTAG_TDO 3-state output None
JTAG_TRSTB* Input 10 kΩ pull-up No connection from the JTAG to the processor.
* Not available on i.MX8 QXP
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Chapter 3
i.MX8 layout/routing recommendations
3.1 Introduction
This chapter provides recommendations to assist design engineers with the layout of an i.MX8 QM and i.MX8 QXP-based system.
3.2 Basic design recommendations
When using the Allegro design tool, it is recommended to use the schematic symbol and PCB footprint created by NXP. When
not using the Allegro tool, use the Allegro footprint export feature (supported by many tools). If the export is not possible, create
the footprint per the package dimensions outlined in the product data sheet.
The native Allegro layout and gerber files are available on www.nxp.com.
3.2.1 Placing decoupling capacitors
Place small decoupling and larger bulk capacitors on the bottom side of the PCB.
The 0201 or 0402 decoupling and 0603 (or larger) bulk capacitors should be mounted as close as possible to the power vias. The
distance should be less than 50 mils. Additional bulk capacitors can be placed near the edge of the BGA via array. Placing the
decoupling capacitors close to the power balls is critical to minimize inductance and ensure high-speed transient current required
by the processor. See the i.MX8 QM and i.MX8 QXP development platform layouts for examples of the desired decoupling
capacitor placement.
Correct via size is critical for preserving adequate routing space. The recommended geometry for the via and pads on an i.MX8
QM design is a metric 45r20 via (0.2 mm drill, 0.45 mm annular ring), while for an i.MX8 QXP design, it is an imperial 18r10 via
(10 mil drill, 18 mil annular ring). An 18r8 via may also be used.
The following list provides the main recommendations for choosing the correct decoupling scheme:
• Place the largest capacitance in the smallest package that the budget and manufacturing can support.
• For high-speed bypassing, select the required capacitance with the smallest package (for example, 0.1 μF, 0.22 μF, 1.0
μF, 2.2 μF, or even 4.7 μF in an 0201 package size).
• Minimize the trace length (inductance) to small caps.
• Series inductance cancels out capacitance.
• Tie caps to GND plane directly with a via.
• Place capacitors close to the power ball of the associated package from the schematic.
• A preferred BGA power decoupling design is available on the development platform board design available on
www.nxp.com. Customers should use the NXP design strategy for power and decoupling.
Note: NXP uses 0402 capacitors in its customer designs as an example for customers who may
not be able to use 0201 components. Nevertheless, NXP recommends using 0201 capacitor where
possible: 0201 capacitors have less package inductance and the number of capacitors placed
underneath the processor can be increased.
3.3 Stack-up recommendations
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3.3.1 Stack-up recommendation (i.MX8 QM)
Due to the number of balls on the i.MX 8QM processor in the 29 mm x 29 mm package, it is recommended to use a minimum
12-layer PCB stack-up. Of the 12-layers on the PCB, a sufficient number of layers must be dedicated to power routing to ensure
the IR drop target of 1 % for the i.MX8 QM CPU power rails is met.
The constraints for the trace width depend on a number of factors, such as the board stack-up and associated dielectric and copper
thickness, required impedance, and required current (for power traces). The stack-up also determines the constraints for routing
and spacing. Consider the following when designing the stack-up and selecting board material:
• Board stack-up is critical for high-speed signal quality.
• Preplanning impedance of critical traces is required.
• High-speed signals must have reference planes on adjacent layers to minimize crosstalk.
• Use PCB materials that have good transmission qualities at high frequencies utilized by the i.MX8 QM interfaces. The
NXP i.MX8 QM customer platform utilizes Megtron 6.
Figure 1. i.MX8 QM board stack-up
3.3.2 Stack-up recommendation (i.MX8 QXP)
For the i.MX 8QXP processor in the 21 mm x 21 mm package, it is recommended to use a minimum 8-layer PCB stack-up. Of the
eight layers on the PCB, a sufficient number of layers must be dedicated to power routing to ensure that the IR drop target of 1 %
for the i.MX8 QXP CPU power rails is met. The Cu foil thickness of the power routing layers may be increased to provide additional
current carrying capacity.
Consider the following when designing the stack-up and selecting board material:
• Board stack-up is critical for high-speed signal quality.
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