NXP Semiconductors S32G-VNP-GLDBOX User manual

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S32G-VNP-GLDBOX
Reference Manual
Version: 0.4

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Contents
1 Introduction 6
1.1 Acronyms and abbreviations 6
1.2 Related documentation 7
1.3 Board version 8
2 S32G-VNP-GLDBOX Hardware 9
2.1 Hardware resources 9
2.2 Block diagram 10
2.3 PCB specification 11
2.4 Top view 11
2.5 Connectors 12
2.6 Buttons 13
2.7 Power switch 13
2.8 DIP Switches 14
2.9 Jumpers 17
2.10 LEDs 18
3 Functional Descriptions 19
3.1 Power supply 19
3.2 Boot 21
3.3 Reset 23
3.4 Clocks 24
3.5 JTAG Connections 25
3.6 Aurora Trace 25
3.7 External Memory and Storage 25
3.7.1 LPDDR4 25
3.7.2 NOR flash 26
3.7.3 SD/eMMC 26
3.8 SerDes interfaces 27
3.9 Ethernet 28
3.9.1 Automotive Ethernet switch 29
3.9.2 Ethernet PHYs 30
3.9.3 SMI interface 31
3.10 CAN 31

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3.11 LIN and UART 35
3.12 FlexRay 36
3.13 DSPI 36
3.14 I2C 37
3.15 USB 38
4 Cables Description 39
5 Revision History 43

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Tables
Table 1. Acronyms and abbreviations................................................................................6
Table 2. Related documentation...........................................................................................7
Table 3. S32G-VNP-GLDBOX board versions..............................................................8
Table 4. Hardware resources.................................................................................................9
Table 5. S32G-VNP-GLDBOX PCB specifications................................................... 11
Table 6. The connectors of the S32G-VNP-GLDBOX............................................ 12
Table 7. The buttons of the S32G-VNP-GLDBOX.................................................... 13
Table 8. The power switch of the S32G-VNP-GLDBOX........................................ 13
Table 9. DIP switches on the S32G-VNP-GLDBOX............................................... 14
Table 10. The configurations of boot mode.................................................................. 17
Table 11. Jumpers on the S32G-VNP-GLDBOX....................................................... 17
Table 12. LEDs on the S32G-VNP-GLDBOX.............................................................. 18
Table 13. Values of the boot mode pins ........................................................................ 22
Table 14. The memory map of the DDR and NOR Flash...................................... 25
Table 15. SerDes_0 work modes and corresponding settings........................... 27
Table 16. SerDes_1 work modes and corresponding settings............................. 28
Table 17. SJA1110 Ethernet port connections........................................................... 30
Table 18. Ethernet PHY description................................................................................. 30
Table 19. SMI interfaces........................................................................................................ 31
Table 20. CAN PHY connections...................................................................................... 31
Table 21. LIN and UART connections............................................................................ 35
Table 22. FlexRay connections.......................................................................................... 36
Table 23. DSPI connections................................................................................................ 37
Table 24. I2C connections.................................................................................................... 37
Table 25. USB connections.................................................................................................. 38
Table 26. J6 Cable................................................................................................................... 39
Table 27. J5 Cable................................................................................................................... 40
Table 28. J53 Cable................................................................................................................. 41

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Figures
Figure 1. The block diagram of S32G-VNP-GLDBOX............................................ 10
Figure 2. The top view of S32G-VNP-GLDBOX......................................................... 11
Figure 3. The power supply block diagram of S32G-VNP-GLDBOX REV D20
Figure 4. Boot mode pins...................................................................................................... 21
Figure 5. RCON pins............................................................................................................... 22
Figure 6. Reset tree of S32G-VNP-GLDBOX.............................................................. 23
Figure 7. Clock tree of S32G-VNP-GLDBOX REVD................................................ 24
Figure 8. The connection of LPDDR4 SDRAM........................................................... 25
Figure 9. Connection between S32G274A and the NOR flash chip................. 26
Figure 10. Connections between S32G274A and SD/eMMC.............................. 27
Figure 11. Ethernet connection diagram of S32G-VNP-GLDBOX.................... 29

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1Introduction
The S32G-VNP-GLDBOX is a compact, highly-optimized and integrated reference design board based on the
S32G274A Vehicle Network Processor. With the high-performance computing capacity and rich
input/output(I/O) of the S32G274A, this board is suitable for a variety of typical automotive applications, such
as service-oriented gateway, vehicle central computing nodes, domain controller, safety controller, black-box,
smart antenna, FOTA etc. It can be directly used by car-makers, suppliers and software ecosystem partners
to accelerate development for a shorter time-to-market.
This document describes the hardware features of the board specifications, block diagram, connectors and
interfaces.
1.1 Acronyms and abbreviations
The table below lists commonly used acronyms and abbreviations.
Table 1. Acronyms and abbreviations
Acronym/abbreviation
Description
CAN
Controller Area Network
CAN FD
CAN with Flexible Data-Rate
DDR
Double Data Rate DRAM
ECC
Error Correcting Code
eMMC
Embedded Multimedia Card
FOTA
Firmware Over The Air
GMAC
Gigabit Ethernet Media Access Controller
GPIO
General Purpose In/Out
I2C
Inter-integrated Circuit
JTAG
Joint Test Action Group
LIN
Local Interconnect Network
LLCE
Low Latency Communications Engine

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MII
Media Independent Interface
PCBA
Printed Circuit Board Assembly
PFE
Packet Forwarding Engine
PHY
Physical Layer
RGMII
Reduced General Media Independent Interface
SerDes
Serializer/Deserializer
SGMII
Serial Gigabit Media Independent Interface
SMI
Serial Management Interface
SPDT
Single Pole Double Throw
SSD
Solid State Drive
TSN
Time Sensitive Network
USB
Universal serial bus
uSDHC
Ultra Secured Digital Host Controller
1.2 Related documentation
The table below lists the documents that can be referred to for more information on the S32G-VNP-GLDBOX.
Some of the documents listed below may be available only under a non-disclosure agreement (NDA). To
request access to these documents, please contact your local field applications engineer (FAE) or sales
representative.
Table 2. Related documentation
Document
Description
S32G2 Product Brief
Provides a brief overview of the S32G2 processor.
S32G2 Reference Manual
Provides a detailed description of the S32G2
multicore processor and its features, such as memory
map, serial interfaces, chip features, and clock
information.

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S32G2 Data Sheet
Provides information about S32G electrical
characteristics, and ordering information.
Errata S32G2 Rev2 Mask0P77B
Lists the details of all known silicon errata for the
S32G2 Rev2.
S32G2 Hardware Design Guide
Provides guidelines of S32G2 hardware design, such
as power management, layout guidelines.
S32G-VNP-GLDBOX Quick Start Guide
Provides an overview of the S32G-VNP-GLDBOX,
and describes how to quickly bring-up the board.
1.3 Board version
The table below lists the board versions for the S32G-VNP-GLDBOX.
Table 3. S32G-VNP-GLDBOX board versions
PCBA version
Schematic
Brief revision information
Board version REV C
SCH-47800 REVC
The first orderable version of the S32G-VNP-GLDBOX.
Board version REV D
SCH-47800 REVD
1. Added core current measurement circuit. The core
current information can be obtained by I2C4.
2. Added temperature measurement circuit. The board
temperature information can be obtained by I2C0.
3. Replaced AQR107-B0-EG-Y with AQR113C-B0-C.
4. Changed the supply voltage of U108
(PPF5020AMBADES).
5. Changed R229 from 68.1K to 62K, R244 from 22K
to 27K for board version identification.
The assembly version of the S32G-VNP-GLDBOX is printed on the label which is usually pasted on the bottom
side of the PCB.

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2S32G-VNP-GLDBOX Hardware
This section describes the hardware resources, specifications and mechanical information of the S32G-VNP-
GLDBOX.
2.1 Hardware resources
The hardware resources of the S32G-VNP-GLDBOX are listed as below.
Table 4. Hardware resources
Items
Resources
Description
Processor
S32G274A
•4 Arm Cortex-A53 cores (with optional cluster lockstep)
•3 dual-core lockstep Arm Cortex-M7 cores
•Hardware Security Engine (HSE) supports SHE / EVITA
•CAN, LIN and FlexRay offload with Low Latency Communications
Engine (LLCE)
•Gigabit Ethernet Packet Forwarding Engine (PFE)
•8MB Embedded System RAM with ECC
•32KB Standby RAM with ECC
Memory
LPDDR4
1 x LPDDR4 (4GB) with inline-ECC and self-refresh
NOR flash
1 x NOR Flash (64MB)
eMMC
1 x eMMC(32GB)
SD card
1 x Slot for SD card
Connectivity
Ethernet
1 x 100BASE-TX
6 x 100BASE-T1
5 x 1000BASE-T
USB
1 x USB 2.0 port as host/device mode
FlexRay
1 x LLCE FlexRay
LIN
4 x LLCE LIN as master mode by default
1 x LINFlexD as slave mode by default
CAN/CAN_FD
16 x LLCE CAN/CAN FD
2 x FlexCAN /CAN FD
ADC
5 x ADC input
GPIO
6 x GPI/GPIO with multiplexable functions (GPI/GPIO, I2C, DSPI,
EIRQ, Wakeup input, and FTM)

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Debug &
Trace
UART
2 x UART
JTAG
1 x 20PIN JTAG for S32G274A
1 x 10PIN JTAG for SJA1110A
Aurora Trace
1 x AURORA
Additional
Features
Low-power
mode
•Supports Low-power mode
•Supports Low-power mode with DDR self-refresh
RTC
Supports internal RTC and external RTC
Expansion
Connector
M.2 slot
1 x M.2 M-key slot
1 x M.2 E-key slot
Tips: When M.2 M-key card is inserted, M.2 E-key slot will not be available, and vice versa.
PCIe x1
socket
1 x PCIe x1 socket
2.2 Block diagram
The figure below shows the block diagram of the S32G-VNP-GLDBOX.
S32G274A
Quad Cortex-A53 Frequency up to 1GHz
Tri Cortex-M7 Frequency up to 400MHz
QSPI Flash
512M-bit
200MHz
LPDDR4
32G-bit
SD Card eMMC 32G-
Byte
RTC
PCA85073A
LIN Phy
TJA1024
(Master Mode)
Gigabit Eth.
Phy
AR8035
Gigabit Eth.
Phy
KSZ9031
Gigabit Eth.
Phy
KSZ9031
Gigabit Eth.
Phy
AR8035
Eth. Switch SJA1110
Eth. Phy
LIN Phy
TJA1021
(Slave Mode)
FlexRay
Phy
TJA1081
UART-USB
FT232
Boot mode
select circuit
Parallel
RCON select
circuit
PMIC
VR5510
USB 2.0
Phy
USB83340
CAN Phy
TJA1043
6 pcs
UART-USB
FT232
CAN Phy
TJA1463
6 pcs
CAN Phy
TJA1153
4 pcs
CAN Phy
TJA1043
2 pcs
PMIC
FS5600
PMIC
PF5300
PMIC
PF5020 PMIC PF5020 Load Switch
GMAC0 PFE_MAC2 SerDes1SerDes0
100Base-T1 Phy x6 100Base-Tx Phy
100Base-T1 x6-ch 100Base-Tx
Port 2 Port 3
RGMII RGMII
PCIe X2
PCIe X2 PCIe X2
RGMII RGMII
uSDHC I/F LINFlex 2GPIO Flex CAN LINFlex 1 LINFlex 0 ULPIADC
IO Expander
PCAL6524H
SerDes1
multiplex circuit
SGMIIPCIe x1 SGMII
1000Base-T Port M.2 slot E-key M.2 slot M-key PCIe X1 socket 100Base-T1 Port 100Base-TX Port 1000Base-T Port 1GBase-T or 2.5GBase-T Port
USB PortUART0 PortUART1 PortAutomotive Bus PortMulti-Function PortSD Card Port12V Power Supply Input Port
ADC
x5ch GPIO
x6 Flex LIN
x1ch LLCE LIN x4ch LLCE CAN
x6ch LLCE CAN x4ch LLCE CAN x6ch Flex CAN
x2ch
FlexRay
x1ch
S32G Aurora Port
S32G JTAG Port
SJA1110 JTAG Port
NXP Device
LLCE LIN LLCE FlexRay LLCE CAN LLCE CAN LLCE CAN
Clock generator
Si5332
Figure 1. The block diagram of S32G-VNP-GLDBOX