NXP Semiconductors S32G-VNP-GLDBOX User manual

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S32G-VNP-GLDBOX
Reference Manual
Version: 0.4

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Contents
1 Introduction 6
1.1 Acronyms and abbreviations 6
1.2 Related documentation 7
1.3 Board version 8
2 S32G-VNP-GLDBOX Hardware 9
2.1 Hardware resources 9
2.2 Block diagram 10
2.3 PCB specification 11
2.4 Top view 11
2.5 Connectors 12
2.6 Buttons 13
2.7 Power switch 13
2.8 DIP Switches 14
2.9 Jumpers 17
2.10 LEDs 18
3 Functional Descriptions 19
3.1 Power supply 19
3.2 Boot 21
3.3 Reset 23
3.4 Clocks 24
3.5 JTAG Connections 25
3.6 Aurora Trace 25
3.7 External Memory and Storage 25
3.7.1 LPDDR4 25
3.7.2 NOR flash 26
3.7.3 SD/eMMC 26
3.8 SerDes interfaces 27
3.9 Ethernet 28
3.9.1 Automotive Ethernet switch 29
3.9.2 Ethernet PHYs 30
3.9.3 SMI interface 31
3.10 CAN 31

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3.11 LIN and UART 35
3.12 FlexRay 36
3.13 DSPI 36
3.14 I2C 37
3.15 USB 38
4 Cables Description 39
5 Revision History 43

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Tables
Table 1. Acronyms and abbreviations................................................................................6
Table 2. Related documentation...........................................................................................7
Table 3. S32G-VNP-GLDBOX board versions..............................................................8
Table 4. Hardware resources.................................................................................................9
Table 5. S32G-VNP-GLDBOX PCB specifications................................................... 11
Table 6. The connectors of the S32G-VNP-GLDBOX............................................ 12
Table 7. The buttons of the S32G-VNP-GLDBOX.................................................... 13
Table 8. The power switch of the S32G-VNP-GLDBOX........................................ 13
Table 9. DIP switches on the S32G-VNP-GLDBOX............................................... 14
Table 10. The configurations of boot mode.................................................................. 17
Table 11. Jumpers on the S32G-VNP-GLDBOX....................................................... 17
Table 12. LEDs on the S32G-VNP-GLDBOX.............................................................. 18
Table 13. Values of the boot mode pins ........................................................................ 22
Table 14. The memory map of the DDR and NOR Flash...................................... 25
Table 15. SerDes_0 work modes and corresponding settings........................... 27
Table 16. SerDes_1 work modes and corresponding settings............................. 28
Table 17. SJA1110 Ethernet port connections........................................................... 30
Table 18. Ethernet PHY description................................................................................. 30
Table 19. SMI interfaces........................................................................................................ 31
Table 20. CAN PHY connections...................................................................................... 31
Table 21. LIN and UART connections............................................................................ 35
Table 22. FlexRay connections.......................................................................................... 36
Table 23. DSPI connections................................................................................................ 37
Table 24. I2C connections.................................................................................................... 37
Table 25. USB connections.................................................................................................. 38
Table 26. J6 Cable................................................................................................................... 39
Table 27. J5 Cable................................................................................................................... 40
Table 28. J53 Cable................................................................................................................. 41

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Figures
Figure 1. The block diagram of S32G-VNP-GLDBOX............................................ 10
Figure 2. The top view of S32G-VNP-GLDBOX......................................................... 11
Figure 3. The power supply block diagram of S32G-VNP-GLDBOX REV D20
Figure 4. Boot mode pins...................................................................................................... 21
Figure 5. RCON pins............................................................................................................... 22
Figure 6. Reset tree of S32G-VNP-GLDBOX.............................................................. 23
Figure 7. Clock tree of S32G-VNP-GLDBOX REVD................................................ 24
Figure 8. The connection of LPDDR4 SDRAM........................................................... 25
Figure 9. Connection between S32G274A and the NOR flash chip................. 26
Figure 10. Connections between S32G274A and SD/eMMC.............................. 27
Figure 11. Ethernet connection diagram of S32G-VNP-GLDBOX.................... 29

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1Introduction
The S32G-VNP-GLDBOX is a compact, highly-optimized and integrated reference design board based on the
S32G274A Vehicle Network Processor. With the high-performance computing capacity and rich
input/output(I/O) of the S32G274A, this board is suitable for a variety of typical automotive applications, such
as service-oriented gateway, vehicle central computing nodes, domain controller, safety controller, black-box,
smart antenna, FOTA etc. It can be directly used by car-makers, suppliers and software ecosystem partners
to accelerate development for a shorter time-to-market.
This document describes the hardware features of the board specifications, block diagram, connectors and
interfaces.
1.1 Acronyms and abbreviations
The table below lists commonly used acronyms and abbreviations.
Table 1. Acronyms and abbreviations
Acronym/abbreviation
Description
CAN
Controller Area Network
CAN FD
CAN with Flexible Data-Rate
DDR
Double Data Rate DRAM
ECC
Error Correcting Code
eMMC
Embedded Multimedia Card
FOTA
Firmware Over The Air
GMAC
Gigabit Ethernet Media Access Controller
GPIO
General Purpose In/Out
I2C
Inter-integrated Circuit
JTAG
Joint Test Action Group
LIN
Local Interconnect Network
LLCE
Low Latency Communications Engine

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MII
Media Independent Interface
PCBA
Printed Circuit Board Assembly
PFE
Packet Forwarding Engine
PHY
Physical Layer
RGMII
Reduced General Media Independent Interface
SerDes
Serializer/Deserializer
SGMII
Serial Gigabit Media Independent Interface
SMI
Serial Management Interface
SPDT
Single Pole Double Throw
SSD
Solid State Drive
TSN
Time Sensitive Network
USB
Universal serial bus
uSDHC
Ultra Secured Digital Host Controller
1.2 Related documentation
The table below lists the documents that can be referred to for more information on the S32G-VNP-GLDBOX.
Some of the documents listed below may be available only under a non-disclosure agreement (NDA). To
request access to these documents, please contact your local field applications engineer (FAE) or sales
representative.
Table 2. Related documentation
Document
Description
S32G2 Product Brief
Provides a brief overview of the S32G2 processor.
S32G2 Reference Manual
Provides a detailed description of the S32G2
multicore processor and its features, such as memory
map, serial interfaces, chip features, and clock
information.

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S32G2 Data Sheet
Provides information about S32G electrical
characteristics, and ordering information.
Errata S32G2 Rev2 Mask0P77B
Lists the details of all known silicon errata for the
S32G2 Rev2.
S32G2 Hardware Design Guide
Provides guidelines of S32G2 hardware design, such
as power management, layout guidelines.
S32G-VNP-GLDBOX Quick Start Guide
Provides an overview of the S32G-VNP-GLDBOX,
and describes how to quickly bring-up the board.
1.3 Board version
The table below lists the board versions for the S32G-VNP-GLDBOX.
Table 3. S32G-VNP-GLDBOX board versions
PCBA version
Schematic
Brief revision information
Board version REV C
SCH-47800 REVC
The first orderable version of the S32G-VNP-GLDBOX.
Board version REV D
SCH-47800 REVD
1. Added core current measurement circuit. The core
current information can be obtained by I2C4.
2. Added temperature measurement circuit. The board
temperature information can be obtained by I2C0.
3. Replaced AQR107-B0-EG-Y with AQR113C-B0-C.
4. Changed the supply voltage of U108
(PPF5020AMBADES).
5. Changed R229 from 68.1K to 62K, R244 from 22K
to 27K for board version identification.
The assembly version of the S32G-VNP-GLDBOX is printed on the label which is usually pasted on the bottom
side of the PCB.

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2S32G-VNP-GLDBOX Hardware
This section describes the hardware resources, specifications and mechanical information of the S32G-VNP-
GLDBOX.
2.1 Hardware resources
The hardware resources of the S32G-VNP-GLDBOX are listed as below.
Table 4. Hardware resources
Items
Resources
Description
Processor
S32G274A
•4 Arm Cortex-A53 cores (with optional cluster lockstep)
•3 dual-core lockstep Arm Cortex-M7 cores
•Hardware Security Engine (HSE) supports SHE / EVITA
•CAN, LIN and FlexRay offload with Low Latency Communications
Engine (LLCE)
•Gigabit Ethernet Packet Forwarding Engine (PFE)
•8MB Embedded System RAM with ECC
•32KB Standby RAM with ECC
Memory
LPDDR4
1 x LPDDR4 (4GB) with inline-ECC and self-refresh
NOR flash
1 x NOR Flash (64MB)
eMMC
1 x eMMC(32GB)
SD card
1 x Slot for SD card
Connectivity
Ethernet
1 x 100BASE-TX
6 x 100BASE-T1
5 x 1000BASE-T
USB
1 x USB 2.0 port as host/device mode
FlexRay
1 x LLCE FlexRay
LIN
4 x LLCE LIN as master mode by default
1 x LINFlexD as slave mode by default
CAN/CAN_FD
16 x LLCE CAN/CAN FD
2 x FlexCAN /CAN FD
ADC
5 x ADC input
GPIO
6 x GPI/GPIO with multiplexable functions (GPI/GPIO, I2C, DSPI,
EIRQ, Wakeup input, and FTM)

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Debug &
Trace
UART
2 x UART
JTAG
1 x 20PIN JTAG for S32G274A
1 x 10PIN JTAG for SJA1110A
Aurora Trace
1 x AURORA
Additional
Features
Low-power
mode
•Supports Low-power mode
•Supports Low-power mode with DDR self-refresh
RTC
Supports internal RTC and external RTC
Expansion
Connector
M.2 slot
1 x M.2 M-key slot
1 x M.2 E-key slot
Tips: When M.2 M-key card is inserted, M.2 E-key slot will not be available, and vice versa.
PCIe x1
socket
1 x PCIe x1 socket
2.2 Block diagram
The figure below shows the block diagram of the S32G-VNP-GLDBOX.
S32G274A
Quad Cortex-A53 Frequency up to 1GHz
Tri Cortex-M7 Frequency up to 400MHz
QSPI Flash
512M-bit
200MHz
LPDDR4
32G-bit
SD Card eMMC 32G-
Byte
RTC
PCA85073A
LIN Phy
TJA1024
(Master Mode)
Gigabit Eth.
Phy
AR8035
Gigabit Eth.
Phy
KSZ9031
Gigabit Eth.
Phy
KSZ9031
Gigabit Eth.
Phy
AR8035
Eth. Switch SJA1110
Eth. Phy
LIN Phy
TJA1021
(Slave Mode)
FlexRay
Phy
TJA1081
UART-USB
FT232
Boot mode
select circuit
Parallel
RCON select
circuit
PMIC
VR5510
USB 2.0
Phy
USB83340
CAN Phy
TJA1043
6 pcs
UART-USB
FT232
CAN Phy
TJA1463
6 pcs
CAN Phy
TJA1153
4 pcs
CAN Phy
TJA1043
2 pcs
PMIC
FS5600
PMIC
PF5300
PMIC
PF5020 PMIC PF5020 Load Switch
GMAC0 PFE_MAC2 SerDes1SerDes0
100Base-T1 Phy x6 100Base-Tx Phy
100Base-T1 x6-ch 100Base-Tx
Port 2 Port 3
RGMII RGMII
PCIe X2
PCIe X2 PCIe X2
RGMII RGMII
uSDHC I/F LINFlex 2GPIO Flex CAN LINFlex 1 LINFlex 0 ULPIADC
IO Expander
PCAL6524H
SerDes1
multiplex circuit
SGMIIPCIe x1 SGMII
1000Base-T Port M.2 slot E-key M.2 slot M-key PCIe X1 socket 100Base-T1 Port 100Base-TX Port 1000Base-T Port 1GBase-T or 2.5GBase-T Port
USB PortUART0 PortUART1 PortAutomotive Bus PortMulti-Function PortSD Card Port12V Power Supply Input Port
ADC
x5ch GPIO
x6 Flex LIN
x1ch LLCE LIN x4ch LLCE CAN
x6ch LLCE CAN x4ch LLCE CAN x6ch Flex CAN
x2ch
FlexRay
x1ch
S32G Aurora Port
S32G JTAG Port
SJA1110 JTAG Port
NXP Device
LLCE LIN LLCE FlexRay LLCE CAN LLCE CAN LLCE CAN
Clock generator
Si5332
Figure 1. The block diagram of S32G-VNP-GLDBOX

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2.3 PCB specification
The table below lists the specifications of the S32G-VNP-GLDBOX PCB.
Table 5. S32G-VNP-GLDBOX PCB specifications
Items
Specifications
Ambient temperature
~ 35°C, Lab environment
PCB dimensions
180mm x 140mm
2.4 Top view
The figure below shows the top view of the S32G-VNP-GLDBOX.
Figure 2. The top view of S32G-VNP-GLDBOX

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2.5 Connectors
The table below lists the connectors of the S32G-VNP-GLDBOX. Please refer to the schematic for more detail.
Table 6. The connectors of the S32G-VNP-GLDBOX
Part
Connector type
Description
Typical connection
J1
USB 2.0 Micro-AB
connector
Console port (UART1)
Connects to host computer.
J2
USB 2.0 Micro-AB
connector
Console port (UART0)
Connects to host computer.
J3
SD card slot
SD card slot
Connects to the SD card.
J4
USB 2.0 Micro-AB
connector
Supports USB 2.0 host/device
mode.
Host mode: Connects to OTG cable.
Device mode: Connects to USB-A to
Micro-B cable.
J5
2 x 13 connector
Connector for GPIO, ADC, LIN,
power supply interfaces.
Connects to the cable in accessories.
J6
2 x 20 connector
Connector for CAN and FlexRay
interfaces.
Connects to the cable in accessories.
J44
2 x 10 connector
SJA1110 JTAG header
Connects to the debugger.
J47
M.2 M-key slot
PCIe x2 M.2 slot with key M and
supports PCIe x2 (Gen3, Gen2,
Gen1) and PCIe x1 (Gen3, Gen2,
Gen1)
Connects to PCIe x2 module (size:
2242, key: M key, B+M key).
It is recommended to connect 2242
B+M key NVME SSD (such as
TOSHIBA RC100 240G, which has
been already tested on S32G-VNP-
GLDBOX).
If J47 is used, J56 is not available.
J48
2 x 10 connector
S32G274A JTAG header
Connects to the debugger.
J53
2 x 12 connector
Connector for 100BASE-T1
interfaces
Connects to the cable in accessories.
J56
M.2 E-key slot
PCIe x2 M.2 slot with key E and
supports PCIe x2 (Gen3, Gen2,
Gen1) and PCIe x1 (Gen3, Gen2,
Gen1)
Connects to PCIe x2 module (size:
2242, key: E key, A+E key)
If J56 is used, J47 is not available
J57
2 x 20 connector
S32G274A Aurora trace header
Connects to the debugger
J176
DC power jack
12 V power jack
Connects to 12V AC-DC power
adapter
P1
PCIe x1 socket
Supports PCIe x1 (Gen3, Gen2,
Gen1)
Connects to PCIe x1 EP module

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P2
Dual-port
RJ45 connector
Ethernet port with Magnetics for
1000BASE-T/100BASE-TX
P4A(bottom)
P4B(top)
Connects to RJ45 Ethernet cable
P3
Dual-port
RJ45 connector
Ethernet port with Magnetics for
1000BASE-T/100BASE-TX
P3A(bottom)
P3B(top)
Connects to RJ45 Ethernet cable
P4
Single-port
RJ45 connector
Ethernet port with Magnetics for
100BASE-TX
Connects to RJ45 Ethernet cable
P5
Single-port
RJ45 connector
Ethernet port with Magnetics for
1000BASE-T/100BASE-TX
Connects to RJ45 Ethernet cable
2.6 Buttons
The table below describes the buttons of the S32G-VNP-GLDBOX.
Table 7. The buttons of the S32G-VNP-GLDBOX
Part
Name
Description
SW1
POR_B
Press SW1 to reset the system.
S32G274A will perform a power-on reset.
SW2
RESET_B
Press SW2 to reset the system.
S32G274A will perform functional reset.
SW16
NMI
Press SW16 to assert non-maskable interrupt.
2.7Power switch
The table below describes the power switch of the S32G-VNP-GLDBOX.
Table 8. The power switch of the S32G-VNP-GLDBOX
Switch
Default setting
Description
SW15
POS. 1
The SW15 is an SPDT switch.
The figure below shows the 3-position of actuator.
Switch Actuator Position
If the actuator is moved to POS. 1, the power supply is input from the
Power Jack(J176)

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If the actuator is moved to POS. 2, the board power supply is turned off.
If the actuator is moved to POS. 3, the power supply is input from the
connector(J5-pin2)
2.8 DIP Switches
The table below describes the DIP switches on the S32G-VNP-GLDBOX.
Table 9. DIP switches on the S32G-VNP-GLDBOX
Switch
Default setting
Description
SW4[1]
OFF
ON : S32G274A Fuse word BOOT_CFG1[0] = 1
OFF: S32G274A Fuse word BOOT_CFG1[0] = 0
SW4[2]
OFF
ON : S32G274A Fuse word BOOT_CFG1[1] = 1
OFF: S32G274A Fuse word BOOT_CFG1[1] = 0
SW4[3]
OFF
ON : S32G274A Fuse word BOOT_CFG1[2] = 1
OFF: S32G274A Fuse word BOOT_CFG1[2] = 0
SW4[4]
OFF
ON : S32G274A Fuse word BOOT_CFG1[3] = 1
OFF: S32G274A Fuse word BOOT_CFG1[3] = 0
SW4[5]
OFF
ON : S32G274A Fuse word BOOT_CFG1[4] = 1
OFF: S32G274A Fuse word BOOT_CFG1[4] = 0
SW4[6]
OFF
ON : S32G274A Fuse word BOOT_CFG1[5] = 1
OFF: S32G274A Fuse word BOOT_CFG1[5] = 0
SW4[7]
ON
ON : S32G274A Fuse word BOOT_CFG1[6] = 1
OFF: S32G274A Fuse word BOOT_CFG1[6] = 0

15
SW4[8]
OFF
ON : S32G274A Fuse word BOOT_CFG1[7] = 1
OFF: S32G274A Fuse word BOOT_CFG1[7] = 0
SW5[1]
OFF
ON : S32G274A Fuse word BOOT_CFG1[8] = 1
OFF: S32G274A Fuse word BOOT_CFG1[8] = 0
SW5[2]
OFF
ON : S32G274A Fuse word BOOT_CFG1[9] = 1
OFF: S32G274A Fuse word BOOT_CFG1[9] = 0
SW5[3]
OFF
ON : S32G274A Fuse word BOOT_CFG1[10] = 1
OFF: S32G274A Fuse word BOOT_CFG1[10] = 0
SW5[4]
OFF
ON : S32G274A Fuse word BOOT_CFG1[11] = 1
OFF: S32G274A Fuse word BOOT_CFG1[11] = 0
SW5[5]
OFF
ON : S32G274A Fuse word BOOT_CFG1[12] = 1
OFF: S32G274A Fuse word BOOT_CFG1[12] = 0
SW5[6]
OFF
ON : S32G274A Fuse word BOOT_CFG1[13] = 1
OFF: S32G274A Fuse word BOOT_CFG1[13] = 0
SW5[7]
OFF
ON : S32G274A Fuse word BOOT_CFG1[14] = 1
OFF: S32G274A Fuse word BOOT_CFG1[14] = 0
SW5[8]
OFF
ON : S32G274A Fuse word BOOT_CFG1[15] = 1
OFF: S32G274A Fuse word BOOT_CFG1[15] = 0
SW6[1]
OFF
ON : S32G274A Fuse word BOOT_CFG1[16] = 1
OFF: S32G274A Fuse word BOOT_CFG1[16] = 0
SW6[2]
OFF
ON : S32G274A Fuse word BOOT_CFG1[17] = 1
OFF: S32G274A Fuse word BOOT_CFG1[17] = 0
SW6[3]
OFF
ON : S32G274A Fuse word BOOT_CFG1[18] = 1
OFF: S32G274A Fuse word BOOT_CFG1[18] = 0
SW6[4]
OFF
ON : S32G274A Fuse word BOOT_CFG1[19] = 1
OFF: S32G274A Fuse word BOOT_CFG1[19] = 0
SW6[5]
OFF
ON : S32G274A Fuse word BOOT_CFG1[20] = 1
OFF: S32G274A Fuse word BOOT_CFG1[20] = 0
SW6[6]
OFF
ON : S32G274A Fuse word BOOT_CFG1[21] = 1
OFF: S32G274A Fuse word BOOT_CFG1[21] = 0
SW6[7]
OFF
ON : S32G274A Fuse word BOOT_CFG1[22] = 1
OFF: S32G274A Fuse word BOOT_CFG1[22] = 0
SW6[8]
OFF
ON : S32G274A Fuse word BOOT_CFG1[23] = 1
OFF: S32G274A Fuse word BOOT_CFG1[23] = 0
SW7[1]
OFF
ON : S32G274A Fuse word BOOT_CFG1[24] = 1
OFF: S32G274A Fuse word BOOT_CFG1[24] = 0
SW7[2]
OFF
ON : S32G274A Fuse word BOOT_CFG1[25] = 1
OFF: S32G274A Fuse word BOOT_CFG1[25] = 0

16
SW7[3]
OFF
ON : S32G274A Fuse word BOOT_CFG1[26] = 1
OFF: S32G274A Fuse word BOOT_CFG1[26] = 0
SW7[4]
OFF
ON : S32G274A Fuse word BOOT_CFG1[27] = 1
OFF: S32G274A Fuse word BOOT_CFG1[27] = 0
SW7[5]
OFF
ON : S32G274A Fuse word BOOT_CFG1[28] = 1
OFF: S32G274A Fuse word BOOT_CFG1[28] = 0
SW7[6]
OFF
ON : S32G274A Fuse word BOOT_CFG1[29] = 1
OFF: S32G274A Fuse word BOOT_CFG1[29] = 0
SW7[7]
OFF
ON : S32G274A Fuse word BOOT_CFG1[30] = 1
OFF: S32G274A Fuse word BOOT_CFG1[30] = 0
SW7[8]
OFF
ON : S32G274A Fuse word BOOT_CFG1[31] = 1
OFF: S32G274A Fuse word BOOT_CFG1[31] = 0
SW3[1]
ON
ON : Connects the S32G274A's uSDHC interface to SD card.
OFF : Connects the S32G274A's uSDHC interface to eMMC
SW8[1]
ON
Refer to 3.8 SerDes interface for more detail
SW17[1]
ON
Refer to 3.8 SerDes interface for more detail
SW12[1]
ON
1-ON, 2-ON : SJA1110 performs SDL boot.
1-ON, 2-OFF : SJA1110 performs NVM boot using SPI Flash.
1-OFF, 2-OFF : Reserved
1-OFF, 2-ON : Reserved
SW12[2]
OFF
SW11[1]
OFF
ON : Connects GPIO6,GPIO7,GPIO95 to U128(RGB LED)
OFF : Connects GPIO6,GPIO7,GPIO95 to J5 connector
SW9[1]
OFF
1-OFF, 2-OFF : BOOTMOD1 value: 0
1-ON, 2-OFF : BOOTMOD1 value: 1
1-OFF,2-ON : BOOTMOD1 value: RESET_B
1-ON, 2-ON : BOOTMOD1 value: INV_RESET_B
SW9[2]
OFF
SW10[1]
ON
1-OFF, 2-OFF : BOOTMOD0 value: 0
1-ON, 2-OFF : BOOTMOD0 value: 1
1-OFF,2-ON : BOOTMOD0 value: RESET_B
1-ON, 2-ON : BOOTMOD0 value: INV_RESET_B
SW10[2]
OFF
Please refer to the S32G274A_Fuse_Map_Tables.xlsx attached to the S32G2 Reference Manual for the
description of BOOT_CFG1.

17
The table below describes the boot mode configuration of S32G-VNP-GLDBOX..
Table 10. The configurations of boot mode
Switch
SD Boot Setting
(default)
eMMC Boot Setting
NOR Flash Boot
Setting
Serial Boot
Setting
SW3
ON
OFF
-
-
SW4
7-ON, REST-OFF
6,7-ON, REST-OFF
ALL-OFF
ALL-OFF
SW5
ALL-OFF
ALL-OFF
ALL-OFF
ALL-OFF
SW6
ALL-OFF
ALL-OFF
ALL-OFF
ALL-OFF
SW7
ALL-OFF
ALL-OFF
ALL-OFF
ALL-OFF
SW9
1-OFF,2-OFF
1-OFF,2-OFF
1-OFF,2-OFF
1-OFF,2-OFF
SW10
1-ON,2-OFF
1-ON,2-OFF
1-ON,2-OFF
1-OFF,2-OFF
2.9 Jumpers
The table below describes the jumpers on the S32G-VNP-GLDBOX.
Table 11. Jumpers on the S32G-VNP-GLDBOX
Part
Type
Default
setting
Description
J184
1 x 2
connector
1-2 Shorted
1-2 Open : VR5510 enters normal mode after power
on.(Watchdog will be enabled)
1-2 Shorted : VR5510 enters debug mode after power on.
(Watchdog will be disabled)
J180
2 x 2
connector
1-2 Shorted
3-4 Shorted
Reserved
J181
2 x 2
connector
1-2 Open
3-4 Open
Reserved
J185 1
1 x 2
connector
1-2 Open
1-2 Open : Disconnect the FS0B signal from the functional
safety management circuit.
1-2 Shorted : Connect the FS0B signal to the functional safety
management circuit.
J186 1
1 x 2
connector
1-2 Open
1-2 Open : The work mode of the USB PHY is determined by the
cable.
1-2 Shorted : USB PHY works in HOST mode.
J187 1
1 x 3
connector
1-2 Shorted
1-2 Shorted : Connect the VCCQ power
rail of eMMC to 3.3V.

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2-3 Shorted : Connect the VCCQ power
rail of eMMC to 1.8V.
Note: The S32G-VNP-GLDBOX REVC does not contain J185, J186, J187.
2.10 LEDs
The table below describes the LEDs on the S32G-VNP-GLDBOX.
Table 12. LEDs on the S32G-VNP-GLDBOX
LED
Color
Description
D33
Green
Lights up when the SJA1110 configuration is available
D7
Red/Green
Lights up in red: UART1 output is in progress
Lights up in green: UART1 input is in progress
D8
Red/Green
Lights up in red: UART0 output is in progress
Lights up in green: UART0 input is in progress
D36
Green
Lights up when the SSD status is available
D2
Red(top)
Lights up when the board is resetting.
Green(bottom)
Lights up when the board is power-on.
U128
Green
Lights up when GPIO95 keeps LOW and SW11[1] = ON.
Red
Lights up when GPIO7 keeps LOW and SW11[1] = ON.
Blue
Lights up when GPIO6 keeps LOW and SW11[1] = ON.

19
3Functional Descriptions
3.1 Power supply
The power supply of the S32G-VNP-GLDBOX is comprised of two parts: the external 12V AC-DC power
adapter and the onboard PMIC.
The specifications of the 12V AC-DC power adapter are listed below:
•Input: 110-240V AC, 50/60 Hz
•Output: 12 V, 6.67A AC-DC, 80W MAX
The figure below shows the power supply block diagram of the S32G-VNP-GLDBOX REV D.
For the power supply block diagram of S32G-VNP-GLDBOX, please refer to SCH-47800_C.pdf.

20
DC 12V
DC 12V
J5-Pin2
J176
P12V
SW15
P12V_CONN
P12V_JACK
Protection
U41 ( VR5510 ) VPRE
U94 ( FS5600 ) BUCK1
U94 ( FS5600 ) BUCK2
Load Switch
U17 (TJA1043) VBAT; U72 (TJA1043) VBAT; U18 (TJA1043) VBAT; U71 (TJA1043) VBAT; U16 (TJA1043) VBAT; U73 (TJA1043) VBAT;
U21 (TJA1463) VBAT; U68 (TJA1463) VBAT; U22 (TJA1463) VBAT; U67 (TJA1463) VBAT; U99 (TJA1463) VBAT; U98 (TJA1463) VBAT;
U20 (TJA1153) VBAT; U69 (TJA1153) VBAT; U19 (TJA1153) VBAT; U70 (TJA1153) VBAT;
P1 (PCIe X1 socket) +12V; J5-Pin4; U23 (TJA1081) VBAT
U92 (PF5300) DNP
U41 ( VR5510 ) BUCK2
U41 ( VR5510 ) LDO2 Load switch
U41 ( VR5510 ) BUCK3
U41 ( VR5510 ) LDO1
Load switch
U41 ( VR5510 ) LDO3
Load switch
U41 ( VR5510 ) HVLDO
U41 ( VR5510 ) VBOOST Load switch
Load switch
U96 ( PF5020 ) BUCK1
U96 ( PF5020 ) BUCK2
U96 ( PF5020 ) BUCK3
U108 ( PF5020 ) BUCK1
U108 ( PF5020 ) BUCK3
U108 ( PF5020 ) LDO1
Load switch
AQR_3V3
AQR_1V0
AQR_0V7
+1V8
+1V2
+1V1
+3V3
+5V0
LDO3_3V3
LDO1_1V8
BUCK3_1V1
P0_8V
P1_8V_IO
VPRE_3V3
P12V_SW
Load switch
J50-Pin2 (FAN); U9 (TJA1024) VBAT; U100 (TJA1021) VBAT; U15 (TJA1043) VBAT; U74 (TJA1043) VBAT; U23 (TJA1081) VBAT
U17 (TJA1043) VIO; U72 (TJA1043) VIO; U18 (TJA1043) VIO; U71 (TJA1043) VIO; U16 (TJA1043) VIO; U73 (TJA1043) VIO;
U99 (TJA1463) VIO; U98 (TJA1463) VIO; U21 (TJA1463) VIO; U68 (TJA1463) VIO; U22 (TJA1463) VIO; U67 (TJA1463) VIO;
U20 (TJA1153) VIO; U69 (TJA1153) VIO; U19 (TJA1153) VIO; U70 (TJA1153) VIO;
U23 (TJA1081) VIO ; U83 (PCA85073) VDD; U46 (SJA1110) VDD33_AO;
U43 (S32G) VDD_IO_STBY;U43 (S32G) VDD_IO_B;
U43 (S32G) VDD_STBY
U43 (S32G) VDD, VDD_VP_PCIE0/1, VDD_LV_PLL_DDR0, VDD_LV_PLL, VDD_LV_PLL_AUR
U43 (S32G) VDD_IO_QSPI, VDD_DDR0 , VDD_IO_GMAC0/1;
U42 (LPDDR4) VDD1;U37 (Nor Flash) VCC,VCCQQ;
U43 (S32G) VDD_IO_SDHC
U43 (S32G) VDD_DDR_IO; U42 (LPDDR4) VDDQ, VDD2
U43 (S32G) VDD_IO_QSPI , VREFH_ADC0/1, VDD_VREF, VDD_ADC, VDD_IO_PCIE0/1,
VDD_IO_AUR, VDD_IO_CLKOUT, VDD_HV_PLL_AUR, VDD_HV_PLL_DDR0, VDD_HV_PLL,
VDD_DDR0, VDD_TMU, VDD_FXOSC, VDD_FIRC
U43 (S32G) VDD_EFUSE
U25 (MAX4886) VDD; U31 (MAX4886) VDD; U44 (MAX4886) VDD; U38 (MAX4886) VDD;
U13 (MCP6022) VDD; U11 (MCP6022) VDD; U12 (MCP6022) VDD;J48 (S32G JTAG);
U8 (USB83340) VDDIO; U3 (FT232) VCCIO; U2 (FT232) VCCIO; J57 (AURORA);
U43 (S32G) VDD_IO_USB, VDD_IO_A , VDD_IO_B ,VDD_IO_GMAC0/1 ;
U43 (S32G) VDD_IO_SDHC
U19 (TJA1153) VCC; U70 (TJA1153) VCC; U21 (TJA1463) VCC
U68 (TJA1463) VCC; U22 (TJA1463) VCC; U67 (TJA1463) VCC
J3-Pin4 (SD Card) VDD; U28 (eMMC) VCC,VCCQ; U26 (MAX4886) VDD;
U34 (MAX4886) VDD;
U23 (TJA1081) VCC; U8 (USB83340) VBAT; U3 (FT232) VCC; U2 (FT232) VCC; J5-Pin1
U15 (TJA1043) VCC; U74 (TJA1043) VCC; U17 (TJA1043) VCC; U72 (TJA1043) VCC;
U18 (TJA1043) VCC; U71 (TJA1043) VCC; U16 (TJA1043) VCC; U73 (TJA1043) VCC;
U20 (TJA1153) VCC; U69 (TJA1153) VCC; U99 (TJA1463) VCC; U98 (TJA1463) VCC;
J4-Pin1 (USB) VBUS
U59 (Si5332) VDD_DIG, VDD_XTAL, VDDA; U50 (Nor Flash) VCC;
J47 (M.2 M-Key Slot); J56 (M.2 E-Key Slot); P1 (PCIe X1 socket) +3.3V; J44-Pin1;
U46 (SJA1110) VDDA33_SGMII4,VDDA33_100BTX,VDDIO ,VDDA33_VREG_IN;
U56 (AR8035) VDD33, AVDD33; U58 (KSZ9031) AVDDH, DVDDH ; U136(INA231) VS;
U57 (AR8035) VDD33, AVDD33; U84 (KSZ9031) AVDDH, DVDDH ; U137(PCT2075) VCC;
U24 ( PCAL6524) VDD_I2C,VDD_P
U46 (SJA1110) VDD11_CORE, VDDA11_SGMII4, VDDA11_100BTX, VDDA11_100BT1,
VDDA11_OSC, VDDA11_PLL
U58 (KSZ9031) DVDDL, AVDDL, AVDDL_PLL;
U84 (KSZ9031) DVDDL, AVDDL, AVDDL_PLL;
U58 (KSZ9031) DVDDH; U28 (eMMC) VCCQ ; U37 (Nor Flash) VCC,VCCQ;
U84 (KSZ9031) DVDDH; U46 (SJA1110) VDDIO_MII2/3
U86 (AQR113C) VDD
U86 (AQR113C) VA20; V20_SRDS
U86 (AQR113C) VDD_IO; U89 (Flash) VCC
R825,R826 DNP
R824
R1147 DNP
R815
PMIC VR5510
PMIC FS5600
PMIC PF5020
Load switch
DNP or NC
S32G power supply
U86 (AQR113C) VA10; V10_SRDS
U108 ( PF5020 ) BUCK2
AQR_2V0
U41 ( VR5510 ) BUCK1 R823
A
Core current
measurement
Figure 3. The power supply block diagram of S32G-VNP-GLDBOX REV D