NXP Semiconductors Kinetis KE1xZ256 User manual

Kinetis KE1xZ256 Sub-Family
Reference Manual
Supports: MKE15Z256VLL7, MKE15Z256VLH7; MKE15Z128VLL7,
MKE15Z128VLH7; MKE14Z256VLL7, MKE14Z256VLH7;
MKE14Z128VLL7, MKE14Z128VLH7.
Document Number: KE1xZP100M72SF0RM
Rev. 3, 07/2018

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Contents
Section number Title Page
Chapter 1
About This Manual
1.1 Audience....................................................................................................................................................................... 43
1.2 Organization..................................................................................................................................................................43
1.3 Module descriptions......................................................................................................................................................43
1.3.1 Example: chip-specific information that supersedes content in the same chapter.........................................44
1.3.2 Example: chip-specific information that refers to a different chapter........................................................... 45
1.4 Register descriptions.....................................................................................................................................................46
1.5 Conventions.................................................................................................................................................................. 47
1.5.1 Numbering systems........................................................................................................................................47
1.5.2 Typographic notation..................................................................................................................................... 47
1.5.3 Special terms..................................................................................................................................................48
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................49
2.2 Block Diagram..............................................................................................................................................................49
2.3 Module Functional Categories......................................................................................................................................50
Chapter 3
Core Overview
3.1 ARM Cortex-M0+ ....................................................................................................................................................... 53
3.2 Core Buses and Interfaces.............................................................................................................................................54
3.3 Core Component Configuration....................................................................................................................................55
3.4 SysTick Clock Configuration....................................................................................................................................... 55
Chapter 4
Interrupts
4.1 Introduction...................................................................................................................................................................57
4.2 NVIC configuration...................................................................................................................................................... 57
4.2.1 Interrupt priority levels.................................................................................................................................. 57
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4.2.2 Non-maskable interrupt..................................................................................................................................58
4.3 Interrupt channel assignments.......................................................................................................................................58
4.3.1 Determining the bitfield and register location for configuring a particular interrupt.................................... 60
Chapter 5
System Integration Module (SIM)
5.1 Introduction...................................................................................................................................................................63
5.1.1 Features.......................................................................................................................................................... 63
5.2 Memory map and register definition.............................................................................................................................63
5.2.1 Chip Control register (SIM_CHIPCTL)........................................................................................................ 64
5.2.2 FTM Option Register 0 (SIM_FTMOPT0)................................................................................................... 66
5.2.3 ADC Options Register (SIM_ADCOPT)...................................................................................................... 67
5.2.4 FTM Option Register 1 (SIM_FTMOPT1)................................................................................................... 69
5.2.5 System Device Identification Register (SIM_SDID).....................................................................................71
5.2.6 Flash Configuration Register 1 (SIM_FCFG1)............................................................................................. 72
5.2.7 Flash Configuration Register 2 (SIM_FCFG2)............................................................................................. 74
5.2.8 Unique Identification Register High (SIM_UIDH)....................................................................................... 75
5.2.9 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................75
5.2.10 Unique Identification Register Mid Low (SIM_UIDML)............................................................................. 76
5.2.11 Unique Identification Register Low (SIM_UIDL)........................................................................................ 76
5.2.12 Miscellaneous Control register (SIM_MISCTRL)........................................................................................ 77
Chapter 6
Memory-Mapped Divide and Square Root (MMDVSQ)
6.1 Chip-specific Information for this Module...................................................................................................................79
6.2 Introduction...................................................................................................................................................................79
6.2.1 Features.......................................................................................................................................................... 79
6.2.2 Block diagram................................................................................................................................................80
6.2.3 Modes of operation........................................................................................................................................ 82
6.3 External signal description............................................................................................................................................83
6.4 Memory map and register definition.............................................................................................................................83
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6.4.1 Dividend Register (MMDVSQ_DEND)........................................................................................................84
6.4.2 Divisor Register (MMDVSQ_DSOR)...........................................................................................................84
6.4.3 Control/Status Register (MMDVSQ_CSR)...................................................................................................86
6.4.4 Result Register (MMDVSQ_RES)................................................................................................................ 89
6.4.5 Radicand Register (MMDVSQ_RCND)....................................................................................................... 89
6.5 Functional description...................................................................................................................................................90
6.5.1 Algorithms..................................................................................................................................................... 90
6.5.2 Execution times..............................................................................................................................................93
6.5.3 Software interface.......................................................................................................................................... 95
Chapter 7
Miscellaneous Control Module (MCM)
7.1 Chip-specific Information for this Module...................................................................................................................97
7.2 Introduction...................................................................................................................................................................98
7.2.1 Features.......................................................................................................................................................... 98
7.3 Memory map/register descriptions............................................................................................................................... 98
7.3.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................99
7.3.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 99
7.3.3 Platform Control Register (MCM_PLACR)..................................................................................................100
7.3.4 Compute Operation Control Register (MCM_CPO)..................................................................................... 103
Chapter 8
Bit Manipulation Engine (BME)
8.1 Chip-specific Information for this Module...................................................................................................................105
8.2 Introduction...................................................................................................................................................................105
8.2.1 Overview........................................................................................................................................................106
8.2.2 Features.......................................................................................................................................................... 107
8.2.3 Modes of operation........................................................................................................................................ 107
8.3 Memory map and register definition.............................................................................................................................107
8.4 Functional description...................................................................................................................................................108
8.4.1 BME decorated stores.................................................................................................................................... 108
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8.4.2 BME decorated loads.....................................................................................................................................115
8.4.3 Additional details on decorated addresses and GPIO accesses......................................................................121
8.5 Application information................................................................................................................................................122
Chapter 9
Crossbar Switch Lite (AXBS-Lite)
9.1 Chip-specific Information for this Module...................................................................................................................125
9.2 Introduction...................................................................................................................................................................126
9.2.1 Features.......................................................................................................................................................... 126
9.3 Memory Map / Register Definition...............................................................................................................................127
9.4 Functional Description..................................................................................................................................................127
9.4.1 General operation...........................................................................................................................................127
9.4.2 Arbitration......................................................................................................................................................128
9.5 Initialization/application information........................................................................................................................... 129
Chapter 10
Peripheral Bridge (AIPS-Lite)
10.1 Chip-specific information for this module....................................................................................................................131
10.1.1 Instantiation Information................................................................................................................................131
10.2 Introduction...................................................................................................................................................................132
10.2.1 Features.......................................................................................................................................................... 132
10.2.2 General operation...........................................................................................................................................133
10.3 Memory map/register definition................................................................................................................................... 133
10.4 Functional description...................................................................................................................................................133
10.4.1 Access support............................................................................................................................................... 133
Chapter 11
Trigger MUX Control (TRGMUX)
11.1 Chip-specific information for this module....................................................................................................................135
11.1.1 Module Interconnectivity...............................................................................................................................135
11.2 Introduction...................................................................................................................................................................140
11.2.1 Features.......................................................................................................................................................... 140
11.3 Functional description...................................................................................................................................................140
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11.4 Memory map and register definition.............................................................................................................................140
11.4.1 TRGMUX1 Register Descriptions.................................................................................................................140
11.4.2 TRGMUX0 Register Descriptions.................................................................................................................145
11.5 Usage Guide..................................................................................................................................................................176
11.5.1 ADC Trigger Source...................................................................................................................................... 176
11.5.2 CMP Window/Sample Input .........................................................................................................................177
11.5.3 FTM Fault Detection Input / Hardware Triggers and Synchronization.........................................................177
Chapter 12
Direct Memory Access Multiplexer (DMAMUX)
12.1 Chip-specific information for this module....................................................................................................................179
12.1.1 DMAMUX request sources........................................................................................................................... 179
12.1.2 DMA trigger sources......................................................................................................................................181
12.2 Introduction...................................................................................................................................................................181
12.2.1 Overview........................................................................................................................................................181
12.2.2 Features.......................................................................................................................................................... 182
12.2.3 Modes of operation........................................................................................................................................ 182
12.3 External signal description............................................................................................................................................183
12.4 Memory map/register definition................................................................................................................................... 183
12.4.1 Channel Configuration register (DMAMUX_CHCFGn).............................................................................. 184
12.5 Functional description...................................................................................................................................................185
12.5.1 DMA channels with periodic triggering capability........................................................................................185
12.5.2 DMA channels with no triggering capability.................................................................................................187
12.5.3 Always-enabled DMA sources...................................................................................................................... 187
12.6 Initialization/application information........................................................................................................................... 189
12.6.1 Reset...............................................................................................................................................................189
12.6.2 Enabling and configuring sources..................................................................................................................189
Chapter 13
Enhanced Direct Memory Access (eDMA)
13.1 Introduction...................................................................................................................................................................193
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13.1.1 eDMA system block diagram........................................................................................................................ 193
13.1.2 Block parts..................................................................................................................................................... 194
13.1.3 Features.......................................................................................................................................................... 195
13.2 Modes of operation....................................................................................................................................................... 196
13.3 Memory map/register definition................................................................................................................................... 197
13.3.1 TCD memory................................................................................................................................................. 197
13.3.2 TCD initialization.......................................................................................................................................... 197
13.3.3 TCD structure.................................................................................................................................................197
13.3.4 Reserved memory and bit fields.....................................................................................................................198
13.3.5 Control Register (DMA_CR).........................................................................................................................204
13.3.6 Error Status Register (DMA_ES).................................................................................................................. 207
13.3.7 Enable Request Register (DMA_ERQ)......................................................................................................... 209
13.3.8 Enable Error Interrupt Register (DMA_EEI).................................................................................................211
13.3.9 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................... 212
13.3.10 Set Enable Error Interrupt Register (DMA_SEEI)........................................................................................ 213
13.3.11 Clear Enable Request Register (DMA_CERQ).............................................................................................214
13.3.12 Set Enable Request Register (DMA_SERQ).................................................................................................215
13.3.13 Clear DONE Status Bit Register (DMA_CDNE)..........................................................................................216
13.3.14 Set START Bit Register (DMA_SSRT)........................................................................................................ 217
13.3.15 Clear Error Register (DMA_CERR)..............................................................................................................218
13.3.16 Clear Interrupt Request Register (DMA_CINT)........................................................................................... 219
13.3.17 Interrupt Request Register (DMA_INT)........................................................................................................220
13.3.18 Error Register (DMA_ERR).......................................................................................................................... 221
13.3.19 Hardware Request Status Register (DMA_HRS).......................................................................................... 223
13.3.20 Enable Asynchronous Request in Stop Register (DMA_EARS)...................................................................225
13.3.21 Channel n Priority Register (DMA_DCHPRIn)............................................................................................ 226
13.3.22 TCD Source Address (DMA_TCDn_SADDR).............................................................................................227
13.3.23 TCD Signed Source Address Offset (DMA_TCDn_SOFF)..........................................................................227
13.3.24 TCD Transfer Attributes (DMA_TCDn_ATTR)...........................................................................................228
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13.3.25 TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................... 229
13.3.26 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).........................................................................................................229
13.3.27 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES)....................................................................................................... 231
13.3.28 TCD Last Source Address Adjustment (DMA_TCDn_SLAST)...................................................................232
13.3.29 TCD Destination Address (DMA_TCDn_DADDR).....................................................................................232
13.3.30 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)..................................................................233
13.3.31 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES).............................................................................................................233
13.3.32 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO).............................................................................................................. 235
13.3.33 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)............ 236
13.3.34 TCD Control and Status (DMA_TCDn_CSR).............................................................................................. 236
13.3.35 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES).............................................................................................................239
13.3.36 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO).............................................................................................................. 240
13.4 Functional description...................................................................................................................................................241
13.4.1 eDMA basic data flow................................................................................................................................... 241
13.4.2 Fault reporting and handling..........................................................................................................................244
13.4.3 Channel preemption....................................................................................................................................... 246
13.4.4 Performance................................................................................................................................................... 246
13.5 Initialization/application information........................................................................................................................... 251
13.5.1 eDMA initialization....................................................................................................................................... 251
13.5.2 Programming errors....................................................................................................................................... 253
13.5.3 Arbitration mode considerations....................................................................................................................253
13.5.4 Performing DMA transfers............................................................................................................................ 254
13.5.5 Monitoring transfer descriptor status............................................................................................................. 258
13.5.6 Channel Linking.............................................................................................................................................260
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13.5.7 Dynamic programming.................................................................................................................................. 261
13.5.8 Suspend/resume a DMA channel with active hardware service requests......................................................264
13.6 Usage Guide..................................................................................................................................................................266
Chapter 14
Memory and memory map
14.1 Introduction...................................................................................................................................................................267
14.2 Flash memory............................................................................................................................................................... 269
14.2.1 Flash memory types....................................................................................................................................... 269
14.2.2 Flash Memory Sizes.......................................................................................................................................269
14.3 SRAM memory.............................................................................................................................................................270
14.3.1 SRAM sizes....................................................................................................................................................270
14.3.2 SRAM retention in low power modes............................................................................................................270
14.4 System memory map.....................................................................................................................................................270
14.4.1 Aliased bit-band regions................................................................................................................................ 272
14.4.2 Bit Manipulation Engine................................................................................................................................273
14.5 Peripheral memory map................................................................................................................................................273
14.5.1 Peripheral Bridge (AIPS-Lite) Memory Map................................................................................................ 274
14.6 Private Peripheral Bus (PPB) memory map..................................................................................................................277
Chapter 15
Flash Acceleration Unit (FAU)
15.1 Flash Acceleration Unit (FAU).....................................................................................................................................279
15.1.1 Introduction....................................................................................................................................................279
15.1.2 Modes of operation........................................................................................................................................ 279
15.1.3 External signal description.............................................................................................................................279
15.1.4 Memory map and register descriptions..........................................................................................................279
15.1.5 Functional description....................................................................................................................................280
15.2 Usage Guide..................................................................................................................................................................280
15.2.1 FAU Features................................................................................................................................................. 281
15.2.2 FAU Configuration........................................................................................................................................ 281
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Chapter 16
Flash Memory Module (FTFE)
16.1 Chip-specific Information for this Module...................................................................................................................283
16.2 Introduction...................................................................................................................................................................283
16.2.1 Features.......................................................................................................................................................... 284
16.2.2 Block diagram................................................................................................................................................286
16.2.3 Glossary......................................................................................................................................................... 286
16.3 External signal description............................................................................................................................................288
16.4 Memory map and registers............................................................................................................................................289
16.4.1 Flash configuration field description............................................................................................................. 289
16.4.2 Program flash 0 IFR map...............................................................................................................................289
16.4.3 Data flash 0 IFR map..................................................................................................................................... 290
16.4.4 Register descriptions......................................................................................................................................293
16.5 Functional Description..................................................................................................................................................309
16.5.1 Flash Protection..............................................................................................................................................309
16.5.2 Flash Access Protection................................................................................................................................. 311
16.5.3 FlexNVM Description....................................................................................................................................312
16.5.4 Interrupts........................................................................................................................................................ 316
16.5.5 Flash Operation in Low-Power Modes.......................................................................................................... 317
16.5.6 Flash memory reads and ignored writes........................................................................................................ 317
16.5.7 Read while write (RWW).............................................................................................................................. 317
16.5.8 Flash Program and Erase................................................................................................................................318
16.5.9 FTFE Command Operations.......................................................................................................................... 318
16.5.10 Margin Read Commands............................................................................................................................... 325
16.5.11 Flash command descriptions..........................................................................................................................326
16.5.12 Security.......................................................................................................................................................... 351
16.6 Reset Sequence............................................................................................................................................................. 354
16.7 Usage Guide..................................................................................................................................................................355
Chapter 17
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Clock Distribution
17.1 Introduction...................................................................................................................................................................357
17.2 High-Level clocking diagram....................................................................................................................................... 358
17.3 Clock definitions...........................................................................................................................................................358
17.4 Typical Clock Configuration........................................................................................................................................ 359
17.4.1 Default start-up clock.....................................................................................................................................359
17.4.2 VLPR mode clocking.....................................................................................................................................360
17.5 Clock Gating.................................................................................................................................................................360
17.6 Module clocks...............................................................................................................................................................360
17.6.1 LPO clock distribution...................................................................................................................................362
17.6.2 EWM clocks...................................................................................................................................................362
17.6.3 WDOG Clocking Information....................................................................................................................... 362
17.6.4 ADC Clocking Information........................................................................................................................... 363
17.6.5 PDB Clock Options........................................................................................................................................364
17.6.6 FTM Clocking Information............................................................................................................................364
17.6.7 LPTMR prescaler/glitch filter clocking options............................................................................................ 365
17.6.8 RTC Clocking Information............................................................................................................................ 365
17.6.9 TSI Clocking Information..............................................................................................................................366
17.6.10 Module Clocking Information for LPUART, LPSPI, LPI2C, FlexIO and LPIT...........................................366
Chapter 18
System Clock Generator (SCG)
18.1 Chip-specific information for this module....................................................................................................................369
18.1.1 Instantiation Information................................................................................................................................369
18.2 Introduction...................................................................................................................................................................372
18.2.1 Features.......................................................................................................................................................... 372
18.3 Memory Map/Register Definition.................................................................................................................................373
18.3.1 Version ID Register (SCG_VERID)..............................................................................................................374
18.3.2 Parameter Register (SCG_PARAM)............................................................................................................. 374
18.3.3 Clock Status Register (SCG_CSR)................................................................................................................375
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18.3.4 Run Clock Control Register (SCG_RCCR)...................................................................................................377
18.3.5 VLPR Clock Control Register (SCG_VCCR)...............................................................................................379
18.3.6 SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG).................................................................381
18.3.7 System OSC Control Status Register (SCG_SOSCCSR)..............................................................................382
18.3.8 System OSC Divide Register (SCG_SOSCDIV).......................................................................................... 384
18.3.9 System Oscillator Configuration Register (SCG_SOSCCFG)...................................................................... 385
18.3.10 Slow IRC Control Status Register (SCG_SIRCCSR)....................................................................................387
18.3.11 Slow IRC Divide Register (SCG_SIRCDIV)................................................................................................ 388
18.3.12 Slow IRC Configuration Register (SCG_SIRCCFG)....................................................................................389
18.3.13 Fast IRC Control Status Register (SCG_FIRCCSR)..................................................................................... 390
18.3.14 Fast IRC Divide Register (SCG_FIRCDIV)..................................................................................................392
18.3.15 Fast IRC Configuration Register (SCG_FIRCCFG)..................................................................................... 393
18.3.16 Fast IRC Trim Configuration Register (SCG_FIRCTCFG)..........................................................................394
18.3.17 Fast IRC Status Register (SCG_FIRCSTAT)................................................................................................395
18.3.18 Low Power FLL Control Status Register (SCG_LPFLLCSR)......................................................................396
18.3.19 Low Power FLL Divide Register (SCG_LPFLLDIV).................................................................................. 398
18.3.20 Low Power FLL Configuration Register (SCG_LPFLLCFG)...................................................................... 399
18.3.21 Low Power FLL Trim Configuration Register (SCG_LPFLLTCFG)...........................................................400
18.3.22 Low Power FLL Status Register (SCG_LPFLLSTAT).................................................................................401
18.4 Functional description...................................................................................................................................................402
18.4.1 SCG Clock Mode Transitions........................................................................................................................402
Chapter 19
RTC Oscillator (OSC32)
19.1 Introduction...................................................................................................................................................................405
19.1.1 Features and Modes....................................................................................................................................... 405
19.1.2 Block Diagram............................................................................................................................................... 405
19.2 RTC Signal Descriptions.............................................................................................................................................. 406
19.2.1 EXTAL32 — Oscillator Input....................................................................................................................... 406
19.2.2 XTAL32 — Oscillator Output....................................................................................................................... 406
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19.3 External Crystal Connections....................................................................................................................................... 407
19.4 Memory Map/Register Descriptions.............................................................................................................................407
19.4.1 RTC Oscillator Control Register (OSC32_CR).............................................................................................407
19.5 Functional Description..................................................................................................................................................408
19.6 Reset Overview.............................................................................................................................................................409
19.7 Interrupts.......................................................................................................................................................................409
Chapter 20
Peripheral Clock Controller (PCC)
20.1 Chip-specific information for this module....................................................................................................................411
20.1.1 Information of PCC on this device................................................................................................................ 411
20.2 Introduction...................................................................................................................................................................411
20.2.1 Features.......................................................................................................................................................... 411
20.3 Functional description...................................................................................................................................................412
20.4 Memory map and register definition.............................................................................................................................413
20.4.1 PCC Register Descriptions.............................................................................................................................413
Chapter 21
Reset and Boot
21.1 Introduction...................................................................................................................................................................459
21.2 Reset..............................................................................................................................................................................460
21.2.1 Power-on reset (POR).................................................................................................................................... 460
21.2.2 System resets..................................................................................................................................................460
21.2.3 MCU Resets................................................................................................................................................... 463
21.2.4 Reset Pin ....................................................................................................................................................... 464
21.3 Boot...............................................................................................................................................................................464
21.3.1 Boot options................................................................................................................................................... 465
21.3.2 Boot sequence................................................................................................................................................ 466
Chapter 22
Kinetis ROM Bootloader
22.1 Chip-specific information for this module....................................................................................................................469
22.1.1 Boot ROM Configuration.............................................................................................................................. 469
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22.2 Introduction...................................................................................................................................................................470
22.3 Functional Description..................................................................................................................................................471
22.3.1 Memory Maps................................................................................................................................................471
22.3.2 The Kinetis Bootloader Configuration Area (BCA)......................................................................................472
22.3.3 Start-up Process..............................................................................................................................................474
22.3.4 Clock Configuration.......................................................................................................................................476
22.3.5 Bootloader Entry Point / API Tree.................................................................................................................477
22.3.6 Bootloader Protocol....................................................................................................................................... 478
22.3.7 Bootloader Packet Types............................................................................................................................... 481
22.3.8 Bootloader Command API.............................................................................................................................487
22.3.9 Bootloader Exit state......................................................................................................................................500
22.4 Kinetis Flash Driver API.............................................................................................................................................. 500
22.4.1 Flash Driver Entry Point................................................................................................................................ 500
22.4.2 Flash driver API Tree.....................................................................................................................................501
22.4.3 Quick demo using Kinetis Flash Driver API................................................................................................. 502
22.4.4 Flash driver data structures............................................................................................................................ 503
22.4.5 Flash driver API.............................................................................................................................................504
22.5 Peripherals Supported................................................................................................................................................... 518
22.5.1 I2C Peripheral................................................................................................................................................ 518
22.5.2 SPI Peripheral................................................................................................................................................ 520
22.5.3 UART Peripheral........................................................................................................................................... 523
22.6 Get/SetProperty Command Properties..........................................................................................................................525
22.6.1 Property Definitions.......................................................................................................................................527
22.7 Kinetis Bootloader Status Error Codes.........................................................................................................................528
Chapter 23
Reset Control Module (RCM)
23.1 Chip-specific information for this module....................................................................................................................531
23.1.1 Instantiation Information................................................................................................................................531
23.2 Introduction...................................................................................................................................................................531
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23.3 Reset memory map and register descriptions............................................................................................................... 532
23.3.1 Version ID Register (RCM_VERID).............................................................................................................532
23.3.2 Parameter Register (RCM_PARAM)............................................................................................................ 534
23.3.3 System Reset Status Register (RCM_SRS)................................................................................................... 536
23.3.4 Reset Pin Control register (RCM_RPC)........................................................................................................ 539
23.3.5 Mode Register (RCM_MR)........................................................................................................................... 540
23.3.6 Force Mode Register (RCM_FM)..................................................................................................................541
23.3.7 Sticky System Reset Status Register (RCM_SSRS)......................................................................................542
23.3.8 System Reset Interrupt Enable Register (RCM_SRIE)................................................................................. 544
Chapter 24
Power Management
24.1 Introduction...................................................................................................................................................................547
24.2 Power Modes Description.............................................................................................................................................548
24.2.1 Run mode....................................................................................................................................................... 549
24.2.2 Wait mode......................................................................................................................................................550
24.2.3 Stop mode...................................................................................................................................................... 551
24.2.4 Power domains...............................................................................................................................................553
24.2.5 Entering and exiting power modes.................................................................................................................554
24.3 Power mode transitions.................................................................................................................................................554
24.4 Power modes shutdown sequencing............................................................................................................................. 555
24.5 Module operation in low power modes........................................................................................................................ 556
24.5.1 Peripheral doze...............................................................................................................................................559
24.6 Low-power wake-up sources........................................................................................................................................ 560
24.7 Power supply supervisor...............................................................................................................................................560
Chapter 25
System Mode Controller (SMC)
25.1 Introduction...................................................................................................................................................................563
25.2 Modes of operation....................................................................................................................................................... 563
25.3 Memory map and register descriptions.........................................................................................................................565
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25.3.1 SMC Version ID Register (SMC_VERID)....................................................................................................565
25.3.2 SMC Parameter Register (SMC_PARAM)................................................................................................... 566
25.3.3 Power Mode Protection register (SMC_PMPROT).......................................................................................567
25.3.4 Power Mode Control register (SMC_PMCTRL)...........................................................................................569
25.3.5 Stop Control Register (SMC_STOPCTRL)...................................................................................................570
25.3.6 Power Mode Status register (SMC_PMSTAT)............................................................................................. 572
25.4 Functional description...................................................................................................................................................572
25.4.1 Power mode transitions..................................................................................................................................572
25.4.2 Power mode entry/exit sequencing................................................................................................................ 574
25.4.3 Run modes......................................................................................................................................................576
25.4.4 Wait modes.................................................................................................................................................... 578
25.4.5 Stop modes.....................................................................................................................................................579
25.4.6 Debug in low power modes........................................................................................................................... 580
Chapter 26
Power Management Controller (PMC)
26.1 Chip-specific Information for this Module...................................................................................................................581
26.2 Introduction...................................................................................................................................................................581
26.3 Features.........................................................................................................................................................................581
26.4 Modes of Operation...................................................................................................................................................... 581
26.4.1 Full Performance Mode (FPM)......................................................................................................................581
26.4.2 Low Power Mode (LPM)...............................................................................................................................582
26.5 Low Voltage Detect (LVD) System............................................................................................................................. 582
26.5.1 Low Voltage Reset (LVR) Operation............................................................................................................ 582
26.5.2 LVD Interrupt Operation............................................................................................................................... 583
26.5.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 583
26.6 Memory Map and Register Definition..........................................................................................................................583
26.6.1 Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)..........................................................584
26.6.2 Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)..........................................................585
26.6.3 Regulator Status and Control Register (PMC_REGSC)................................................................................586
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Section number Title Page
26.6.4 Low Power Oscillator Trim Register (PMC_LPOTRIM)............................................................................. 587
Chapter 27
Security
27.1 Introduction...................................................................................................................................................................589
27.2 Flash security feature summary.................................................................................................................................... 589
27.2.1 Flash security byte......................................................................................................................................... 589
27.2.2 Flash access protection (FAC)....................................................................................................................... 590
27.3 Security hardware accelerators..................................................................................................................................... 590
27.3.1 CRC................................................................................................................................................................590
27.4 General security features...............................................................................................................................................591
27.4.1 Unique ID.......................................................................................................................................................591
27.4.2 Program Once Field....................................................................................................................................... 591
Chapter 28
External Watchdog Monitor (EWM)
28.1 Introduction...................................................................................................................................................................593
28.1.1 Features.......................................................................................................................................................... 593
28.1.2 Modes of Operation....................................................................................................................................... 594
28.1.3 Block Diagram............................................................................................................................................... 595
28.2 EWM Signal Descriptions............................................................................................................................................ 596
28.3 Memory Map/Register Definition.................................................................................................................................596
28.3.1 Control Register (EWM_CTRL)................................................................................................................... 596
28.3.2 Service Register (EWM_SERV)....................................................................................................................597
28.3.3 Compare Low Register (EWM_CMPL)........................................................................................................597
28.3.4 Compare High Register (EWM_CMPH).......................................................................................................598
28.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)..................................................................................599
28.4 Functional Description..................................................................................................................................................599
28.4.1 The EWM_out Signal.................................................................................................................................... 599
28.4.2 The EWM_in Signal...................................................................................................................................... 600
28.4.3 EWM Counter................................................................................................................................................601
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Section number Title Page
28.4.4 EWM Compare Registers.............................................................................................................................. 601
28.4.5 EWM Refresh Mechanism.............................................................................................................................601
28.4.6 EWM Interrupt...............................................................................................................................................602
28.4.7 Counter clock prescaler..................................................................................................................................602
28.5 Usage Guide..................................................................................................................................................................602
28.5.1 EWM low-power modes................................................................................................................................ 602
28.5.2 EWM_out pin state in low power modes.......................................................................................................603
28.5.3 Example code.................................................................................................................................................603
Chapter 29
Watchdog timer (WDOG)
29.1 Chip-specific information for this module....................................................................................................................605
29.1.1 WDOG Clocking Information....................................................................................................................... 605
29.1.2 WDOG low-power modes............................................................................................................................. 605
29.2 Introduction...................................................................................................................................................................606
29.2.1 Features.......................................................................................................................................................... 606
29.2.2 Block diagram................................................................................................................................................607
29.3 Memory map and register definition.............................................................................................................................607
29.3.1 Watchdog Control and Status Register (WDOG_CS)................................................................................... 608
29.3.2 Watchdog Counter Register (WDOG_CNT).................................................................................................611
29.3.3 Watchdog Timeout Value Register (WDOG_TOVAL)................................................................................ 611
29.3.4 Watchdog Window Register (WDOG_WIN)................................................................................................612
29.4 Functional description...................................................................................................................................................613
29.4.1 Clock source...................................................................................................................................................613
29.4.2 Watchdog refresh mechanism........................................................................................................................614
29.4.3 Configuring the Watchdog.............................................................................................................................616
29.4.4 Using interrupts to delay resets......................................................................................................................617
29.4.5 Backup reset...................................................................................................................................................617
29.4.6 Functionality in debug and low-power modes...............................................................................................618
29.4.7 Fast testing of the watchdog...........................................................................................................................618
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Section number Title Page
29.5 Application Information................................................................................................................................................619
29.5.1 Disable Watchdog..........................................................................................................................................620
29.5.2 Configure Watchdog......................................................................................................................................620
29.5.3 Refreshing the Watchdog...............................................................................................................................621
Chapter 30
Cyclic Redundancy Check (CRC)
30.1 Introduction...................................................................................................................................................................623
30.1.1 Features.......................................................................................................................................................... 623
30.1.2 Block diagram................................................................................................................................................623
30.1.3 Modes of operation........................................................................................................................................ 624
30.2 Memory map and register descriptions.........................................................................................................................624
30.2.1 CRC Data register (CRC_DATA)................................................................................................................. 625
30.2.2 CRC Polynomial register (CRC_GPOLY).................................................................................................... 626
30.2.3 CRC Control register (CRC_CTRL)..............................................................................................................626
30.3 Functional description...................................................................................................................................................627
30.3.1 CRC initialization/reinitialization..................................................................................................................627
30.3.2 CRC calculations............................................................................................................................................628
30.3.3 Transpose feature........................................................................................................................................... 629
30.3.4 CRC result complement.................................................................................................................................631
30.4 Usage Guide..................................................................................................................................................................631
30.4.1 32-bit POSIX CRC.........................................................................................................................................632
30.4.2 16-bit KERMIT CRC.....................................................................................................................................633
Chapter 31
Debug
31.1 Introduction...................................................................................................................................................................635
31.2 Debug port pin descriptions..........................................................................................................................................635
31.3 SWD status and control registers..................................................................................................................................635
31.3.1 MDM-AP status register................................................................................................................................ 637
31.3.2 MDM-AP Control register.............................................................................................................................638
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