NXP Semiconductors S32R27 Guide

1 Introduction
The S32R is a 32-bit heterogeneous multi-core microcontroller
family primarily intended for use in computationally intensive
automotive RADAR applications. The device family
incorporates Power Architecture®cores arranged as two
independent e200z7260 for general computation and the
S32R274 device also features an e200z420 core with an
e200z419 checker core running in delayed lockstep
configuration for safety-critical and housekeeping tasks. The
family integrates high-performance signal processing features
designed to support sophisticated automotive RADAR
applications, and the S32R274 also integrates high accuracy
analog features to further enhance it's ability to interface with
a wide range of RADAR RF devices.
This application note illustrates the S32R family power supply
options and details the external circuitry required for power
supplies, oscillator connections, and supply decoupling pins. It
also discusses configuration options for clock, reset, ADC
modules and the RADAR analog front-end, as well as
recommended debug and peripheral communication
connections (including MIPI-CSI2) and other major external
hardware required for the device.
The S32R family requires multiple external power supplies to
operate. The main cores internal logic requires a 1.25 V power
supply. This can be supplied from an external source or on
some devices this can alternatively be provided by an internal
DC-DC regulator that requires a dedicated supply. 3.3 V is
NXP Semiconductors Document Number: AN5251
Application Note Rev. 1, 04/2018
S32R27/37 Hardware Design Guide
by: NXP Semiconductors
Contents
1 Introduction.............................. .............................. 1
2 S32R family package options
overview..................................................................2
3 Power supply...........................................................3
4 Clock configuration...............................................15
5 Device reset configuration............... .....................17
6 Recommended debug connectors and
connector pin-out definitions.................... ............ 18
7 ADC overview........................... ........................... 22
8 RADAR analog front end..................................... 23
9 Example communication peripheral
connections.......................................... ................. 29
10 High speed layout considerations..........................48
A Revision History................................................... 49

required for the general purpose I/O, flash memory, analog front-end, external communications interfaces, and on-chip SAR
analog to digital converter.
2 S32R family package options overview
The S32R family is available in multiple device and package options that are suited to development, debug and commercial
production.
Table 1. S32R package description
Device Package Description
S32R274 257 Map ball grid array (MAPBGA) Full support for all device modules and features
including JTAG and Nexus High Speed Aurora Trace
debug interfaces.
S32R372 257 Map ball grid array (MAPBGA) Full support for all device modules and features
including JTAG and Nexus High Speed Aurora Trace
debug interfaces. Pin compatible with S32R274,
although with reduced feature set. See Table 3 below
for details.
S32R372 141 Map ball grid array (MAPBGA) Reduced support for some device modules and
features. See Table 3 for details of reduced features
The table below shows the physical dimensions of the packages. See the device data sheet for complete package dimensions
and ball placement. Drawings are also available on nxp.com, search for the case outline number shown in Table 2.
Table 2. Package sizes
Device Package Physical Size Case Outline Number Pitch
S32R274 257 MAPBGA 14 x 14 mm 98ASA00081D 0.8 mm
S32R372 257 MAPBGA 14 x 14 mm 98ASA00081D 0.8 mm
S32R372 141 MAPBGA 10 x 10 mm 84ASA00768D 0.65 mm
The table below shows the main differences between the S32R family, including the different available packages. This list
only references the differences that have a hardware impact. For full details of all differences between the various devices
please see the relevant device reference manuals.
Table 3. Feature Differences Between Packages
Feature S32R274 S32R372 257 MAPBGA S32R372 141 MAPBGA
SD-ADC 4x SD-ADC None None
DAC Yes None None
MIPI CSI2 4 Lanes + Clock 2 Lanes + Clock 2 Lanes + Clock
Ethernet Yes, up to RGMII interface. None None
Wave Generator Module
(WGM)
Yes None None
LINFlexD Yes, 1 module Yes, 1 module None
FlexPWM 1 module, 12 channels 1 module, 12 channels 1 module, 11 channels
Table continues on the next page...
S32R family package options overview
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Table 3. Feature Differences Between Packages (continued)
Feature S32R274 S32R372 257 MAPBGA S32R372 141 MAPBGA
SPI 2 modules 2 modules 2 modules, some chip selects not
available. See device muxing
sheet for details.
IIC 2 modules 2 modules 1 module (IIC1 only).
Serial Inter-Processor
Interface (SIPI)
Yes None None
System Timer Module
(STM)
3 modules x 4 channels 2 modules x 4 channels 2 modules x 4 channels
System Timer Module
(STM)
eTimer_0: 6 channels,
eTimer_1: 6 channels
eTimer_1:6 channels eTimer_1:5 channels
FlexRay 1 module None None
FlexCAN 1x FlexCAN, 2x FlexCAN-
FD
2x FlexCAN-FD 2x FlexCAN-FD
Device Power Supply Internal or External
regulation modes
Internal or External regulation
modes
External regulation mode only
3 Power supply
The S32R family of microcontroller units have a robust power management infrastructure that enables applications to select
among various user modes and to monitor internal voltages for high- and low-voltage conditions. The monitoring capability
is also used to ensure supply voltages and internal voltages are within the required operating ranges before the
microcontroller can exit the reset state and enter operation.
The microcontroller offers a DC-DC voltage regulator function as part of the power management controller (PMC) module. 1
This regulator can be used to supply the digital low voltage required for the internal logic and other low voltage supplies. The
device can be configured to use either this internal regulation mode or an external 1.25 V regulated power supply to provide
the core voltage. The standard configuration utilizes the internal DC-DC voltage regulator, with the following external supply
voltages:
• 3.3 V for main general purpose I/O, SAR ADC supply and reference, JTAG debug interface, flash memory supply
voltage and external communication interfaces (Ethernet, FlexRay, etc.)
• 3.13 - 5.5 V (required) for the internal DC-DC voltage regulator which supplies 1.25 V for the internal logic, PLL
circuits and low voltage/Nexus Aurora I/O, and MIPI-CSI2.
Detailed information on the power management configurations can be found in the Power management controller section.
1. Not available on the S32R372 141BGA Package.
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3.1 Power supply signals and decoupling
Table 4 lists all MCU power domains with corresponding pin names. Depending on the power management configuration,
some of the supplies below may not require an external power source. The power management configuration is detailed in
Power management controller.
Table 4. MCU power supply pins
Domain name Supply
Voltage
Description
VDD_LV_CORE 1.25 V Low-voltage supply for core logic
VDD_HV_IOx 3.3 V High-voltage supply for general purpose I/O
VDD_HV_RAW 3.3 V High-voltage, high fidelity supply for analog front-end block
VDD_HV_DAC 13.3 V High-voltage supply for DAC module in analog front-end
VDD_HV_ADC 3.3 V Voltage supply for SAR ADC module
VDD_HV_ADCREF0/2 23.3 V Voltage reference for SAR ADC 0/2
VDD_HV_FLA 3.3 V Voltage supply for flash memory
VDD_HV_PMU 3.3 V Voltage supply for power management unit
VDD_HV_IO_PWM 13.3 V Voltage supply for PWM IO
VDD_HV_REG3V8 13.13 V - 5.5 V3Voltage supply for internal DC-DC voltage regulator
VDD_LV_LFASTPLL41.25 V Voltage supply for DigiRF (SIPI/LFAST) PLL
VDD_LV_IO_AURORA51.25 V Voltage supply for Nexus Aurora I/O
VDD_LV_PLL0 1.25 V Voltage supply for system PLL
VDD_LV_IO 1.25 V Low voltage supply for general purpose I/O
VDD_LV_DPHY61.25 V Low voltage supply for MIPI-CSI2 DHPY
1. Not present on S32R372 141MAPBGA Package
2. To ensure optimum SAR ADC performance it is recommended to have a ground plane below the VDD_HV_ADCREF0/2
traces.
3. Internal regulation mode. When using external regulation mode, this domain can be tied to VDD_HV_PMU
4. The naming convention VDD_LV_LFASTPLL is equal to VDD_LV_DRFPLL. Not present on S32R372 141MAPBGA
Package
5. VDD_LV_IO_AURORA must be connected to the same voltage supply as VDD_LV_CORE. The supplies must be brought
up simultaneously.
6. Can be supplied from VDD_LV_CORE supply with filtering as recommended below.
Some of the supplies can be powered with different supply voltages. The internal voltage regulator supply,
VDD_HV_REG3V8, can be supplied with a voltage between 3.13 V and 5.5 V. See the device data sheet for specific
information and to learn what voltage ranges can be safely connected to the power pins.
Table 5 shows all power domains and the suggested decoupling and/or filter capacitors for their corresponding pins. These
values are provided as a guideline and will vary depending on the application and capability of the power supplies used.
The decoupling capacitors must be placed as close as possible to the MCU supply pins, with priority given to those with the
smallest capacitance value.
Table 5. Supply pin decoupling capacitors
Domain name Supply
Voltage
Minimum Decoupling Capacitors
VDD _LV_CORE 1.25 V 0.1 μF x 16, 4.7 μF x 4, 10 μF x 2 (40 μF total)1
VDD_HV_IOx 3.3 V 2 x 0.1 μF for each VDD_HV_IO supply2
Table continues on the next page...
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Table 5. Supply pin decoupling capacitors (continued)
Domain name Supply
Voltage
Minimum Decoupling Capacitors
VDD_HV_RAW 3.3 V 0.1 μF, 1 μF
VDD_HV_DAC 33.3 V 1000 pF, 0.1 μF, 1 μF
VDD_HV_ADC 3.3 V 0.1 μF, 1 μF
VDD_HV_ADCREF0/2 3.3 V 0.01 μF, 1 μF
VDD_HV_IO_PWM 33.3 V 2x 0.1 μF for each supply
VDD_HV_FLA 3.3 V 0.1 μF, 1000 pF
VDD_HV_PMU 3.3 V 100 nF, 4.7 μF
VDD_HV_REG3V8 33.13 V - 5.5
V
1 μF Ceramic4
VDD_LV_DRFPLL 31.25 V 1000 pF, 0.1 μF, 1 μF, 0.01 μF
VDD_LV_IO_AURORA 1.25 V 0.1 μF, 1 μF
VDD_LV_PLL0 1.25 V 1000 pF, 0.1 μF, 1μF, 0.01 μF
VDD_LV_DPHY 1.25 V Ferrite bead, >5 μF, 100 nF, 1000 pF
1. When using internal regulation mode, assure that the total capacitance (accounting for temperature variations) never falls
below 40 μF
2. External capacitors for the IO pins are dependent on the application.
3. Not present on S32R372 141BGA Package
4. When device is configured in external regulation mode and supply is connected to VDD_HV_PMU. For internal regulation
mode see SMPS external component configuration
The device has several pins for the connection to external decoupling capacitors for the analog front-end. Details of these can
be found in RADAR analog front end
3.2 Decoupling capacitors layout priority
When trade-offs must be made in the schematic layout, it is important to ensure that the highest priority supplies have
decoupling capacitors placed as closely as possible to the MCU. The list below outlines the recommended order of the
supplies from highest to lowest priority in terms of their importance for decoupling.
1. VDD_HV_RAW & VDD_HV_DAC
2. VDD_HV_ADCREF0/2
3. VDD_HV_ADC
4. VDD_LV_PLL0
5. VDD_LV_DPHY
6. VDD_LV_CORE
7. VDD_LV_AURORA
8. VDD_HV_PMU
9. VDD_HV_FLA
10. VDD_LV_LFASTPLL2
11. VDD_LV_IO
12. VDD_HV_PWM3
13. VDD_HV_IO
2. Not present on S32R372 141MAPBGA Package
3. Not present on S32R372 141MAPBGA Package
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Highest priority is given to the high-fidelity analog front end supplies VDD_HV_RAW and VDD_HV_DAC, as their
decoupling must be prioritized to maintain analog signal integrity. VDD_HV_ADRREF0, VDD_HV_ADREF1, and
VDD_HV_ADC is the SAR analog-to-digital converters reference and power supply decoupling. Clean supplies are vital to
ensure that the highest accuracy is achieved with the ADCs. The supply for the system PLL is prioritized as this helps to
ensure reliable and stable operation from the internal PLL circuit.
Medium priority is given to VDD_LV_CORE, VDD_LV_DRFPLL, VDD_LV_AURORA, VDD_HV_PMU,
VDD_LV_DPHY and VDD_HV_FLA. VDD_LV_CORE is the main supply for the on-chip digital logic and this is
prioritized as it affects the largest amount of logic on the device. VDD_LV_AURORA powers the high speed Nexus Aurora
pins and noise on this domain would affect the quality of the output. VDD_HV_PMU is the power management unit supply
and VDD_LV_DPHY is the MIPI-CSI2 DPHY supply. The MIPI-CSI2 DPHY is a high speed module which requires
minimal noise in order to acheive the specified performance levels. VDD_HV_FLA is the input supply for the flash memory.
A good supply to the flash memory ensures reliable flash programming and erasing.
VDD_LV_LFASTPLL powers the PLL for the LFAST/SIPI communication interface. 4VDD_HV_IO, VDD_HV_PWM,
and VDD_LV_IO drive GPIO and other external communication interfaces. Although it is still important that these supplies
have a clean power signal, the hardware they power is less affected by noise and they are considered of lower priority.
When completing the layout of decoupling capacitors care should be taken to reduce the volume of the space in the
transmission line between the device and the capacitor, which results in faster response to energy requests from the device.
The capacitor should always be the closest to the device so that the energy comes from the capacitor and not from the power
trace, as illustrated in the figure below.
Figure 1. Decoupling capacitor placement recommendation
3.3 Power management controller
The S32R family has a dedicated module for configuration and monitoring of power supplies, enable signals, internal
component trimming, and power-on reset generation. The Power Management Controller (PMC) consists of an analog block
and a supporting digital interface that provides control over the analog components. The PMC chapter in the device reference
manual explores the digital block in depth.
4. This interface is not present on the S32R372 device, but the supply name remains the same for the 257MAPBGA
package to avoid confusion, and is not present on the 141MAPBGA package.
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NOTE
This document will focus on the external hardware and connections concerned with the
PMC analog block.
3.3.1 Core supply options
The S32R family offers two options for supplying the 1.25 V used by the core and other low-voltage digital power domains.
• Internal voltage regulation mode, using the integrated DC-DC voltage regulator (VREG)5
• External voltage regulation mode using an externally regulated 1.25 V supply
The input pin VREG_SEL allows selection between internal and external regulation modes, the function of this input is
described in the table below.6
Table 6. VREG_SEL input signal
Input Level Core Supply Mode
High (3.3 V) Internal regulation mode
Low (GND) External regulation mode
The PMC has an internal voltage regulator function that uses a switched-mode power supply (SMPS) circuit to supply the
1.25 V required by the internal core logic, VDD_LV_CORE and the other low-voltage digital supplies
(VDD_LV_AURORA, VDD_LV_PLL0, VDD_LV_DPHY and VDD_LV_IO). The regulator requires the support of
external circuitry detailed in SMPS external component configuration. This configuration is an asynchronous buck regulator
with nominal switching frequency of 1 MHz. The switching frequency may be modulated to improve the EMI performance
of the device, further information on this feature can be found in the PMC chapter in the device reference manual.
VREG_SEL is part of a collection of I/O signals that relate to the VREG operation mode. The other pins are mentioned in the
table below.
Table 7. PMC Voltage regulator signals
Signal Name Direction VREG Enabled (Internal Mode) VREG Disabled (External Mode)
VREG_POR_B Input External power-on reset. If not used it is
recommended to be externally pulled up
to 3.3 V, but can be left floating.
Internally pulled up to 3.3 V.
Power-on reset (POR) input. Used by
external circuitry to trigger a POR or hold
device in reset state. Should be used to
hold device in reset until supplies are
within the ranges described in the device
data sheet.
VREG_ISENS1Input Current sense input to internal regulator Not used. Connect to VDD_LV_CORE
VREG_SWP1Output Output from internal VREG. Controls the
gate of the external switching PMOS
transistor 2
Not used, can be left floating. Internally
pulled up, do not connect to GND.
1. Not present on S32R372 141MAPBGA package.
2. If the connection between VREG_SWP and the PMOS gate is broken, the switch may fully turn on. For added protection
against this risk, a 100 Kilo Ohm resistor can be connected between VDD_HV_REG3V8 and the PMOS gate.
5. Not supported on S32R372 141MAPBGA package.
6. VREG_SEL pad is internally bonded to GND on S32R372 141MAPBGA package.
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3.3.2 Internal voltage regulator supply mode
The standard device configuration for the S32R family 257 MAPBGA packages uses the internal DC-DC voltage regulator to
supply the core voltage and other low-voltage digital supplies. Figure 2 shows all the power supply connections required
when operating in internal voltage regulation mode and also provides guidelines on how to structure the power nets. Values
for the decoupling capacitors shown in the figure are listed in Table 5.
DC-DC
VReg
Board supply 5V -12V
DC-DC
VReg
SWP
SAR ADC
3.3V
low noise
POR
Lin.
VReg
3.3V
low noise
Lin.
VReg Lin.
VReg
POR_B
DC-DC
VReg
AFE
Internal Lin. VRegs
3.3V
low noise
HV_PMU
3.3V
HV_REG_3V8
3.13V - 5.5V
LV_DRFPLL
LV_PLL0
LFAST
PLL
System
PLL
HV_ADCREF0/2
HV_ADC
1.25V
HV_DAC
HV_RAW
LV_IO_AURORA
NEXUS
AURORA
See "SMPS
External
Component
Configuration"
LV_DPHY
MIPI
CSI2
HV_FLA
HV_IOx
ISENS
LV_CORE
1.25V, 1.8A
HV_IO_PWM
Figure 2. Supply connections
The internal regulator requires a dedicated 3.13 V - 5.5 V supply alongside the 3.3 V PMC supply to generate the 1.25 V
digital low voltage. The support of an external PMOS switch circuit is also required, details are given in SMPS external
component configuration. The analog front-end (AFE) requires high-fidelity supplies and careful decoupling to support its
sensitive analog functionality, covered in RADAR analog front end.
Internal regulation mode is enabled by driving the VREG_SEL input high and has the following attributes.
• The PMC internal power-on-reset (POR) and low-voltage/high-voltage detect (LVD/HVD) circuits are enabled by
default.
• The internal POR will keep the device in reset until all the monitored supplies have reached their minimum operation
threshold.
• The internal POR function means that the external POR pin VREG_POR_B is not needed. As such, it is internally
pulled up to the PMC supply voltage. It can be left floating or alternatively connected to 3.3 V.
• VREG_POR_B remains active in internal regulation mode, even though POR is managed internally. If pulled low it
will cause a power-on reset regardless of voltage regulation mode.7
• The internal LVD/HVD circuits are by default enabled to ensure the expected boot-up sequence occurs. More
information on the LVDs/HVDs is available in Low-Voltage (LVD) and High-Voltage Detection (HVD).
• Use a single Linear VREG to supply both VDD_HV_RAW and VDD_HV_DAC. Both supply pins must have the
recommended filtering as described in Table 5 and have separate routes (star route) of roughly equal length to the
Linear VREG.
• Either ramp VDD_HV_IO and VDD_HV_PMC together or ramp VDD_HV_IO before VDD_HV_PMC such that the
two supplies always maintain 100 mV or less difference when using internal regulation mode.
• VDD_HV_IO, VDD_HV_IO_RGMII, VDD_HV_IO_PWM and VDD_HV_IO_LFAST supplies should be treated as a
single supply from a board perspective.
7. VREG_POR_B can be used in internal regulation mode to ensure that the POR sequence is only started when main
power supply reaches a stable regulation point. This can assist in cases where the power supply reaches the
minimum LVD threshold but then drops below the threshold again when loaded, before reaching a stable regulation
point.
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3.3.3 SMPS external component configuration
When operating in internal voltage regulation mode, an SMPS circuit is required along with the support of external
components in order to minimize noise and maintain a stable supply to guarantee device performance. Special care must be
taken so that the switched regulator does not introduce noise into high-fidelity analog components. The external component
layout is shown in Figure 3.
Figure 3. SMPS external components layout
Table 8 provides recommended values for the external components.
Table 8. External component values
Component Label Recommended Value
M1 SI3443, 2SQ2315
L1 2.2 μH 3A <100 mΩ series resistance (E.g. Bourns SRU8043-2R2Y)
D1 SS8P3L 8A Schottcky diode
R1 24 kΩ
C1 10 μF ceramic
Table continues on the next page...
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Table 8. External component values (continued)
Component Label Recommended Value
C2 100 nF ceramic
C3 100 nF ceramic (place close to inductor)
C4 10 μF ceramic (place close to inductor)
C5 1 nF ceramic
C6 4x 100 nF + 4x 10 nF ceramic (place close to MCU supply pins)
C7 4x 10 μF ceramic (place close to MCU supply pins)1
C8 100 nF ceramic (place close to MCU supply pins)
C9 1 μF ceramic (place close to MCU supply pins)
1. These are the same capacitors as those listed for VDD_LV_CORE in Table 2
For optimum electro-magnetic interference (EMI) performance, it is critical that the inner and outer loops shown in Figure 3
overlap on the PCB and are made as short as possible. It is highly recommended to have a section of the PCB ground plane
dedicated to making a good connection between the grounds of C1/C2 and C3/C4. This measure will help to ensure that the
loops are made as short as possible.
The role of C1/C2 is to guarantee a low input impedance to the buck converter. In a similar manner, C3/C4 make the
impedance low at the buck converter output. This measure helps reduce the high frequency content of the current passing
through the highlighted branch 'Iload', making it less critical that the buck converter components be placed close to the
VDD/VSS pins of the MCU. However, it is important that capacitors C6 and C7 are placed as closely as possible to the
VDD/VSS pins of the MCU, as they guarantee the low impedance of the core MCU supply and also help to reduce the high
frequency content of the 'Iload' path.
The gate-driver circuitry also forms important current loops that must be minimized (not shown in Figure 3). For that
purpose, C8/C9 must be placed as close as possible to the gate-driver supply pins. The ground connections for C8/C9 must be
made as short as possible to C1/C2. When the PMOS switch is turned on, the high-frequency current that charges the gate
comes from C1/C2, passing through the PMOS gate into the gate-driver pin. That current is carried to the gate-driver VSS pin
returning to C1/C2. This current loop must be made as small as possible.
Conversely, when the PMOS switch is turned off, high-frequency currents enter in the PMOS gate coming from the gate-
driver pin and flows into C1/C2, returning through the ground into C8/C9 and then into the gate-driver supply pin.
Minimizing this second loop area is as critical as the first.
To shield nearby nets from the gate-driver generated noise, it is also recommended that the gate-driver supply pins are used
to shield the VREG_SWP net until it reaches the PMOS switch. Nets on other PCB layer should avoid running parallel to this
net.
The figure below is a circuit schematic showing an example SMPS circuit derived from the above guidelines. For best
performance, use the component values recommended in Table 8.
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