NXP Semiconductors S32R27 Guide

1 Introduction
The S32R is a 32-bit heterogeneous multi-core microcontroller
family primarily intended for use in computationally intensive
automotive RADAR applications. The device family
incorporates Power Architecture®cores arranged as two
independent e200z7260 for general computation and the
S32R274 device also features an e200z420 core with an
e200z419 checker core running in delayed lockstep
configuration for safety-critical and housekeeping tasks. The
family integrates high-performance signal processing features
designed to support sophisticated automotive RADAR
applications, and the S32R274 also integrates high accuracy
analog features to further enhance it's ability to interface with
a wide range of RADAR RF devices.
This application note illustrates the S32R family power supply
options and details the external circuitry required for power
supplies, oscillator connections, and supply decoupling pins. It
also discusses configuration options for clock, reset, ADC
modules and the RADAR analog front-end, as well as
recommended debug and peripheral communication
connections (including MIPI-CSI2) and other major external
hardware required for the device.
The S32R family requires multiple external power supplies to
operate. The main cores internal logic requires a 1.25 V power
supply. This can be supplied from an external source or on
some devices this can alternatively be provided by an internal
DC-DC regulator that requires a dedicated supply. 3.3 V is
NXP Semiconductors Document Number: AN5251
Application Note Rev. 1, 04/2018
S32R27/37 Hardware Design Guide
by: NXP Semiconductors
Contents
1 Introduction.............................. .............................. 1
2 S32R family package options
overview..................................................................2
3 Power supply...........................................................3
4 Clock configuration...............................................15
5 Device reset configuration............... .....................17
6 Recommended debug connectors and
connector pin-out definitions.................... ............ 18
7 ADC overview........................... ........................... 22
8 RADAR analog front end..................................... 23
9 Example communication peripheral
connections.......................................... ................. 29
10 High speed layout considerations..........................48
A Revision History................................................... 49

required for the general purpose I/O, flash memory, analog front-end, external communications interfaces, and on-chip SAR
analog to digital converter.
2 S32R family package options overview
The S32R family is available in multiple device and package options that are suited to development, debug and commercial
production.
Table 1. S32R package description
Device Package Description
S32R274 257 Map ball grid array (MAPBGA) Full support for all device modules and features
including JTAG and Nexus High Speed Aurora Trace
debug interfaces.
S32R372 257 Map ball grid array (MAPBGA) Full support for all device modules and features
including JTAG and Nexus High Speed Aurora Trace
debug interfaces. Pin compatible with S32R274,
although with reduced feature set. See Table 3 below
for details.
S32R372 141 Map ball grid array (MAPBGA) Reduced support for some device modules and
features. See Table 3 for details of reduced features
The table below shows the physical dimensions of the packages. See the device data sheet for complete package dimensions
and ball placement. Drawings are also available on nxp.com, search for the case outline number shown in Table 2.
Table 2. Package sizes
Device Package Physical Size Case Outline Number Pitch
S32R274 257 MAPBGA 14 x 14 mm 98ASA00081D 0.8 mm
S32R372 257 MAPBGA 14 x 14 mm 98ASA00081D 0.8 mm
S32R372 141 MAPBGA 10 x 10 mm 84ASA00768D 0.65 mm
The table below shows the main differences between the S32R family, including the different available packages. This list
only references the differences that have a hardware impact. For full details of all differences between the various devices
please see the relevant device reference manuals.
Table 3. Feature Differences Between Packages
Feature S32R274 S32R372 257 MAPBGA S32R372 141 MAPBGA
SD-ADC 4x SD-ADC None None
DAC Yes None None
MIPI CSI2 4 Lanes + Clock 2 Lanes + Clock 2 Lanes + Clock
Ethernet Yes, up to RGMII interface. None None
Wave Generator Module
(WGM)
Yes None None
LINFlexD Yes, 1 module Yes, 1 module None
FlexPWM 1 module, 12 channels 1 module, 12 channels 1 module, 11 channels
Table continues on the next page...
S32R family package options overview
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
2 NXP Semiconductors

Table 3. Feature Differences Between Packages (continued)
Feature S32R274 S32R372 257 MAPBGA S32R372 141 MAPBGA
SPI 2 modules 2 modules 2 modules, some chip selects not
available. See device muxing
sheet for details.
IIC 2 modules 2 modules 1 module (IIC1 only).
Serial Inter-Processor
Interface (SIPI)
Yes None None
System Timer Module
(STM)
3 modules x 4 channels 2 modules x 4 channels 2 modules x 4 channels
System Timer Module
(STM)
eTimer_0: 6 channels,
eTimer_1: 6 channels
eTimer_1:6 channels eTimer_1:5 channels
FlexRay 1 module None None
FlexCAN 1x FlexCAN, 2x FlexCAN-
FD
2x FlexCAN-FD 2x FlexCAN-FD
Device Power Supply Internal or External
regulation modes
Internal or External regulation
modes
External regulation mode only
3 Power supply
The S32R family of microcontroller units have a robust power management infrastructure that enables applications to select
among various user modes and to monitor internal voltages for high- and low-voltage conditions. The monitoring capability
is also used to ensure supply voltages and internal voltages are within the required operating ranges before the
microcontroller can exit the reset state and enter operation.
The microcontroller offers a DC-DC voltage regulator function as part of the power management controller (PMC) module. 1
This regulator can be used to supply the digital low voltage required for the internal logic and other low voltage supplies. The
device can be configured to use either this internal regulation mode or an external 1.25 V regulated power supply to provide
the core voltage. The standard configuration utilizes the internal DC-DC voltage regulator, with the following external supply
voltages:
• 3.3 V for main general purpose I/O, SAR ADC supply and reference, JTAG debug interface, flash memory supply
voltage and external communication interfaces (Ethernet, FlexRay, etc.)
• 3.13 - 5.5 V (required) for the internal DC-DC voltage regulator which supplies 1.25 V for the internal logic, PLL
circuits and low voltage/Nexus Aurora I/O, and MIPI-CSI2.
Detailed information on the power management configurations can be found in the Power management controller section.
1. Not available on the S32R372 141BGA Package.
Power supply
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
NXP Semiconductors 3

3.1 Power supply signals and decoupling
Table 4 lists all MCU power domains with corresponding pin names. Depending on the power management configuration,
some of the supplies below may not require an external power source. The power management configuration is detailed in
Power management controller.
Table 4. MCU power supply pins
Domain name Supply
Voltage
Description
VDD_LV_CORE 1.25 V Low-voltage supply for core logic
VDD_HV_IOx 3.3 V High-voltage supply for general purpose I/O
VDD_HV_RAW 3.3 V High-voltage, high fidelity supply for analog front-end block
VDD_HV_DAC 13.3 V High-voltage supply for DAC module in analog front-end
VDD_HV_ADC 3.3 V Voltage supply for SAR ADC module
VDD_HV_ADCREF0/2 23.3 V Voltage reference for SAR ADC 0/2
VDD_HV_FLA 3.3 V Voltage supply for flash memory
VDD_HV_PMU 3.3 V Voltage supply for power management unit
VDD_HV_IO_PWM 13.3 V Voltage supply for PWM IO
VDD_HV_REG3V8 13.13 V - 5.5 V3Voltage supply for internal DC-DC voltage regulator
VDD_LV_LFASTPLL41.25 V Voltage supply for DigiRF (SIPI/LFAST) PLL
VDD_LV_IO_AURORA51.25 V Voltage supply for Nexus Aurora I/O
VDD_LV_PLL0 1.25 V Voltage supply for system PLL
VDD_LV_IO 1.25 V Low voltage supply for general purpose I/O
VDD_LV_DPHY61.25 V Low voltage supply for MIPI-CSI2 DHPY
1. Not present on S32R372 141MAPBGA Package
2. To ensure optimum SAR ADC performance it is recommended to have a ground plane below the VDD_HV_ADCREF0/2
traces.
3. Internal regulation mode. When using external regulation mode, this domain can be tied to VDD_HV_PMU
4. The naming convention VDD_LV_LFASTPLL is equal to VDD_LV_DRFPLL. Not present on S32R372 141MAPBGA
Package
5. VDD_LV_IO_AURORA must be connected to the same voltage supply as VDD_LV_CORE. The supplies must be brought
up simultaneously.
6. Can be supplied from VDD_LV_CORE supply with filtering as recommended below.
Some of the supplies can be powered with different supply voltages. The internal voltage regulator supply,
VDD_HV_REG3V8, can be supplied with a voltage between 3.13 V and 5.5 V. See the device data sheet for specific
information and to learn what voltage ranges can be safely connected to the power pins.
Table 5 shows all power domains and the suggested decoupling and/or filter capacitors for their corresponding pins. These
values are provided as a guideline and will vary depending on the application and capability of the power supplies used.
The decoupling capacitors must be placed as close as possible to the MCU supply pins, with priority given to those with the
smallest capacitance value.
Table 5. Supply pin decoupling capacitors
Domain name Supply
Voltage
Minimum Decoupling Capacitors
VDD _LV_CORE 1.25 V 0.1 μF x 16, 4.7 μF x 4, 10 μF x 2 (40 μF total)1
VDD_HV_IOx 3.3 V 2 x 0.1 μF for each VDD_HV_IO supply2
Table continues on the next page...
Power supply
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
4 NXP Semiconductors

Table 5. Supply pin decoupling capacitors (continued)
Domain name Supply
Voltage
Minimum Decoupling Capacitors
VDD_HV_RAW 3.3 V 0.1 μF, 1 μF
VDD_HV_DAC 33.3 V 1000 pF, 0.1 μF, 1 μF
VDD_HV_ADC 3.3 V 0.1 μF, 1 μF
VDD_HV_ADCREF0/2 3.3 V 0.01 μF, 1 μF
VDD_HV_IO_PWM 33.3 V 2x 0.1 μF for each supply
VDD_HV_FLA 3.3 V 0.1 μF, 1000 pF
VDD_HV_PMU 3.3 V 100 nF, 4.7 μF
VDD_HV_REG3V8 33.13 V - 5.5
V
1 μF Ceramic4
VDD_LV_DRFPLL 31.25 V 1000 pF, 0.1 μF, 1 μF, 0.01 μF
VDD_LV_IO_AURORA 1.25 V 0.1 μF, 1 μF
VDD_LV_PLL0 1.25 V 1000 pF, 0.1 μF, 1μF, 0.01 μF
VDD_LV_DPHY 1.25 V Ferrite bead, >5 μF, 100 nF, 1000 pF
1. When using internal regulation mode, assure that the total capacitance (accounting for temperature variations) never falls
below 40 μF
2. External capacitors for the IO pins are dependent on the application.
3. Not present on S32R372 141BGA Package
4. When device is configured in external regulation mode and supply is connected to VDD_HV_PMU. For internal regulation
mode see SMPS external component configuration
The device has several pins for the connection to external decoupling capacitors for the analog front-end. Details of these can
be found in RADAR analog front end
3.2 Decoupling capacitors layout priority
When trade-offs must be made in the schematic layout, it is important to ensure that the highest priority supplies have
decoupling capacitors placed as closely as possible to the MCU. The list below outlines the recommended order of the
supplies from highest to lowest priority in terms of their importance for decoupling.
1. VDD_HV_RAW & VDD_HV_DAC
2. VDD_HV_ADCREF0/2
3. VDD_HV_ADC
4. VDD_LV_PLL0
5. VDD_LV_DPHY
6. VDD_LV_CORE
7. VDD_LV_AURORA
8. VDD_HV_PMU
9. VDD_HV_FLA
10. VDD_LV_LFASTPLL2
11. VDD_LV_IO
12. VDD_HV_PWM3
13. VDD_HV_IO
2. Not present on S32R372 141MAPBGA Package
3. Not present on S32R372 141MAPBGA Package
Power supply
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
NXP Semiconductors 5

Highest priority is given to the high-fidelity analog front end supplies VDD_HV_RAW and VDD_HV_DAC, as their
decoupling must be prioritized to maintain analog signal integrity. VDD_HV_ADRREF0, VDD_HV_ADREF1, and
VDD_HV_ADC is the SAR analog-to-digital converters reference and power supply decoupling. Clean supplies are vital to
ensure that the highest accuracy is achieved with the ADCs. The supply for the system PLL is prioritized as this helps to
ensure reliable and stable operation from the internal PLL circuit.
Medium priority is given to VDD_LV_CORE, VDD_LV_DRFPLL, VDD_LV_AURORA, VDD_HV_PMU,
VDD_LV_DPHY and VDD_HV_FLA. VDD_LV_CORE is the main supply for the on-chip digital logic and this is
prioritized as it affects the largest amount of logic on the device. VDD_LV_AURORA powers the high speed Nexus Aurora
pins and noise on this domain would affect the quality of the output. VDD_HV_PMU is the power management unit supply
and VDD_LV_DPHY is the MIPI-CSI2 DPHY supply. The MIPI-CSI2 DPHY is a high speed module which requires
minimal noise in order to acheive the specified performance levels. VDD_HV_FLA is the input supply for the flash memory.
A good supply to the flash memory ensures reliable flash programming and erasing.
VDD_LV_LFASTPLL powers the PLL for the LFAST/SIPI communication interface. 4VDD_HV_IO, VDD_HV_PWM,
and VDD_LV_IO drive GPIO and other external communication interfaces. Although it is still important that these supplies
have a clean power signal, the hardware they power is less affected by noise and they are considered of lower priority.
When completing the layout of decoupling capacitors care should be taken to reduce the volume of the space in the
transmission line between the device and the capacitor, which results in faster response to energy requests from the device.
The capacitor should always be the closest to the device so that the energy comes from the capacitor and not from the power
trace, as illustrated in the figure below.
Figure 1. Decoupling capacitor placement recommendation
3.3 Power management controller
The S32R family has a dedicated module for configuration and monitoring of power supplies, enable signals, internal
component trimming, and power-on reset generation. The Power Management Controller (PMC) consists of an analog block
and a supporting digital interface that provides control over the analog components. The PMC chapter in the device reference
manual explores the digital block in depth.
4. This interface is not present on the S32R372 device, but the supply name remains the same for the 257MAPBGA
package to avoid confusion, and is not present on the 141MAPBGA package.
Power supply
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
6 NXP Semiconductors

NOTE
This document will focus on the external hardware and connections concerned with the
PMC analog block.
3.3.1 Core supply options
The S32R family offers two options for supplying the 1.25 V used by the core and other low-voltage digital power domains.
• Internal voltage regulation mode, using the integrated DC-DC voltage regulator (VREG)5
• External voltage regulation mode using an externally regulated 1.25 V supply
The input pin VREG_SEL allows selection between internal and external regulation modes, the function of this input is
described in the table below.6
Table 6. VREG_SEL input signal
Input Level Core Supply Mode
High (3.3 V) Internal regulation mode
Low (GND) External regulation mode
The PMC has an internal voltage regulator function that uses a switched-mode power supply (SMPS) circuit to supply the
1.25 V required by the internal core logic, VDD_LV_CORE and the other low-voltage digital supplies
(VDD_LV_AURORA, VDD_LV_PLL0, VDD_LV_DPHY and VDD_LV_IO). The regulator requires the support of
external circuitry detailed in SMPS external component configuration. This configuration is an asynchronous buck regulator
with nominal switching frequency of 1 MHz. The switching frequency may be modulated to improve the EMI performance
of the device, further information on this feature can be found in the PMC chapter in the device reference manual.
VREG_SEL is part of a collection of I/O signals that relate to the VREG operation mode. The other pins are mentioned in the
table below.
Table 7. PMC Voltage regulator signals
Signal Name Direction VREG Enabled (Internal Mode) VREG Disabled (External Mode)
VREG_POR_B Input External power-on reset. If not used it is
recommended to be externally pulled up
to 3.3 V, but can be left floating.
Internally pulled up to 3.3 V.
Power-on reset (POR) input. Used by
external circuitry to trigger a POR or hold
device in reset state. Should be used to
hold device in reset until supplies are
within the ranges described in the device
data sheet.
VREG_ISENS1Input Current sense input to internal regulator Not used. Connect to VDD_LV_CORE
VREG_SWP1Output Output from internal VREG. Controls the
gate of the external switching PMOS
transistor 2
Not used, can be left floating. Internally
pulled up, do not connect to GND.
1. Not present on S32R372 141MAPBGA package.
2. If the connection between VREG_SWP and the PMOS gate is broken, the switch may fully turn on. For added protection
against this risk, a 100 Kilo Ohm resistor can be connected between VDD_HV_REG3V8 and the PMOS gate.
5. Not supported on S32R372 141MAPBGA package.
6. VREG_SEL pad is internally bonded to GND on S32R372 141MAPBGA package.
Power supply
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
NXP Semiconductors 7

3.3.2 Internal voltage regulator supply mode
The standard device configuration for the S32R family 257 MAPBGA packages uses the internal DC-DC voltage regulator to
supply the core voltage and other low-voltage digital supplies. Figure 2 shows all the power supply connections required
when operating in internal voltage regulation mode and also provides guidelines on how to structure the power nets. Values
for the decoupling capacitors shown in the figure are listed in Table 5.
DC-DC
VReg
Board supply 5V -12V
DC-DC
VReg
SWP
SAR ADC
3.3V
low noise
POR
Lin.
VReg
3.3V
low noise
Lin.
VReg Lin.
VReg
POR_B
DC-DC
VReg
AFE
Internal Lin. VRegs
3.3V
low noise
HV_PMU
3.3V
HV_REG_3V8
3.13V - 5.5V
LV_DRFPLL
LV_PLL0
LFAST
PLL
System
PLL
HV_ADCREF0/2
HV_ADC
1.25V
HV_DAC
HV_RAW
LV_IO_AURORA
NEXUS
AURORA
See "SMPS
External
Component
Configuration"
LV_DPHY
MIPI
CSI2
HV_FLA
HV_IOx
ISENS
LV_CORE
1.25V, 1.8A
HV_IO_PWM
Figure 2. Supply connections
The internal regulator requires a dedicated 3.13 V - 5.5 V supply alongside the 3.3 V PMC supply to generate the 1.25 V
digital low voltage. The support of an external PMOS switch circuit is also required, details are given in SMPS external
component configuration. The analog front-end (AFE) requires high-fidelity supplies and careful decoupling to support its
sensitive analog functionality, covered in RADAR analog front end.
Internal regulation mode is enabled by driving the VREG_SEL input high and has the following attributes.
• The PMC internal power-on-reset (POR) and low-voltage/high-voltage detect (LVD/HVD) circuits are enabled by
default.
• The internal POR will keep the device in reset until all the monitored supplies have reached their minimum operation
threshold.
• The internal POR function means that the external POR pin VREG_POR_B is not needed. As such, it is internally
pulled up to the PMC supply voltage. It can be left floating or alternatively connected to 3.3 V.
• VREG_POR_B remains active in internal regulation mode, even though POR is managed internally. If pulled low it
will cause a power-on reset regardless of voltage regulation mode.7
• The internal LVD/HVD circuits are by default enabled to ensure the expected boot-up sequence occurs. More
information on the LVDs/HVDs is available in Low-Voltage (LVD) and High-Voltage Detection (HVD).
• Use a single Linear VREG to supply both VDD_HV_RAW and VDD_HV_DAC. Both supply pins must have the
recommended filtering as described in Table 5 and have separate routes (star route) of roughly equal length to the
Linear VREG.
• Either ramp VDD_HV_IO and VDD_HV_PMC together or ramp VDD_HV_IO before VDD_HV_PMC such that the
two supplies always maintain 100 mV or less difference when using internal regulation mode.
• VDD_HV_IO, VDD_HV_IO_RGMII, VDD_HV_IO_PWM and VDD_HV_IO_LFAST supplies should be treated as a
single supply from a board perspective.
7. VREG_POR_B can be used in internal regulation mode to ensure that the POR sequence is only started when main
power supply reaches a stable regulation point. This can assist in cases where the power supply reaches the
minimum LVD threshold but then drops below the threshold again when loaded, before reaching a stable regulation
point.
Power supply
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
8 NXP Semiconductors

3.3.3 SMPS external component configuration
When operating in internal voltage regulation mode, an SMPS circuit is required along with the support of external
components in order to minimize noise and maintain a stable supply to guarantee device performance. Special care must be
taken so that the switched regulator does not introduce noise into high-fidelity analog components. The external component
layout is shown in Figure 3.
Figure 3. SMPS external components layout
Table 8 provides recommended values for the external components.
Table 8. External component values
Component Label Recommended Value
M1 SI3443, 2SQ2315
L1 2.2 μH 3A <100 mΩ series resistance (E.g. Bourns SRU8043-2R2Y)
D1 SS8P3L 8A Schottcky diode
R1 24 kΩ
C1 10 μF ceramic
Table continues on the next page...
Power supply
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
NXP Semiconductors 9

Table 8. External component values (continued)
Component Label Recommended Value
C2 100 nF ceramic
C3 100 nF ceramic (place close to inductor)
C4 10 μF ceramic (place close to inductor)
C5 1 nF ceramic
C6 4x 100 nF + 4x 10 nF ceramic (place close to MCU supply pins)
C7 4x 10 μF ceramic (place close to MCU supply pins)1
C8 100 nF ceramic (place close to MCU supply pins)
C9 1 μF ceramic (place close to MCU supply pins)
1. These are the same capacitors as those listed for VDD_LV_CORE in Table 2
For optimum electro-magnetic interference (EMI) performance, it is critical that the inner and outer loops shown in Figure 3
overlap on the PCB and are made as short as possible. It is highly recommended to have a section of the PCB ground plane
dedicated to making a good connection between the grounds of C1/C2 and C3/C4. This measure will help to ensure that the
loops are made as short as possible.
The role of C1/C2 is to guarantee a low input impedance to the buck converter. In a similar manner, C3/C4 make the
impedance low at the buck converter output. This measure helps reduce the high frequency content of the current passing
through the highlighted branch 'Iload', making it less critical that the buck converter components be placed close to the
VDD/VSS pins of the MCU. However, it is important that capacitors C6 and C7 are placed as closely as possible to the
VDD/VSS pins of the MCU, as they guarantee the low impedance of the core MCU supply and also help to reduce the high
frequency content of the 'Iload' path.
The gate-driver circuitry also forms important current loops that must be minimized (not shown in Figure 3). For that
purpose, C8/C9 must be placed as close as possible to the gate-driver supply pins. The ground connections for C8/C9 must be
made as short as possible to C1/C2. When the PMOS switch is turned on, the high-frequency current that charges the gate
comes from C1/C2, passing through the PMOS gate into the gate-driver pin. That current is carried to the gate-driver VSS pin
returning to C1/C2. This current loop must be made as small as possible.
Conversely, when the PMOS switch is turned off, high-frequency currents enter in the PMOS gate coming from the gate-
driver pin and flows into C1/C2, returning through the ground into C8/C9 and then into the gate-driver supply pin.
Minimizing this second loop area is as critical as the first.
To shield nearby nets from the gate-driver generated noise, it is also recommended that the gate-driver supply pins are used
to shield the VREG_SWP net until it reaches the PMOS switch. Nets on other PCB layer should avoid running parallel to this
net.
The figure below is a circuit schematic showing an example SMPS circuit derived from the above guidelines. For best
performance, use the component values recommended in Table 8.
Power supply
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
10 NXP Semiconductors

Figure 4. Example schematic of SMPS external components
3.3.4 External supply mode
If there is a stable 1.25 V regulated supply available to provide the digital low voltage, the internal voltage regulator can be
disabled. This also negates the need for the external SMPS circuit. An overview of the power connections required for such a
configuration is shown in Figure 5. This is the default and only configuration for the S32R372 141MAPBGA packaged
device, due to the reduced pin count.
DC-DC
VReg
Board supply 5V -12V
SAR ADC
3.3V
low noise
POR
Lin.
VReg
3.3V
low noise
Lin.
VReg Lin.
VReg
POR_B
DC-DC
VReg
AFE
Internal Lin. VRegs
3.3V
low noise
HV_PMU
3.3V
HV_REG_3V8
HV_ADCREF0/2
HV_ADC
1.25V
HV_DAC
HV_RAW
DC-DC
VReg
HV_FLA
HV_IOx
LV_CORE
1.25V, 1.8A
HV_IO_PWM
External
Monitor
Figure 5. Supply connections
This mode of operation can be selected by driving the VREG_SEL pin low.8This disables the internal:
• Voltage regulator (VREG)
• VDD_LV POR function (can be enabled by software)
• VDD_LV LVD/HVD circuits (can be enabled by software)
8. Not required on S32R372 141MAPBGA package as VREG_SEL is internally bonded to GND
Power supply
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
NXP Semiconductors 11

When internal regulation is disabled, the signals VREG_ISENS and VREG_SWP are not needed as they are for feedback and
control of the SMPS circuitry. VREG_ISENS should be connected to VDD_LV_CORE and VREG_SWP is internally pulled
up, so should be left floating. 9
In external regulation mode, the supply for the internal voltage regulator, VDD_HV_REG3V8, can be connected to the same
supply voltage as VDD_HV_PMU.
Use a single Linear VREG to supply both VDD_HV_RAW and VDD_HV_DAC. Both supply pins must have the
recommended filtering as described in Table 5 and have separate routes (star route) of roughly equal length to the Linear
VREG.
VDD_HV_IO, VDD_HV_IO_RGMII, VDD_HV_IO_PWM and VDD_HV_IO_LFAST supplies should be treated as a
single supply from a board perspective.
VDD_LV POR and LVD/HVD is the responsibility of the external regulation circuit. The device must be kept in reset
(VREG_POR_B driven low) during power-up until all supplies have reached their minimum operating threshold and also
during operation if any of the supplies move outside the specified range, as defined in the device data sheet. To achieve this,
external LVD/HVD circuits are needed to monitor the supplies. After power-up, the internal LVDs/HVDs can be enabled by
software to act as a second tier of detection and provide power supply information to the software.
3.4 Supply monitoring
The S32R family has the capability to monitor selected supply voltages internally. This section concerns only with the
internal monitoring functions for POR and LVD/HVD. The external POR and LVD/HVD circuit behavior will vary and
should be designed using the device data sheet as reference. From this point, it is assumed that internal regulation mode is
being used unless where explicitly stated. In external regulation mode, the internal POR and LVD/HVD are disabled by
default but can be enabled by software after power-up.
The function of the POR and LVD circuits is to hold the device in reset as long as the supply voltages to the LVD circuits are
below the minimum operating voltage. The device is held in reset until the point at which the supplies cross the lower
threshold and the POR and LVDs are released.
3.4.1 Behavior of LVD / HVD
The internal LVD and HVD circuits monitor whether the voltage on the corresponding supply is below or above defined
values and either assert a reset or an interrupt. The LVDs/HVDs also support hysteresis for the falling and rising trip points.
Although there is an option to disable the LVDs and HVDs following reset, they are capable of being used in a ‘monitor’
only mode and are also capable of generating a safe/interrupt event. The LVDs/HVDs can also be configured after device
initialization to prevent reset when a supply crosses the LVD threshold, providing a higher voltage range. An application then
must verify the device remains in the functional range.
NOTE
The LVDs that form the power-on reset functionality, monitoring VDD_LV_CORE and
VDD_HV_PMU, cannot be disabled. These modules are used during power-up phase and
must ensure that an absolute lowest threshold of operation is never crossed. This is not a
guarantee that the device will function down to this level. It is rather a guarantee that the
device will recover if this level is crossed.
9. Not required on S32R372 141MAPBGA package as these signals are internally bonded.
Power supply
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
12 NXP Semiconductors

3.4.2 Low-Voltage (LVD) and High-Voltage Detection (HVD)
The internal LVD circuits monitor whether the voltage on the corresponding supply is below defined values and either assert
a reset or an interrupt, while the HVD circuits monitor to ensure a supply does not exceed an upper voltage limit. The LVDs/
HVDs also support hysteresis in the falling and rising trip points.
• All LVDs and HVDs are capable of generating either a reset or an interrupt based on configuration, with the exception
of two POR threshold monitors10 :
• LVD monitoring the internal core voltage (VDD_LV_CORE) always generates a reset when triggered.
• LVD monitoring the PMC voltage supply input (VDD_HV_PMU) always generates a reset when triggered.
• All LVDs and HVDs configured for reset generation cause functional or destructive reset. Reset is not exited until all
destructive reset conditions are cleared.
• The appropriate bits in the PMC status registers are set by LVD and HVD events.
• LVD and HVD control is protected by the SoC-wide register protection scheme. Therefore, it is configurable as long as
the scheme is followed.
• There are user option bits available to allow degrading of “configurable” LVDs/HVDs from destructive down to
functional reset. This is a write once mechanism managed by SSCM during device initialization.
• When the LVD or the HVD is enabled for destructive reset generation, then when a trigger event is detected, the
external RESET_B pin is driven low.
Please refer to the device data sheet for LVD and HVD characteristics.
3.4.3 Power-on reset
The power management controller (PMC) controls the internal power-on reset (POR) signal for the MCU. POR is the
combination of all internal POR signals from the analog PMC block. When the critical power supplies are below minimum
levels (internal regulation mode) or the VREG_POR_B pin is driven low, the MCU is held in the POWERUP phase of the
reset state machine, POR asserted, until the power supplies have reached specified levels. When the required voltage levels
are reached, POR is deasserted and is input to the reset generation module (MC_RGM) which propagates the device through
the next steps of the boot process.
The PMC has internal POR low voltage detect (LVD) circuits to detect the minimum critical power supply voltages required
to operate the internal voltage regulator, including hysteresis. It monitors:
• The voltage on the 1.25 V supply input, VDD_LV_CORE
• The 3.3 V signal used internally by the PMC, VDD_HV_PMU
Once both these supply voltages are above the threshold the internal POR signal will deassert. See Device reset configuration
and the Reset chapter in the reference manual for VREG_POR_B and RESET_B pin functionality.
3.5 Power sequence
The device is considered to be in a power sequence (POWER-UP state) when the device is either not supplied or is partially
supplied. An internal power-on reset (POR) signal is used to identify POWER-UP state. This signal is released on exit of the
power sequence. The power-on reset signal is a combination of LVD monitoring of the VDD_LV_CORE and
VDD_HV_PMU supplies. The exit from the next phase, PHASE0, depends on the release of the secondary LVD/HVD
circuits, which monitor:
• VDD_LV_PLL0
• VDD_HV_IO
• VDD_HV_FLA
• VDD_HV_ADC
10. As mentioned previously, the internal POR management is disabled by default when external regulation mode is
selected. They cannot be disabled when operating in internal VREG mode.
Power supply
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
NXP Semiconductors 13

Once they have reached the minimum operating threshold the device will exit reset. For more information on phases of the
reset process, please refer to the Reset chapter in the device reference manual.
The actual threshold use for each internal LVD depends on the configuration of the device. This is configurable by hardware
(flash option bits content) or by software (LVD event configuration through PMC register interface). Once the power-on
signal has been asserted, the device configuration is reset to default power-up configuration. During the initialization phase,
the device defaults to a pre-determined state for each of the LVDs, HVDs, and the internal regulators. As the flash memory
becomes available, the differential read process allows the trimmed data to be available for trimming the internal LVDs,
HVDs, and regulators.
3.5.1 Power-up sequence
In this section, the assumption is made that all supplies are low when entering the power-up sequence. Brown-out and power
down sequences are specified in further sections below.
There are simple power sequencing rules to follow in order to correctly power-up the device:
• The system PLL supply (VDD_LV_PLL0) and the core supply (VDD_LV_CORE) must be powered simultaneously. It
is recommended to connect them to the same voltage supply.
• The high-voltage I/O supply (VDD_HV_IO) and the Power Management Unit supply (VDD_HV_PMU) must be
powered simultaneously or VDD_HV_IO ramped before VDD_HV_PMU such that the two supplies always maintain
less than 100 mV difference during the power ramp. They can be connected to the same voltage supply.
• If VDD_HV_DAC and VDD_HV_RAW are supplied by 2 separate regulators, the following must be met:
• For RAW or DAC ramp rates less than 1ms, VDD_HV_DAC comes on no earlier than 500 us before
VDD_HV_RAW.
• for RAW or DAC ramp rates greater than 1ms, VDD_HV_DAC is below 2.0V at the time VDD_HV_RAW
reaches 1.0 V.
• Alternatively VDD_HV_DAC and VDD_HV_RAW can be supplied from the same regulator, providing adequate
decoupling is provided as described in Power supply signals and decoupling
• For the S32R274 device the SD ADCs must be powered before a signal is applied to their inputs, to ensure protection
of the input channels from overdrive signal levels. To do this, ramp VDD_HV_RAW supply before applying input to
the SD ADCs.
All power supplies should ramp at slew rates within the ranges recommended in the device data sheet. For recommended
supply groupings for the S32R372 devices please see the device data sheet power sequencing requirements section.
3.5.2 Power-down sequence
If the threshold of the configurable monitor LVDs is crossed and they are configured to generate a destructive reset, the
device re-enters the PHASE0 phase. The power-down sequence is started and the device enters the POWER-UP state as soon
as the threshold of one of the POR LVDs (monitoring VDD_LV_CORE and VDD_HV_PMU) is crossed. The device
supplies may then proceed to drop down to ground either through device leakage or external pull-down.
3.5.3 Brown-out management
During brown-out, the device re-enters the POWER-UP phase as soon as the threshold of either POR VDD 1.2 V or APOR is
crossed.
Power supply
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
14 NXP Semiconductors

4 Clock configuration
The S32R family system reference clock can be sourced in three ways: using the internal RC oscillator (IRCOSC),
connecting an external crystal or connecting an external oscillator (XOSC). To use XOSC, an external 40 MHz crystal or
oscillator must be connected through the XTAL and EXTAL pins. XTAL and EXTAL pins also support differential LVDS
clock inputs. Information on how to do this can be found in Connecting external clock sources. IRCOSC or XOSC is used as
the clock source for the internal phase-locked loops (PLL) to generate the high frequency clocks for the cores and
peripherals.
This structure provides five different clock domains that are available as the source for system and peripheral clocks:
• IRCOSC - 16 MHz internal reliable RC oscillator
• XOSC - 40 MHz oscillator (using external crystal (XTAL) or external oscillator in bypass (EXTAL))
• PLL0 - up to 240 MHz PLL
• PLL1 - up to 240 MHz frequency-modulated (FM) PLL
• SDPLL- 320 MHz11 PLL for the Sigma-Delta ADC
XOSC
40MHz
1-2ps Jitter
Bypass:
40MHz
FMPLL_1
VCO:600-
1250MHz
IRCOSC
16MHz
Cryst
40MHz
SDPLL
320MHz
IRC_CLK
PLL_CLK0
PLL_CLK1
PLL_0
VCO: 600-
1250MHz
OSC
40MHz
XOSC_CLK
SDPLL_CLK
AFE
XTAL
EXTAL
Figure 6. S32R family clock sources
During power up, the IRCOSC is the default clock for the system. In normal operation, software can then configure each of
the system components to use one of the clock domains as the clock source. The dual PLL must be enabled by software and
can provide separate system and peripheral clocks. PLL0 is the primary PLL driven by the reference clock and used to
provide a clock to the device modules. PLL1 is a frequency-modulated PLL (FMPLL) driven by PLL0 and is used to provide
the system clock. Alternatively, XOSC can be used to drive PLL1.
The most important aspects of an accurate clock source require that some care be taken in the layout and design of the
circuitry around the crystal and PLL power supplies. Any noise in these circuits can affect the accuracy of the clock source to
the PLL. The power supply for the PLL is taken from VDD_LV_PLL0. Noise on this supply can affect the accuracy and
jitter performance of the PLLs. In order to minimize any potential noise, it is recommended that the additional capacitors
recommended in Table 5 are fitted to the VDD_LV_PLL0 supply.
11. Divided by 2 (160 MHz), and 4 (80 MHz) if used for system and peripheral clocks
Clock configuration
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
NXP Semiconductors 15

4.1 Connecting external clock sources
The S32R family features internal load capacitance on the XTAL and EXTAL pins for connecting external clock sources.
This feature is intended to simplify the design and reduce the overall system cost by eliminating external components and
reducing the PCB footprint. See the device data sheet for details on the internal capacitance values. PCB designers must take
into account the parasitic capacitance levels on the signal lines connecting an external oscillator to the XTAL and EXTAL
pins in order to avoid frequency deviation. Generally, for a crystal with load capacitance of 8 pF, a capacitance figure of 12
pF on the signal lines connected to both XTAL and EXTAL will result in good oscillator performance. Choose a crystal with
a Q factor of > 25,000.
A diagram for the connection of an external 40 MHz crystal oscillator is shown in the figure below.
XTAL EXTAL
Crystal
S32R27X / S32R37X
Figure 7. External oscillator connection
The oscillator should be placed as close as possible to the MCU. In order to minimize signal degradation, the circuitry should
be placed entirely on only one PCB layer, avoiding unnecessary vias where possible. Do not allow any signals to cross the
crystal connections to the device. Absolutely no high current or high speed signals should be run near any of the crystal
components.
Other than the connections shown in the above schematics, no other connections should be made to the crystal or EXTAL
and XTAL device pins. Do not use XTAL to drive any other circuitry than shown.
If an external single clock source is being used as clock reference to the MCU, then the XTAL pin should be left floating and
the clock should be provided to EXTAL as shown in the figure below. Note that the clock source should be a low voltage
signal, please ensure any source meets the specifications detailed in the device data sheet for the input signal to avoid
potential damage to the device.
XTAL EXTAL
S32R27X / S32R37X
40MHz
Clock
Figure 8. External clock connection (Single Ended Bypass Mode)
In order to use a differential LVDS clock input for the device, the device offers 100 Ω internal termination resistance between
EXTAL and XTAL pins. For differential operation positive clock should be connected to XTAL and negative to EXTAL
pins, and if the clock is a differential voltage source then AC coupling capacitors of 0.01 uF should be used, as shown in the
figure below. Care should be taken during PCB design to avoid vias, and ensure that all differential pairs are trace and
impedance matched, and also follow differential pair best practices as detailed later in the document.
Clock configuration
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
16 NXP Semiconductors

S32R27X / S32R37X
Figure 9. External clock connection (Differential LVDS AC Coupled Mode)
S32R27X / S32R37X
Figure 10. External clock connection (Differential LVDS DC Coupled Mode)
Using either of these methods to connect an external clock makes it available as the XOSC internal clock source.
5Device reset configuration
The S32R family of MCU's require only very basic external reset circuitry. External circuitry for device configuration is not
required. The device is configured during reset based on data in stored flash memory.
5.1 External reset signals
The S32R family of devices feature two active-low external reset signals:
• Functional reset (RESET_B)
• Power-on reset (VREG_POR_B)
RESET_B is a bidirectional reset input/output that indicates if the device is active (high signal) or in reset. It is thus weak
pull-up after the reset sequence has completed, but an external pull up resistor to VDD_HV_IO should also be used. A falling
edge on this pin will trigger a functional reset to the Reset Generation Module (RGM). Forcing this pin low will keep the
device in the last phase of the reset sequence (Phase3[Functional]).
In external voltage regulation mode, VREG_POR_B allows external supply circuits to signal to the MCU when power is
available, so the power-up sequence can begin. It should be forced high when the critical power supplies cross the LVD
threshold.
In internal regulation mode, VREG_POR_B is not needed as the POR is managed within the PMC. It is internally pulled up
to the PMC voltage, so it can be left floating. Alternatively, it can be connected to VDD_HV_PMU through a 4.7 Kilo Ohm
pull-up resistor. , 12
Both of these pins operate on the 3.3 V power domain.
12. Note that VREG_POR_B remains active in internal regulation mode. As such, if it is pulled low it will cause a power-on
reset in the device.
Device reset configuration
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
NXP Semiconductors 17

6 Recommended debug connectors and connector pin-out
definitions
The S32R microcontroller family implements the newly added (in the IEEE-ISTO 5001™-2011 version of the standard) high
speed serial Nexus trace Auxiliary Port that uses the Xilinx™ Aurora physical interface. The Aurora interface allows the
Nexus protocol information to be transmitted serially at a high date rate over one or more Aurora lanes. The Aurora protocol
handles the encoding of the data and stripes the information across the number of lanes available on the device.
Table 9 shows the recommended connectors for different applications for the S32Rxxx Family.
Table 9. Recommended connectors
Connector style Target system part number Connector type
14-pin BERG JTAG only 3M 2514-6002UB JTAG-only configuration
17-position (2 × 17, 34-pin) Samtec Samtec ASP-137973-01 Serial Nexus configuration (supports up
to 8 simplex lanes, less lanes are
available if duplex support or High
Speed Calibration LFAST interface
support is required)
NOTE
Whichever connector is chosen, "keep-out" areas may be required by some tools. Consult
the preferred tool vendor to determine any area that must remain clear around the debug
connector. Some tool vendors may include an extension cable to minimize "keep-out"
areas, but use of an extension will degrade the signal. In many cases, this degradation will
be insignificant, but it depends on many factors including clock frequency and target
board layout.
6.1 S32R Family JTAG connector
Table 10 shows the pinout of the recommended JTAG connector to support the S32R device family.
The recommended connector for the target system is Tyco part number 2514-6002UB.
Table 10. Recommended JTAG connector pinout
Description Pin Pin Description
TDI 1 2 GND/VSS
TDO 3 4 GND/VSS
TCK 516 GND/VSS
EVTI0 7 8 VREG_POR_B
RESET_B 9 10 TMS
VREF/VDD 11 12 GND/VSS
EVTO0 13 14 JCOMP
1. If LBIST is enabled, an external pull resistor between 1 Kilo and 100 Kilo Ohm must be connected between TCK and either
VDD/VSS to avoid LBIST failures
Recommended debug connectors and connector pin-out definitions
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
18 NXP Semiconductors

Figure 11. Diagram of the JTAG connector pinout
6.2 S32R family high-speed Nexus serial trace connector
For high speed Nexus Aurora trace applications, the Samtec™ ERF8 Series connector is recommended in the IEEE-ISTO
5001™-2011 standard. For the S32R family, the 17 position (34 pins) connector is recommended. The part number of the
Samtec connectors are shown in Table 11.
Table 11. Recommended high-speed serial trace connector part numbers
Connector Part number (Samtec) Style Description
HS34 ASP-137973-01 Samtec ERF8 Series, 17
position by 2 row
Vertical mount for MCU
module
HS34 ASP-177706-02 Samtec ERF8 Series, 17
position by 2 row
Right Angle mount for MCU
module
The Samtec ERF8 series of connectors is intended for high speed applications requiring a minimum footprint size with a
reliable, latching connection. The recommended connector has two rows of seventeen contacts each with a spacing of 0.8
mm. The connector provides isolation between the high-speed trace signals and the low-speed JTAG and control signals. It
also provides ample ground connections to ensure signal integrity. If at all possible, the connector should be placed onto the
target system with the even numbered pins nearest the edge of the printed circuit board. It is also recommended that the
"even" side of the connector be mounted closer to the edge of the printed circuit board to facilitate a direct connection to the
tool.
Figure 12 is courtesy of Samtec U.S.A.
Recommended debug connectors and connector pin-out definitions
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
NXP Semiconductors 19

Figure 12. Recommended Nexus connector
Table 12 shows the recommended pinout for the Samtec connector.
Table 12. S32R family high-speed serial trace connector
Function Pin No Pin No Function
TX0+ 1 2 VREF
TX0- 3 4 TCK/TCKC/DRCLK
VSS 5 6 TMS/TMSC/TxDataP
TX1+ 7 8 TDI/TxDataN
TX1- 9 10 TDO/RxDataP
VSS 11 12 JCOMP/RxDataN
TX2+ 13 14 EVTI1
TX2- 15 16 EVTI0
VSS 17 18 EVTO0
TX3+ 19 20 VREG_POR_B
TX3- 21 22 RESET_B
VSS 23 24 VSS
(TX4+)125 26 CLK+
(TX4-)127 28 CLK-
VSS 29 30 VSS
(TX5+)131 32 EVTO1/RDY
(TX5-)133 34 N/C
VSS GND GND VSS
1. Reserved for TXn signals, not currently used.
Recommended debug connectors and connector pin-out definitions
S32R27/37 Hardware Design Guide, Rev. 1, 04/2018
20 NXP Semiconductors