NXP Semiconductors MPC5777C User manual

MPC5777C Clock Calculator Guide
How to use MPC5777C tool to easily calculate device
frequency domains
by: NXP Semiconductors
1.Introduction
NXP’s MPC5777C is a dual-core 32-bit microcontroller
dedicated to high-performance powertrain applications.
The MCU supports ASIL-D automotive safety rating
and runs on two e200z7 Power Architecture cores. The
MPC5777C features two versions, a standard version
whose core runs up to 264 MHz and a performance
version that supports up to 300 MHz. This application
note will refer to these versions as
“MPC5777C_264MHz” and “MPC5777C_300MHz”,
respectively, for version-specific information; general
content that applies to both versions will refer to the
device as simply “MPC5777C”.
The MPC5777C supports an 8-44 MHz external
oscillator (XOSC), a 16 MHz internal RC oscillator
(IRC), and two phase locked loops (PLL).
MPC5777C_264MHz’s two PLLs support 200 MHz
and 264 MHz, respectively; MPC5777C_300MHz’s
respective PLLs can run up to 240 MHz and 300 MHz.
The IRC is selected out of reset so increasing the
operating frequency from 16 MHz requires additional
configuration. The MPC5777C Clock Calculator is
meant to complement the reference manual. It seeks to
simplify the clock configuration process by providing a
graphical, interactive tool to help the user find the
NXP Semiconductors
Document Number: AN12176
Application Notes
Rev. 1
,
12/2018
Contents
1. Introduction........................................................................1
2. Clock calculator design...................................................... 2
2.1. Tree......................................................................... 4
2.2. Device Select .......................................................... 7
2.3. Oscillator control .................................................... 8
2.4. Peripheral domains ................................................. 8
2.5. FlexCAN clocking and MCAN clocking................ 9
2.6. LFAST clocking ................................................... 10
2.7. PLLx..................................................................... 12
2.8. Reference tables (pll0_phi, pll0_phi1, and pll1_phi)12
2.9. Summary............................................................... 13
2.10. Limits.................................................................... 16
3. Clock tool example use case: Configure eMIOS to 60 MHz
PLL1 with MPC5777C_264MHz .................................... 17
3.1. Select the Device .................................................. 18
3.2. Configure PER_CLK............................................ 19
3.3. Observe the registers............................................. 29
3.4. Copy the code ....................................................... 30
4. Conclusion....................................................................... 30
5. Revision History .............................................................. 30

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correct register settings in order to achieve the desired clock frequencies.
Accompanying this application note is the clock calculator itself. You can download it from
MPC5777C clock calculator.
The clock calculator makes use of macros to perform functions like resetting the spreadsheet to initial
values, configuring all clock frequencies to the fastest allowable settings, and copying generated code.
Macros must be enabled in the user’s MS Excel settings to access these features. If macros are turned
off, however, the tool will still be able to calculate clock frequencies, but the aforementioned features
will be disabled. To turn on macros in MS Excel 2016, go to the Developer tab on the top toolbar and
click on Macro Security. A popup window will appear. In it, select Enable all macros.
Figure 1. Enable macros
2.Clock calculator design
The MPC5777C clock calculator takes the form of an interactive Microsoft Excel spreadsheet organized
into multiple tabs as shown in the following figure.
Figure 2. MPC5777C Clock calculator setup
Clock sources (e.g. oscillators and PLLs) propagate to the various clock domains from which the MCU
modules take their clocks. Most cells representing clock domain frequencies are not to be modified
manually. The user is meant to enter frequencies to the few select clock sources and all clock domain
frequencies derive from these sources. Several clock domain inputs are meant to be modified manually
as they represent external clocks that are driven into a pin. There are also input cells that set muxes and
clock dividers. All cells that take entries have blue borders instead of black, as shown in the figure
below.

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Figure 3. Input cells vs. Output cells
There are limits to what frequencies can be entered to the input frequency cells. Values that are out of
range will be rejected and the user will receive an error message. Invalid clock domain frequencies that
arise from valid input values and legal, but improper, dividers will be shaded in red, as will be explained
in greater depth later in this application note.
Frequency values are linked across tabs, so PER_CLK in the Tree tab will always be the same as
PER_CLK in the Peripheral Domains tab. Hyperlinks are provided to duplicate domain names to link
back to their points of origin. For example, PER_CLK originates in Tree. So clicking the PER_CLK
textbox in Peripheral Domains will take the user to PER_CLK in Tree. Textboxes that are links, when
hovered over, will cause the mouse cursor to turn into a hand icon and a pop-up to appear, showing the
destination address, as shown in the following figure.

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Figure 4. Clicking on a link
The following subsections will explain in depth the purpose of each tab.
2.1. Tree
Tree is the centerpiece of the tool. This tab is the starting point for all clock frequency calculations. It is
organized to resemble the MPC5777C clock tree as presented in the following figure.

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Figure 5. MPC5777C Reference manual clock Tree
Figure 6 shows, in part, the diagram’s clock tool counterpart. The difference between the two is that the
latter is interactive.

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Figure 6. Clock calculator Tree
The flow of the diagram generally goes from left to right. On the left are the MPC5777C clock sources
and on the right are the clock domains. MCU modules run on one or more of these clock domains.
Clock domain frequency values are displayed in the outlined cells next to their labels. Most cells are not
meant to be written to; their values are dependent on the frequencies of preceding steps in the clock tree.
Take FM_PER_CLK, for example: its value is sourced from either the system clock, which in turn
comes from either the IRC, XOSC, PLL0_PHI, or PLL1_PHI. Now look at the XOSC block. XOSC
depends on the settings from the Oscillator Control tab. So all clock domains ultimately derive from a
few select inputs. The IRC is always on at 16 MHz, PLL0_PHI and PLL1_PHI are configured in the
PLL0 and PLL1 tab, respectively. The system clock selects from these four clock sources by selecting
the value of the System Clock Selector block. Then finally the selected signal is divided by the
FM_PER_CLK prescaler value. It is important to note, though, that the user input for the divider field is
not the desired divider, but the bitfield value that one would have to enter to achieve the desired divider.
Some divider blocks like FM_PER_CLK’s, provide a dropdown list with textbox description
underneath. Others support too many input values to be put into a list. The user must provide the proper
bitfield value, not the desired divisor. That is why such blocks are labelled something like
“/(1+(0…63))” rather than simply “/1…64”. The user provides a value between 0 and 63, to which the
hardware automatically adds 1 to calculate a divider that is between 1 and 64.
Tree also features two buttons, Reset and Max. They only function when macros are enabled. Clicking
on these buttons with macros disabled will return an error. If macros are enabled, the Reset button will
set all blocks to their reset value, as described in the reference manual. The Max button sets all blocks in
this tool to values that configure the system and auxiliary clock domains to their respective maximum
allowable frequencies. Below is a screenshot of the buttons.

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Figure 7. Buttons
2.2. Device select
The Device Select tab allows user to choose between MPC5777C_264MHz and MPC5777C_300MHz.
This changes the hardware specification table used by the MPC5777C Clock Calculator. For example,
if MPC5777C_300MHz is selected, PLL1_PHI will shade red starting at 300 MHz rather than 264 MHz.
The structure of the tool remains unchanged, though, since the two MPC5777C versions share the same
architecture, but with different operating speeds.
Figure 8. Device select

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2.3. Oscillator control
Oscillator Control controls the generation of the external oscillator (XOSC) frequency. MPC5777C
supports two ways of XOSC generation. The chip has two external oscillator pins, XTAL and EXTAL.
An 8-44 MHz external oscillator can be connected to both pins. This external oscillator is also referred
to simply as XTAL. If the XOSC Enable/Select block selects XTAL, XOSC will derive its frequency from
the external oscillator (XTAL) block. Alternatively, a waveform can be driven directly to the EXTAL
pin, also known as bypass mode. This signal is also referred to simply as EXTAL. When the XOSC
Enable/Select block selects EXTAL, XOSC will derive its frequency from the EXTAL pin. Shown below
is a screenshot of oscillator control.
Figure 9. Oscillator control
2.4. Peripheral domains
Peripheral Domains is an in-depth diagram of MPC5777C modules. Where Tree leaves off at the clock
domain level, Peripheral Domains picks up and progresses to the module level, as shown in the figure
below.

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Figure 10.Peripheral domains
The clock domains are color-coded. Black lines are reserved for clock domains that only a few modules
use. For example, many modules’ BIU clocks are filtered through a Halt block. The output of each Halt
block is colored black, since each only goes to at most a few modules. As a rule of thumb, clock
domains are represented with black lines if all modules using it can fit within a single window without
having to scroll. The frequencies on this tab are not meant to be modified and are dependent on
frequency values in the Tree tab.
2.5. FlexCAN clocking and MCAN clocking
Some modules have so many clock configuration possibilities that they warrant their own dedicated
sections, lest Peripheral Domains becomes too complicated. FlexCAN and MCAN uses their protocol
clocks to generate can message time segments. Domains still hosts FlexCAN and MCAN blocks that
show their input clocks and are hyperlinked to FlexCAN Clocking and MCAN Clocking, respectively,
as shown in the below figure.

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Figure 11.FlexCAN in Peripheral domains
FlexCAN clocking and MCAN clocking provides options to configure the bit time segments, as shown in
the figure below. The column on the right-hand side of the diagram shows the breakdown, in
nanoseconds, of a CAN bit time, as configured by the FlexCAN or MCAN.
Figure 12.FlexCAN clocking
2.6. LFAST clocking
The LFAST is the third module that has its own tab. It is a versatile, but intricate module that hosts its
own PLL which generates multiple phases and generates a signal within specification only if its inputs
are certain frequencies. These intricacies make it necessary to give LFAST its own dedicated tab.
LFAST clocking presents a block diagram of the module with various clocks going into it. It also
supports LFAST_PLL configuration to increase the LFAST frequency up to 480 MHz. The LFAST also

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supports a low-speed mode as well as a high-speed mode. This tool allows the user to select between
the two modes. Below is a screenshot of LFAST clocking.
Figure 13.LFAST block diagram
Since the LFAST signal must be generated from an input clock of 10 or 20 MHz, this tool blocks any
input from the signal RF_REF other than these two values. RF_REF can technically be set to any value,
but the signal goes through the clock calculator’s LFAST Input Filter block to become lfast_sys_clk,
which in turn is the signal that gets fed into the LFAST PLL and phase generators, as shown in the
following figure.
Figure 14.LFAST clocking input filter

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If RF_REF is 10 or 20 MHz, lfast_sys_clk is the same; otherwise, lfast_sys_clk is 0. MPC5777C does
not actually filter RF_REF the way this tool does. The purpose of the LFAST Input Filter block is to
simulate how the user can technically set RF_REF to any value, but the resulting LFAST output would
be unusable. Therefore, if a user were to enter an invalid input frequency (i.e. not 10 or 20 MHz), all
subsequent frequencies would be 0, and the user would know to change the input.
2.7. PLLx
PLL0 and PLL1 are visual abstractions of the PLL digital interface, as shown in the figure below.
Figure 15.PLL0 control
The input source of PLL0 and PLL1 are selected by the PLL0 Clock Selector and PLL1 Clock Selector
blocks in the Tree tab, respectively. Then, from the source, the dividers and multipliers located in the
PLL0 and PLL1 tabs are set in order to achieve the PLL output frequencies. The PLL output frequencies
are in turn propagated to the PLLx_PHIn clock domains in the Tree tab.
2.8. Reference tables (pll0_phi, pll0_phi1, and pll1_phi)
The three tabs pll0_phi, pll0_phi1, and pll1_phi are reference tables for the user to find the appropriate
PLL dividers and multipliers to achieve the desired PLL frequency. There is a tab for each PLL output
because input frequencies and the range of acceptable divider/multiplier values differ between each
other. However, they all follow the same setup. Note that Columns A, B, and C of these tabs are frozen
so if the table looks cut off, just scroll left or right.
PLL frequencies are calculated from a reference frequency, a reference divider (RFD), a multiplier
(MFD), and in PLL0, a prescaler (PREDIV). The PLL reference is not manually configurable because
there is a finite number of input values the PLL can take. For example, PLL0 can only reference either
the 16 MHz IRC or the 8-44 MHz XOSC. PLL reference therefore comes from the Tree tab. Configure
PLL0 Clock Selector and PLL1 Clock Selector in Tree for PLL0 and PLL1, respectively. Once the PLL
reference frequency is configured, enter the desired PLL output frequency. Also, enter the PREDIV
value when using PLL0_PHI or PLL0_PHI1. The reference table will then calculate the output
frequency for each MFD and RFD setting. Like in the other sections, frequencies are color-coded to
define which values are valid and which are not. Shading will change automatically once the output PLL
frequencies are calculated. MFD and RFD settings that achieve the exact desired frequency will be

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shaded in green; values that exceed the desired frequency, but are within MPC5777C hardware
specifications are marked in yellow; and frequencies that exceed the MPC5777C hardware specification
are colored red. Below is a screenshot of the reference table for PLL0_PHI.
Figure 16.PLL0_PHI Reference table
2.9. Summary
Almost all blocks populating this clock calculator represent real register fields in silicon. The Summary
tab collates all the information from the rest of the clock calculator into a list of register values, a
screenshot of which is shown in Figure 16. The values in the register summary are interactive, updating
automatically when the associated block is changed. Registers listed within Summary are only the ones
whose values are affected by clock configuration, not every single register available in the chip.

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Figure 17.Register summary table
The register values are displayed in either hexadecimal or binary format, where a “0x” prefix represents
hexadecimal and “0b” denotes binary. A capital “X” represents a “don’t care” bit/half-byte. These bits
do not affect the clock frequency, so users can set these values to whatever suits their purposes. Users
can best utilize Summary by setting the configuration they want in the clock calculator and then copying
the resulting register value into code. For example, taking from the figure above, the register
SIU_LFCLKCFG should be set to 0xX0002009. Assuming the instances of “X” are “0”, the resulting
S32DS C code would be: “SIU.LFCLKCFG.R = 0x00002009;”.
Summary also includes an overview of the clock domain frequencies. Since this tool consists of multiple
interdependent spreadsheets, it might be cumbersome for users to weave through them all to find a clock
domain. This table provides a place where all of them can be found. The table is organized by module,
followed by the clock type (i.e. BIU clock, peripheral clock, protocol clock, etc.), and finally the
frequency, as currently configured. Below is a screenshot of clock summary table.

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Figure 18.Clock summary table
This tool also supports a degree of code generation. Summary provides two sample clock initialization
functions, Sysclk_Init for configuring oscillators and PLLs and InitPeriClkGen for providing
sources/dividers to auxiliary clocks. The dynamic C code in these functions depend on tool settings just
like the register summary. These functions can be copied and pasted to a source file via Ctrl+C/Ctrl+V
or by clicking on the associated Copy Code button, if macros are enabled. The following figure shows
Sysclk_Init and its Copy Code button.

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Figure 19.Sample initialization code
2.10.Limits
Limits is the reference tab for all the color-coding and other rules. The values in its tables are based on
the MPC5777C’s datasheet and reference manual and should not be modified by the user. The following
figure is a screenshot of the Limits tab.

Clock tool example use case: Configure eMIOS to 60 MHz PLL1 with MPC5777C_264MHz
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Figure 20.MPC5777C Frequency limits
3.Clock tool example use case: Configure eMIOS to 60
MHz PLL1 with MPC5777C_264MHz
The following sections presents an example application of the MPC5777C Clock Calculator. This
application note’s example will configure eMIOS0’s clocks to 60 MHz. The example will not only show
the correct configurations but also how the tool responds if improper configurations are attempted.
When configuring clocks for a module, start at Peripheral Domains. As shown in the following figure,
eMIOS0 follows only PER_CLK for both the bus interface unit and module clock.

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Figure 21.eMIOS0 clocks
PER_CLK is currently 8 MHz. If a module uses multiple clock domains, configuring the clock
calculator can be done in any order.
3.1. Select the device
First choose the correct the device. Go to Device Select and set the device to MPC5777C_264MHz.
This ensures that the MPC5777C Clock Calculator will use the spec sheet corresponding to the 264
MHz variant.

Clock tool example use case: Configure eMIOS to 60 MHz PLL1 with MPC5777C_264MHz
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Figure 22.Selecting MPC5777C_264 MHz
3.2. Configure PER_CLK
Click on PER_CLK to forward to the PER_CLK cell of Tree, shown below.
Figure 23.PER_CLK, Tree tab
Trace PER_CLK all the way back to its point of origin. As shown in the figure, PER_CLK is sourced
from the 16 MHz CORE_CLK and divided by 2, hence 8 MHz. The cell is a drop-down menu and the

Clock tool example use case: Configure eMIOS to 60 MHz PLL1 with MPC5777C_264MHz
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textbox explains what each available value represents. As shown in the figure, CORE_CLK,in turn, is
currently sourced from the 16 MHz IRC, divided by 1, for a final frequency of 16 MHz.
Since the only way to achieve 60 MHz is through the PLL, one of the PLLs must be configured. This
example will choose PLL1. Trace PLL1_PHI back to its own sources. PLL1 selects from either XOSC
or PLL0_PHI1 via PLL1 Clock Selector. These oscillators are the point of origin for all clock domains.
The figure below shows PER_CLK being traced back to PLL1 and then finally to the oscillators.
Figure 24.PER_CLK to oscillators
3.2.1. Configure the oscillator
Now start going downstream, configuring from the oscillator down to PER_CLK. The external oscillator
frequency is application-dependent and can be any value between 8 MHz and 40 MHz. This tool has a
safeguard to prevent invalid values from being entered. The Figure23 shows an attempt to enter 7 MHz
to the XOSC frequency cell. A dialog box appears notifying the user that the value is not accepted when
he/she tries to click away from the cell.