NXP Semiconductors PN7462 series User manual

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Document information
Info
Content
Keywords
PN7462, PN7462 family, PN7362; PN7360; NFC reader
Abstract
This document describes how to use the PN7462 family.

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Contact information
For more information, please visit:
http://www.nxp.com
Revision history
Rev
Date
Description
1.4
20180514
Editorial updates
1.3
20180212
Reworking the document to describe complete PN7462 family
SDA hold equation added
1.2
20170908
GPIO wakeup condition corrected
Pull-up and pull-down configuration for SPIM pins corrected
CRC polynomial specified
1.1
20170216
Max enhanced ESD protection changed to 12 kV
Dynamic Power Control (DPC) added
1.0
20160225
Initial version

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1. Introduction
1.1 General description
The PN7462 family is a family of 32-bit ARM Cortex-M0-based NFC microcontrollers
offering high performance and low power consumption. It has a simple instruction set and
memory addressing along with a reduced code size compared to existing architectures.
PN7462 family offers an all in one solution, with features such as NFC, microcontroller,
optional contact smart card reader, and software in a single chip. It operates at CPU
frequencies of up to 20 MHz. The PN7462 family consists of six different products.
For more details on all products of the PN7462 family refer to the data sheet.
Having the differences listed in the table above, all products within the PN7462 family are
equipped with 12 kB of SRAM data memory and 4 kB EEPROM. All products within the
family also include one host interface with either high-speed mode I2C-bus, SPI, USB or
high-speed UART, and two master interfaces, SPI and Fast-mode Plus I2C-bus. Four
general-purpose counter/timers, a random number generator, one CRC coprocessor and
up to 21 general-purpose I/O pins.
The PN7462 family NFC microcontroller offers a one chip solution to build contactless, or
contact and contactless applications. It is equipped with a highly integrated high-power
output NFC-IC for contactless communication at 13.56 MHz enabling EMV-compliance
on RF level, without additional external active components.
PN7462 family supports the following operating modes:
•read/write mode supporting ISO/IEC 1443A and MIFARE ICs
•JIS X 6319-4 (comparable with FeliCa scheme)
•ISO/IEC 15693, ICODE, ISO/IEC 18000-3 mode 3
•NFC protocols - tag reader/writer, P2P
•ISO/IEC 14443- type A card emulation
•EMVCo compliance
In this document the term „MIFARE Classic card“ refers to a MIFARE Classic IC-based
contactless card and the term „MIFARE Plus card“ refers to a MIFARE Plus IC-based
contactless card.

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1.2 Features and benefits
1.2.1 Integrated contact interface front-end
This chapter applies to the products with contact interface only.
•Class A, B, and C cards can work on 1.8 V, 3 V, and 5 V supply
•Specific ISO UART, variable baud rate through frequency or division ratio
programming, error management at character level for T = 0, and extra guard
time register
•DC-to-DC converter for class A support starting at 3 V, and class B support
starting at 2.7 V
•Thermal and short-circuit protection on contact cards
•Automatic activation and deactivation sequence, initiated by software or by
hardware in case of short-circuit, card removal, overheating, and VDD or VDD
drop-out
•Enhanced ESD protection (> 12 kV)
•ISO/IEC 7816 compliant
•EMVCo 4.3 compliant
•Clock generation up to 13.56 MHz
•Synchronous card support
•Possibility to extend the number of contact interfaces, with the addition of slot
extenders such as TDA8026
1.2.2 Integrated ISO/IEC 7816-3&4 UART interface
This chapter applies to the products with Integrated ISO/IEC 7816 UART interface
only.
The PN7462 family offers the possibility to extend the number of contact interfaces
available. It uses an I/O auxiliary interface to connect a slot extension (TDA8035 - 1 slot,
TDA8020 - 2 slots, and TDA8026 - 5 slots).
•Class A (5 V), class B (3 V), and class C (1.8 V) smart card supply
•Protection of smart card
•Three protected half-duplex bidirectional buffered I/O lines (C4, C7, and C8)
•Compliant with ISO/IEC 7816 and EMVCo 4.3 standards
1.2.3 Integrated contactless interface front end
•High RF output power frontend IC for transfer speeds up to 848 kbit/s
•NFC IP1 and NPFC IP2 support
•Full NFC Tag support (Type 1, Type 2, Type 3, Type 4 A and B)
•P2P active and passive, target and initiator
•Card emulation ISO14443 type A

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•ISO/IEC 14443 Type A and B
•Support for MIFARE Classic card
•ISO/IEC 15693 and ISO/IEC 18000-3 mode 3
•iClass serial number support
•Low power card detection function
•Compliance with EMV Contactless protocol specification
•Compliance with NFC standard
1.2.4 Cortex M0 microcontroller
•Processor core
−32-bit ARM cortex M0 processor
−Built-in Nested Vectored Interrupt Controller (NVIC)
−Non-maskable interrupt
−System Tick Timer 24 bits
−Running frequency up to 20 MHz
−Clock management to enable low power consumption
•Memory
−Flash: 160 kB
−RAM: 12 kB
−EEPROM: 4 kB
−40 K boot ROM included, including USB mass storage primary boot loader for
code download.
•Debug Option
−Serial Wire Debug interface (SWD)
•Master Interfaces:
−SPI half-duplex, up to 6.78 Mbit/s
−I²C supporting fast mode plus, and clock stretching
•Host Interfaces
−HSUART for serial communication, supporting standards speeds from 9600 to
115200 bps, and faster speed up to 1.288 Mbit/s
−SPI half-duplex and full duplex, up to 7 Mbit/s
−I²C Host supporting standard, fast and high-speed mode with multiple address
support
−USB 2.0 full speed, with USB 3.0 hub connection capability
•Up to 21 General-Purpose I/O (GPIO) with configurable pull-up/pull-down resistors
•GPIOs 1 to 12 can be used as edge and level sensitive interrupt sources
•Power
−Two reduced power modes: Sleep mode and hard power down mode

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−Suspend mode for USB host interface
−Processor wake-up from hard power down mode, stand-by mode, suspend mode
via: host interface, contact card interface, GPIOs, RF field detection
−Integrated PMU to automatically adjust internal regulators, to minimize the power
consumption during all possible power modes.
−Power-on reset
−RF supply; external, or using an integrated LDO (TXLDO configurable with 3 V,
3.3 V, 3.6 V, 4.5 V, and 4.75 V)
−Pad voltage supply: external 3.3 V or 1.8 V, or using an integrated LDO (3.3 V
supply)
−Integrated contact interface voltage regulation for 1.8 V, 3 V, and 5 V card supply,
including a DC-to-DC converter for support of Class A and Class B cards
•Timers
−Four general-purpose timers
−Programmable WatchDog Timer (WDT)
•CRC coprocessor
•Random number generator
•Clocks
−Crystal oscillator 27.12 MHz
−Dedicated PLL 48 MHz for the USB
−Integrated HFO 20 MHz and LFO 380 kHz
•General
−HVQFN64 packaging
−Temperature range: -40 °C to 85 °C
1.3 Derivates
1.3.1 PN7462AUEV features
Supports all PN7462AU features except ISO 7816 contact interface pins not exposed
(AUX pins still available)
1.3.2 PN7362AU features
Supports all PN7462AU features except ISO 7816 interface
1.3.3 PN7360AU features
Supports all PN7462AU features except ISO 7816 interface and reduced flash size
(80kB)

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1.4 Ordering information
Table 1. Ordering information
Type Number
Package
Name
Description
Version
PN7462AUHN
HVQFN64
160 kB memory; contact interface; ISO/IEC 7816-3&4
UART interface;
plastic thermal enhanced very thin quad flat package; no
leads; 64 terminals; body 9 × 9 × 0.85 mm
SOT804-4
PN7462AUEV
VFBGA64
160 kB memory; no contact interface; ISO/IEC
7816-3&4 UART interface;
plastic very thin fine-pitch ball grid array package; 64
balls; 4.5 mm x 4.5 mm x 0.80 mm
SOT1307-2
PN7362AUHN
HVQFN64
160 kB memory; no contact interface; no ISO/IEC
7816-3&4 UART interface;
plastic thermal enhanced very thin quad flat package; no
leads; 64 terminals; body 9 × 9 × 0.85 mm
SOT804-4
PN7362AUEV
VFBGA64
160 kB memory; no contact interface; no ISO/IEC
7816-3&4 UART interface;
plastic very thin fine-pitch ball grid array package; 64
balls; 4.5 mm x 4.5 mm x 0.80 mm
SOT1307-2
PN7360AUHN
HVQFN64
80 kB memory; no contact interface; no ISO/IEC
7816-3&4 UART interface;
plastic thermal enhanced very thin quad flat package; no
leads; 64 terminals; body 9 × 9 × 0.85 mm
SOT804-4
PN7360AUEV
VFBGA64
80 kB memory; no contact interface; no ISO/IEC
7816-3&4 UART interface;
plastic very thin fine-pitch ball grid array package; 64
balls; 4.5 mm x 4.5 mm x 0.80 mm
SOT1307-2

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1.5 Block diagram PN7462 HVQFN64
Fig 1. Block diagram

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1.6 Block diagram PN7462 VFBGA64
Fig 2. Block diagram

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1.7 Block diagram PN736X
Fig 3. Block diagram

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2. PN7462 family memory
2.1 Memory mapping
The PN7462 family incorporates several distinct memory regions. Fig 4 shows the overall
map of the entire address space from user program viewpoint following reset. The APB
peripheral area is 512 K in size, and is divided to allow for up to 32 peripherals. Only
peripheral from 0 to 15 are accessible, and each one is allocated 16 kB of space, in order
to simplify the address decoding for each peripheral. The APB peripheral memory map is
shown on the right side of Fig 4.
Fig 4. PN7462 family Memory map

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Fig 5. APB memory map

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2.2 On-chip flash memory map
The PN7462 family contains 160 kB or 80 kB(PN7360) on-chip flash program memory.
The flash can be programmed using In-System Programming (ISP) or In-Application
Programming (IAP) via the on-chip boot-loader software.
The flash memory is divided into two instances of 80 kB, with each sector consisting of
individual pages of 64 Bytes. The flash memory map is described in Fig 6.
Fig 6. Flash memory mapping

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2.3 EEPROM memory map
The PN7462 family embeds 4 kB of on-chip EEPROM data memory. The EEPROM
memory map is shown in Fig 7.
Fig 7. EEPROM memory mapping

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2.4 SRAM memory map
The PN7462 family contains a total of 12 kB on-chip static RAM memory. The SRAM
memory map is presented in Fig 8.
Fig 8. SRAM memory mapping

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3. EEPROM CTRL module
The EEPROM controller module controls the access to 4 kB EEPROM and 160 kB On-
chip Flash memories. This comprises:
•Reading the content of an EEPROM or Flash word in response to a read-transfer
coming from the CPU
•Writing a word (8 ,16 and 32-bit word length transfer allowed for EEPROM, only 32-bit
allowed for flash) in page file upon a write-transfer coming from the CPU (Full page
has to be written for flash)
•Programming the Flash, meaning copying the content of the page into the relevant
EEPROM/flash
•Implementing security bits (at boot time the EEPROM first word is read. Part of those
bits are controlling the Flash access and the CMB enabling. These bits are available in
a register). Fig 9 shows the block diagram EEPROM/flash controller module
Fig 9. Block diagram of EEPROM/FLASH controller module
3.1 EEPROM/Flash controller features
•Three non-volatile memory ports: two for 80 x 2 kB of flash and one for a 4 kB of
EEPROM
•32-bit AHB-Lite slave interface with the CPU
•Read prefetching for flash memory to speed up reading from flash.
•Interrupt Request Device
•Register bank for control and status with user mode protection

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•2.8 ms maximum to write a page on the EEPROM, with a max. power consumption of
2 mA
•2.5 ms to write a page on the Flash in typical condition
•1.03 ms to write a page on the Flash with maximum clock speed, with a max. power
consumption of 3 mA
•Test support Unit with CRC computation of the EEPROM and flash content
3.2 AHB interface
AMBA 3 AHB Lite slave interface is implemented to connect the CPU to the EECTRL.
The wait states are inserted with individual length for a read or write access.
3.3 Memory map
The memory map for the EECTRL module is divided into four parts:
•0x0020_0000 - 0x0020_0FFF - EECTRL registers area
•0x0020_1000 - 0x0020_1FFF - 4 kBytes DATA EEPROM Area
•0x0020_2000 - 0x0020_2FFF - UNDEFINED area
•0x0020_3000 - 0x0022_AFFF - 160 kBytes flash area
3.4 EEPROM controller
3.4.1 Write operation
Write operation cannot be handled within one AHB clock cycle, therefore wait states are
inserted by the AHB Slave Interface during page register write phase. The following table
gives an overview of minimum idle time for a write operation. The EEPROM controller
programs the data page by page. A page register for write access is used to internally
store the data in a quick way and then a programming cycle can start. The targeted
EEPROM is 16-bit oriented so 32-bit write access need additional processing to combine
two 16-bit access leading to additional wait states.
Table 2. Wait states for write access on EEPROM
Address
width
Wait states FAST mode
Wait states SLOW mode
AHB
clock cycles
20 MHz Clock
AHB
clock cycles
20 MHz Clock
32-bit
5
250 ns
7
350 ns
8/16-bit
2
100 ns
3
150 ns
The Write operation to the EEPROM has to be done in two steps:
1. Write the 64-Byte short term storage page register.
2. Program the page register in one row of the EEPROM matrix.

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3.4.2 Read operation
A read request cannot be handled within one AHB clock cycle, therefore wait states are
inserted by the AHB Slave Interface. The targeted EEPROM is 16-bit oriented so 32-bit
Read access need additional processing leading to additional wait states. Table 3gives
an overview of minimum idle time for a read operation.
Table 3. Wait states for read access on EEPROM
Address Width
Wait states FAST mode
Wait states SLOW mode
AHB clock
cycles
20 MHz clock
AHB clock
cycles
20 MHz clock
32-bit
5
250 ns
7
350 ns
8/16-bit
2
100 ns
3
150 ns
3.5 Flash controller
The Flash is composed of two memory devices respectively controlled by one Flash
controller integrated twice in the EECTRL module. The main difference to the EEPROM
is a faster read access and a full-page programming.
3.5.1 Write operation
Write Access is done only with 32-bit access. A write operation cannot be handled within
one AHB clock cycle, therefore wait states are inserted by the AHB Slave Interface
during page register write phase. The following table gives an overview of minimum idle
time for a write operation. The Flash controllers program the Flash_0 and Flash_1 data
page by page.
A page register for write access is used to internally store the data in a quick way and
then a programming cycle is necessary to store the data.
Flash_0 stores data corresponding to «even» AHB addresses with bit [2] = ’0’ and
Flash_1 stores data corresponding to «odd» AHB addresses with bit [2] = ’1’.
Table 4. Wait states for write access on EEPROM
Address Width
Wait states FAST mode
Wait states SLOW mode
AHB clock
cycles
ns (20 MHz clock)
AHB clock
cycles
ns (20 MHz clock)
32-bit access
2
100
3
150
A write operation to the Flash has to be done in two steps:
1. Write the 64-Byte short term storage page register.
2. Program the page register in one row of the Flash matrix.
3.5.2 Read Operation
Even if 32-bit, 16-bit and 8-bit Read Access are supported at system level, read access
is only done with 32-bit accesses at memory level because the Flash is 32-bit oriented.
The read access is similar as for the EEPROM.
The following table gives idle time with AHB wait states insertion for a read operation

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Table 5. Wait states for read access on EEPROM
Address
Width
Wait states FAST mode
Wait states SLOW mode
AHB
clock cycles
ns
(20 MHz Clock)
AHB
clock cycles
ns
(20 MHz Clock)
32- bit access
2
100
3
150
3.6 Register overview
Table 6. Clock generator register overview
Name
Address
offset
Width
(bits)
Access
Reset value
Description
EE_CTRL
0000h
32
R/W
001F_0000h
EECTRL general control register
EE_DYN
0004h
32
W
0000_0000h
EECTRL dynamic control register
EE_STAT_DAT
0008h
32
R
0X00_0000h
EEPROM status register
EE_STAT_COD
000Ch
32
R
0000_0000h
FLASH status register
EE_CRC_DAT
0010h
32
R
FFFF_FFFFh
EEPROM CRC value
EE_CRC_DAT_ADDR
0014h
32
R/W
0FFF_0000h
EEPROM CRC start/end
Addresses
EE_CRC_1_COD_INIT
0018h
32
R/W
FFFF_FFFFh
FLASH
_1 CRC init value
EE_CRC_1_COD
001Ch
32
R
FFFF_FFFFh
FLASH_1 CRC value
EE_CRC_1_COD_ADDR
0020h
32
R/W
4FFF_0000h
FLASH_1 CRC start/end address
EE_CRC_0_COD_INIT
0024h
32
R/W
FFFF_FFFFh
FLAH_0 CRC Init value
EE_CRC_0_COD
0028h
32
R
FFFF_FFFFh
FLASH_0 CRC value
EE_CRC_0_COD_ADDR
002Ch
32
R/W
4FFF_0000h
FLASH_0 CRC start/end
Addresses
RESERVED
0030h
32
R/W
0000_0000h
Reserved
RESERVED
0034h
32
R/W
0000_0000h
Reserved
RESERVED
0038h
32
R/W
0000_0000h
Reserved
EE_TRIMM
003Ch
32
R/W
0000_0000h
EEPROM/PFLASH trimming
values
RESERVED
0040h
32
R
6000_01ACh
Reserved
EE_ECC_PF_AHB_ERROR_ADD
R
0044h
32
R
0000_0000h
FLASH ECC Error address
Unused
0048h
-
0FD4h
32
-
-
Unused
EE_INT_CLR_ENABLE
0FD8h
32
W
0000_0000h
Interrupt CLR_ENABLE
commands
EE_INT_SET_ENABLE
0FDCh
32
W
0000_0000h
Interrupt SET_ENABLE
commands
EE_INT_STATUS
0FE0h
32
R
0000_0000h
Interrupt STATUS commands
EE_INT_ENABLE
0FE4h
32
R
0000_0000h
Interrupt ENABLE commands

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Name
Address
offset
Width
(bits)
Access
Reset value
Description
EE_INT_CLR_STATUS
0FE8h
32
W
0000_0000h
Interrupt CLR_STATUS
commands
EE_INT_SET_STATUS
0FECh
32
W
0000_0000h
Interrupt SET_STATUS
commands
3.7 Register description
Table 7. EE_CTRL (address offset 0x0000h)
Bit
Symbol
Access
Value
Description
31:16
RESERVED
-
0
Reserved
15
ECC_PF_AHB_ERROR_ENABLE
R/W
0
when ’1’ enables the AHB error
generation when FLASH read data cannot
be corrected by the ECC mechanism and
automatically set the FAST_COD bit to ’0’
to put the FLASH in slow mode.
14
PFLASH_READ_PREFETCH_DI
S
R/W
0
When ’1’ disables read prefetching for the
Flash memories
13
BLOCK_1_COD
R/W
0
Block mode for FLASH_1
12
BNWSENS_1_COD
R/W
0
voltage drop sensor enable for FLASH_1
11
SKIPPRG_1_COD
R/W
0
skip program if erase fails for FLASH_1
10
STOP_1_COD
R/W
0
stop ramp-up at low power for FLASH_1
9
PFLASH_DOUT_SYNCHRO_DI
S
R/W
0
when ’0’ output PAGEFLASH data is
synchronized with the system clock to
ensure that following ECC calculation is
made on stable data. It is automatically
set to ’1’ if FAST_COD = ’1’.
8
POWER_DOWN_1_COD
R/W
0
power down FLASH_1 block
7
BLOCK_0_COD
R/W
0
block mode for FLASH_0
6
BNWSENS_0_COD
R/W
0
voltage drop sensor enable for FLASH_0
5
SKIPPRG_0_COD
R/W
0
skip program if erase fails for FLASH_0
4
STOP_0_COD
R/W
0
stop ramp-up at low power for FLASH_0
3
FAST_COD
R/W
0
fast access for both FLASH_0 and
FLASH_1. It is automatically set to ’0’ if
EE_CTRL.ECC_PF_AHB_ERROR_ENAB
LE register is set to ’1’
2
POWER_DOWN_0_COD
R/W
0
power down FLASH block
1
FAST_DAT
R/W
0
fast EEPROM data access
0
power_down_dat
R/W
0
power down EEPROM block
Table 8. EE_DYN (address offset 0x0004h)
Bit
Symbol
Access
Value
Description
31:24
RESERVED
-
0
Reserved