NXP Semiconductors LPC800 User manual

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UM10601
LPC800 User manual
Rev. 1.0 — 7 November 2012 Preliminary user manual
Document information
Info Content
Keywords ARM Cortex M0+, LPC800, USART, I2C, LPC810M021FN8,
LPC811M001FDH16, LPC812M101FDH16, LPC812M101FD20,
LPC812M101FDH20
Abstract LPC800 Preliminary user manual

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UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Preliminary user manual Rev. 1.0 — 7 November 2012 2 of 313
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NXP Semiconductors UM10601
LPC800 User manual
Revision history
Rev Date Description
1 20121107 Preliminary LPC800 user manual

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UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Preliminary user manual Rev. 1.0 — 7 November 2012 3 of 313
1.1 Introduction
The LPC800 are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at
CPU frequencies of up to 30 MHz. The UM10601 support up to 16 kB of flash memory
and 4 kB of SRAM.
The peripheral complement of the UM10601 includes a CRC engine, one I2C-bus
interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up
timer, and state-configurable timer, one comparator, function-configurable I/O ports
through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O
pins.
1.2 Features
•System:
–ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz.
–ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
–Micro Trace Buffer
–System tick timer
•Memory:
–16 kB on-chip flash programming memory.
–4 kB SRAM.
–In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
boot loader software.
•Boot ROM API support:
–UART drivers
–I2C drivers
–Power profiles
–IAP/ISP
•Digital peripherals:
–High-speed GPIO interface connected to the ARM Cortex-M0+ I/O port with up to
18 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.
–Pin interrupt generation capability with boolean pattern-matching feature onup to
eightselectable GPIO inputs.
–Switch matrix for flexible configuration of each I/O pin function.
–State Configurable Timer (SCT) with input and output functions (including capture
and match) assigned to pins through the switch matrix.
–Multiple-channel multi-rate timer for repetitive interrupt generation at up to four
programmable, fixed rates.
–Wake-up timer for self-timed wake-up from reduced power modes.
UM10601
Chapter 1: LPC800 Introductory information
Rev. 1.0 — 7 November 2012 Preliminary user manual

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NXP Semiconductors UM10601
Chapter 1: LPC800 Introductory information
–CRC engine.
–Windowed Watchdog timer
•Analog peripherals:
–Comparator with external voltage reference with pin functions assigned through
the switch matrix.
–Internal reference voltage.
•Serial interfaces:
–Three UART interfaces with pin functions assigned through the switch matrix.
–Two SPI controllers with pin functions assigned through the switch matrix.
–One I2C-bus interface with open-drain full I2C spec fast Modeplus.
•Clock generation:
–12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used
as a system clock.
–Crystal oscillator with an operating range of 1 MHz to 25 MHz.
–Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.
–PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the external clock input (CLKIN), the
system oscillator, or the internal RC oscillator.
•Power control:
–Integrated PMU (Power Management Unit) to minimize power consumption.
–Reduced power modes (Sleep, deep-sleep, power-down, deep power-down).
–Power-On Reset (POR).
–Brownout detect.
•Unique device serial number for identification.
•Single power supply.
•Available in a SO20 package, TSSOP20 package, TSSOP16, and DIP8 package.

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NXP Semiconductors UM10601
Chapter 1: LPC800 Introductory information
1.3 Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
LPC810M021FN8 DIP8 plastic dual in-line package; 8 leads (300 mil) SOT097-2
LPC811M001FDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
LPC812M101FDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
LPC812M101FD20 SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
LPC812M101FDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
Table 2. Ordering options
Type number Flash/kB SRAM/kB USART I2CSPI Comparator GPIO Package
LPC810M021FN8 4 1 2 1 1 1 6 DIP8
LPC811M001FDH16 8 2 2 1 1 1 14 TSSOP16
LPC812M101FDH16 16 4 3 1 2 1 14 TSSOP16
LPC812M101FD20 16 4 2 1 1 1 18 SO20
LPC812M101FDH20 16 4 3 1 2 1 18 TSSOP20

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Preliminary user manual Rev. 1.0 — 7 November 2012 6 of 313
NXP Semiconductors UM10601
Chapter 1: LPC800 Introductory information
1.4 Block diagram
Fig 1. LPC800 block diagram
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Preliminary user manual Rev. 1.0 — 7 November 2012 7 of 313
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Chapter 1: LPC800 Introductory information
1.5 General description
1.5.1 ARM Cortex-M0+ core configuration
The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz. Integrated in
the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints.
The ARM Cortex-M0+ core supports a single-cycle I/O enabled port (IOP) for fast GPIO
access at address 0xA000 0000.
The core includes a single-cycle multiplier and a system tick timer (SysTick).

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2.1 How to read this chapter
The memory mapping is identical for all LPC800 parts. Different LPC800 parts support
different flash memory sizes.
2.2 General description
The LPC800 incorporates several distinct memory regions. Figure 2 shows the overall
map of the entire address space from the user program viewpoint following reset.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral is allocated 16 kB of space simplifying the address decoding.
The registers incorporated into the ARM Cortex-M0+ core, such as NVIC, SysTick, and
sleep mode control, are located on the private peripheral bus.
The GPIO port and pin interrupt/pattern match registers are accessed by the ARM
Cortex-M0+ single-cycle I/O enabled port (IOP).
UM10601
Chapter 2: LPC800 Memory mapping
Rev. 1.0 — 7 November 2012 Preliminary user manual

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Preliminary user manual Rev. 1.0 — 7 November 2012 9 of 313
NXP Semiconductors UM10601
Chapter 2: LPC800 Memory mapping
2.2.1 Memory mapping
2.2.2 Micro Trace Buffer (MTB)
The LPC800 supports the ARM Cortex-M0+ Micro Trace Buffer.
The private peripheral bus includes the ARM Cortex-M0+ peripherals such as the NVIC, SysTick, and the core control registers.
Fig 2. LPC800 Memory mapping
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UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
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3.1 How to read this chapter
The NVIC is identical on all LPC800 parts.
The SPI1 and USART2 interrupts are implemented on parts LPC812M101FDH20 and
LPC812M101FDH16 only.
3.2 Features
•Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0+.
•Tightly coupled interrupt controller provides low interrupt latency.
•Controls system exceptions and peripheral interrupts.
•The NVIC supports 32 vectored interrupts.
•Four programmable interrupt priority levels with hardware priority level masking.
•Software interrupt generation using the ARM exceptions SVCall and PendSV.
•Support for NMI.
•ARM Cortex M0+ Vector table offset register VTOR implemented.
3.3 General description
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0+. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
3.3.1 Interrupt sources
Tabl e 3 lists the interrupt sources for each peripheral function. Each peripheral device
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source. The interrupt number does not imply any
interrupt priority.
See Ref. 1 for a detailed description of the NVIC and the NVIC register description.
UM10601
Chapter 3: LPC800 Nested Vectored Interrupt Controller
(NVIC)
Rev. 1.0 — 7 November 2012 Preliminary user manual
Table 3. Connection of interrupt sources to the NVIC
Interrupt
number Name Description Flags
0 SPI0_IRQ SPI0 interrupt See Table 192 “SPI Interrupt Enable read and Set register
(INTENSET, addresses 0x4005 800C (SPI0) , 0x4005 C00C
(SPI1)) bit description”.
1 SPI1_IRQ SPI1 interrupt Same as SPI0_IRQ
2 - Reserved -

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Chapter 3: LPC800 Nested Vectored Interrupt Controller (NVIC)
3 UART0_IRQ USART0 interrupt See Tab l e 16 1 “ USART Interrupt Enable read and set register
(INTENSET, address 0x4006 400C(USART0), 0x4006 800C
(USART1), 0x4006 C00C(USART2)) bit description”
4 UART1_IRQ USART1 interrupt Same as UART0_IRQ
5 UART2_IRQ USART2 interrupt Same as UART0_IRQ
6 - Reserved -
7 - Reserved -
8 I2C0_IRQ I2C0 interrupt See Table 175 “Interrupt Enable Clear register (INTENCLR,
address 0x4005 000C) bit description”.
9 SCT_IRQ State configurable timer
interrupt
EVFLAG SCT event
10 MRT_IRQ Multi-rate timer interrupt Global MRT interrupt.
GFLAG0
GFLAG1
GFLAG2
GFLAG3
11 CMP_IRQ Analog comparator interrupt COMPEDGE - rising, falling, or both edges can set the bit
12 WDT_IRQ Windowed watchdog timer
interrupt
WARNINT - watchdog warning interrupt
13 BOD_IRQ BOD interrupts BODINTVAL - BOD interrupt level
14 FLASH_IRQ Flash interrupt <tbd>
15 WKT_IRQ Self wake-up timer interrupt ALARMFLAG
23:16 - Reserved -
24 PININT0_IRQ Pin interrupt 0 or pattern
match engine slice 0
interrupt
PSTAT - pin interrupt status
25 PININT1_IRQ Pin interrupt 1 or pattern
match engine slice 1
interrupt
PSTAT - pin interrupt status
26 PININT2_IRQ Pin interrupt 2 or pattern
match engine slice 2
interrupt
PSTAT - pin interrupt status
27 PININT3_IRQ Pin interrupt 3 or pattern
match engine slice 3
interrupt
PSTAT - pin interrupt status
28 PININT4_IRQ Pin interrupt 4 or pattern
match engine slice 4
interrupt
PSTAT - pin interrupt status
Table 3. Connection of interrupt sources to the NVIC
Interrupt
number Name Description Flags

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Chapter 3: LPC800 Nested Vectored Interrupt Controller (NVIC)
29 PININT5_IRQ Pin interrupt 5 or pattern
match engine slice 5
interrupt
PSTAT - pin interrupt status
30 PININT6_IRQ Pin interrupt 6 or pattern
match engine slice 6
interrupt
PSTAT - pin interrupt status
31 PININT7_IRQ Pin interrupt 7 or pattern
match engine slice 7
interrupt
PSTAT - pin interrupt status
Table 3. Connection of interrupt sources to the NVIC
Interrupt
number Name Description Flags

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4.1 How to read this chapter
The system configuration block is identical for all LPC800 parts. USART2 and SPI1 are
only available on parts LPC812M101FDH20 and LPC812M101FDH16 and the corresponding
clocks, reset, and wake-up control bits are reserved for all other parts.
4.2 Features
•Clock control
•Reset control
•Pin interrupt set-up
•Configuration of reduced power modes
•Wake-up control
•BOD configuration
4.3 Basic configuration
Configure the SYSCON block as follows:
•The SYSCON uses the CKIN, CLKOUT, RESET, and XTALIN/OUT pins. Configure
the pin functions through the switch matrix. See Section 4.4.
•No clock configuration is needed. The clock to the SYSCON block is always enabled.
By default, the SYSCON block is clocked by the IRC.
4.3.1 Set up the PLL
The PLL creates a stable output clock at a higher frequency than the input clock. If you
need a main clock with a frequency higher than the 12 MHz IRC clock, use the PLL to
boost the input frequency.
1. Power up the system PLL in the PDRUNCFG register.
Section 4.6.32 “Power configuration register”
2. Select the PLL input in the SYSPLLCLKSEL register. You have the following input
options:
–IRC: 12 MHz internal oscillator.
–System oscillator: External crystal oscillator using the XTALIN/XTALOUT pins.
–External clock input CLKIN. Select this pin through the switch matrix.
Section 4.6.8 “System PLL clock source select register”
3. Update the PLL clock source<tbd> in the SYSPLLCKUEN register.
Section 4.6.9 “System PLL clock source update register”
4. Configure the PLL M and N dividers.
Section 4.6.3 “System PLL control register”
UM10601
Chapter 4: LPC800 System configuration (SYSCON)
Rev. 1.0 — 7 November 2012 Preliminary user manual

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Chapter 4: LPC800 System configuration (SYSCON)
5. Wait for the PLL to lock by monitoring the PLL lock status.
Section 4.6.4 “System PLL status register”
4.3.2 Configure the main clock and system clock
The clock source for the registers and memories is derived from main clock. The main
clock can be sourced from the IRC at a fixed clock frequency of 12 MHz or from the PLL.
The divided main clock is called the system clock and clocks the core, the memories, and
the peripherals (register interfaces and peripheral clocks).
1. Select the main clock . You have the following options:
–IRC: 12 MHz internal oscillator (default).
–PLL output: You must configure the PLL to use the PLL output.
Section 4.6.10 “Main clock source select register”
2. Update the main clock source.
Section 4.6.11 “Main clock source update enable register”
3. Select the divider value for the system clock. A divider value of 0 disables the system
clock.
Section 4.6.12 “System clock divider register”
4. Select the memories and peripherals that are operating in your application and
therefore must have an active clock. The core is always clocked.
Section 4.6.13 “System clock control register”
4.3.3 Set up the system oscillator using XTALIN and XTALOUT
If you want to use the system oscillator with the LPC800, you need to assign the XTALIN
and XTALOUT pins, which connect to the external crystal, through the fixed-pin function in
the switch matrix. XTALIN and XTALOUT can only be assigned to pins PIO0_8 and
PIO0_9.
1. In the IOCON block,remove the pull-up and pull-down resistors in the IOCON
registers for pins PIO0_8 and PIO0_9.
2. In the switch matrix block, enable the 1-bit functions for XTALIN and XTALOUT.
3. In the SYSOSCCTRL register, disable the BYPASS bit and select the oscillator
frequency range according to the desired oscillator output clock.
Related registers:
Table 62 “PIO0_8 register (PIO0_8, address 0x4004 4038) bit description”
Table 61 “PIO0_9 register (PIO0_9, address 0x4004 4034) bit description”
Table 105 “Pin enable register 0 (PINENABLE0, address 0x4000 C1C0) bit description”
Table 10 “System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit
description”

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Chapter 4: LPC800 System configuration (SYSCON)
4.4 Pin description
The SYSCON inputs and outputs are assigned to external pins through the switch matrix.
See Section 9.3.1 “Connect an internal signal to a package pin”to assign the CLKOUT
function to a pin on the LPC800 package.
See Section 9.3.2 to enable the clock input, the oscillator pins, and the external reset
input.
4.5 General description
4.5.1 Clock generation
The system control block facilitates the clock generation. Except for the USART clock and
the clock to configure the glitch filters of the digital I/O pins, the clocks to the core and
peripherals run at the same frequency. The maximum clock frequency for LPC800 is 30
MHz. See Figure 3.
Table 4. SYSCON pin description
Function Direction Pin Description SWM register Reference
CLKOUT O any CLKOUT clock output. PINASSIGN8 Table 104
CLKIN I PIO0_1/ACMP_I2/CLKIN External clock input to the system
PLL. Disable the ACMP_I2 function
in the PINENABLE register.
PINENABLE0 Table 105
XTALIN I PIO0_8/XTALIN Input to the system oscillator. PINENABLE0 Table 105
XTALOUT O PIO0_9/XTALOUT Output from the system oscillator. PINENABLE0 Table 105
RESET I RESET/PIO0_5 External reset input PINENABLE0 Table 105

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Chapter 4: LPC800 System configuration (SYSCON)
4.5.2 Power control of analog components
The system control block controls the power to the analog components such as the
oscillators and PLL, the BOD, and the analog comparator. For details, see the following
registers:
Section 4.6.30 “Deep-sleep mode configuration register”
Section 4.6.3 “System PLL control register”
Section 4.6.6 “Watchdog oscillator control register”
Section 4.6.5 “System oscillator control register”
Fig 3. LPC800 clock generation
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Chapter 4: LPC800 System configuration (SYSCON)
4.5.3 Configuration of reduced power-modes
The system control block configures analog blocks that can remain running in the reduced
power modes (the BOD and the watchdog oscillator for safe operation) and enables
various interrupts to wake up the chip when the internal clocks are shut down in
Deep-sleep and Power-down modes. For details, see the following registers:
Section 4.6.32 “Power configuration register”
Section 4.6.29 “Start logic 1 interrupt wake-up enable register”
4.5.4 Reset and interrupt control
The peripheral reset control register in the system control register allows to assert and
release individual peripheral resets. See Tab l e 7.
Up to eight external pin interrupts can be assigned to any digital pin in the system control
block (see Section 4.6.27 “Pin interrupt select registers”).
4.6 Register description
All system control block registers reside on word address boundaries. Details of the
registers appear in the description of each function.
Reset values describe the content of the registers after the boot loader has executed.
All address offsets not shown in Tab le 5 are reserved and should not be written.
Table 5. Register overview: System configuration (base address 0x4004 8000)
Name Access Offset Description Reset value Reference
SYSMEMREMAP R/W 0x000 System memory remap 0x2 Tab l e 6
PRESETCTRL R/W 0x004 Peripheral reset control 0x0000 1FFF Tab l e 7
SYSPLLCTRL R/W 0x008 System PLL control 0 Tab l e 8
SYSPLLSTAT R 0x00C System PLL status 0 Tab l e 9
- - 0x010 Reserved - -
- - 0x014 Reserved - -
SYSOSCCTRL R/W 0x020 System oscillator control 0x000 Tab l e 10
WDTOSCCTRL R/W 0x024 Watchdog oscillator control 0x0A0 Ta b l e 11
- - 0x028 Reserved - -
- - 0x02C Reserved - -
SYSRSTSTAT R/W 0x030 System reset status register 0 Tabl e 12
SYSPLLCLKSEL R/W 0x040 System PLL clock source select 0 Tab l e 13
SYSPLLCLKUEN R/W 0x044 System PLL clock source update enable 0 Tabl e 1 4
MAINCLKSEL R/W 0x070 Main clock source select 0 Tabl e 15
MAINCLKUEN R/W 0x074 Main clock source update enable 0 Tab l e 16
SYSAHBCLKDIV R/W 0x078 System clock divider 1 Tab l e 17
SYSAHBCLKCTRL R/W 0x080 System clock control 0x1F Tab l e 1 8
UARTCLKDIV R/W 0x094 USART clock divider 0 Tab l e 19
- - 0x098 Reserved - -

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Chapter 4: LPC800 System configuration (SYSCON)
- - 0x09C Reserved - -
- - 0x0A0 -
0x0BC
Reserved - -
- - 0x0CC Reserved - -
CLKOUTSEL R/W 0x0E0 CLKOUT clock source select 0 Tab l e 20
CLKOUTUEN R/W 0x0E4 CLKOUT clock source update enable 0 Ta bl e 2 1
CLKOUTDIV R/W 0x0E8 CLKOUT clock divider 0 Tab l e 22
UARTFRGDIV R/W 0x0F0 USART fractional generator divider value 0 Tab l e 23
UARTFRGMULT R/W 0x0F4 USART fractional generator multiplier value 0 Tab le 2 4
EXTTRACECMD R/W 0x0FC External trace buffer command register 0 Tab l e 2 5
PIOPORCAP0 R 0x100 POR captured PIO status 0 user dependent Tab l e 26
- - 0x104 Reserved - -
IOCONCLKDIV6 R/W 0x134 Peripheral clock 6 to the IOCON block for
programmable glitch filter
0x0000 0000 Tab l e 27
IOCONCLKDIV5 R/W 0x138 Peripheral clock 5 to the IOCON block for
programmable glitch filter
0x0000 0000 Tab l e 27
IOCONCLKDIV4 R/W 0x13C Peripheral clock 4 to the IOCON block for
programmable glitch filter
0x0000 0000 Tab l e 27
IOCONCLKDIV3 R/W 0x140 Peripheral clock 3 to the IOCON block for
programmable glitch filter
0x0000 0000 Tab l e 27
IOCONCLKDIV2 R/W 0x144 Peripheral clock 2 to the IOCON block for
programmable glitch filter
0x0000 0000 Tab l e 27
IOCONCLKDIV1 R/W 0x148 Peripheral clock 1 to the IOCON block for
programmable glitch filter
0x0000 0000 Tab l e 27
IOCONCLKDIV0 R/W 0x14C Peripheral clock 0 to the IOCON block for
programmable glitch filter
0x0000 0000 Tab l e 27
BODCTRL R/W 0x150 Brown-Out Detect 0 Tab l e 28
SYSTCKCAL R/W 0x154 System tick counter calibration 0x0 Tab l e 29
- R/W 0x168 Reserved - -
IRQLATENCY R/W 0x170 IQR delay. Allows trade-off between interrupt
latency and determinism.
0x0000 0010 Tab l e 30
NMISRC R/W 0x174 NMI Source Control 0 Tab le 3 1
PINTSEL0 R/W 0x178 GPIO Pin Interrupt Select register 0 0 Tab l e 32
PINTSEL1 R/W 0x17C GPIO Pin Interrupt Select register 1 0 Ta b le 3 2
PINTSEL2 R/W 0x180 GPIO Pin Interrupt Select register 2 0 Tab le 3 2
PINTSEL3 R/W 0x184 GPIO Pin Interrupt Select register 3 0 Tab le 3 2
PINTSEL4 R/W 0x188 GPIO Pin Interrupt Select register 4 0 Tab le 3 2
PINTSEL5 R/W 0x18C GPIO Pin Interrupt Select register 5 0 Tab l e 32
PINTSEL6 R/W 0x190 GPIO Pin Interrupt Select register 6 0 Tab le 3 2
PINTSEL7 R/W 0x194 GPIO Pin Interrupt Select register 7 0 Tab le 3 2
STARTERP0 R/W 0x204 Start logic 0 pin wake-up enable register 0 Ta b l e 33
STARTERP1 R/W 0x214 Start logic 1 interrupt wake-up enable
register
0Tab l e 34
Table 5. Register overview: System configuration (base address 0x4004 8000) …continued
Name Access Offset Description Reset value Reference

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Chapter 4: LPC800 System configuration (SYSCON)
4.6.1 System memory remap register
The system memory remap register selects whether the exception vectors are read from
boot ROM, flash, or SRAM. By default, the flash memory is mapped to address 0x0000
0000. When the MAP bits in the SYSMEMREMAP register are set to 0x0 or 0x1, the boot
ROM or RAM respectively are mapped to the bottom 512 bytes of the memory map
(addresses 0x0000 0000 to 0x0000 0200).
4.6.2 Peripheral reset control register
The PRESETCTRL register allows software to reset specific peripherals. A zero in any
assigned bit in this register resets the specified peripheral. A 1 clears the reset and allows
the peripheral to operate.
PDSLEEPCFG R/W 0x230 Power-down states in deep-sleep mode 0xFFFF Tab l e 35
PDAWAKECFG R/W 0x234 Power-down states for wake-up from
deep-sleep
0xEDF0 Tab le 3 6
PDRUNCFG R/W 0x238 Power configuration register 0xEDF0 Ta b le 3 7
DEVICE_ID R 0x3F4 Device ID part dependent Tab l e 38
Table 5. Register overview: System configuration (base address 0x4004 8000) …continued
Name Access Offset Description Reset value Reference
Table 6. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit
description
Bit Symbol Value Description Reset
value
1:0 MAP System memory remap. Value 0x3 is reserved. 0x2
0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot
ROM.
0x1 User RAM Mode. Interrupt vectors are re-mapped to Static
RAM.
0x2 User Flash Mode. Interrupt vectors are not re-mapped and
reside in Flash.
31:2 - - Reserved -
Table 7. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit
description
Bit Symbol Value Description Reset
value
0 SPI0_RST_N SPI0 reset control 1
0 Assert the SPI0 reset.
1 Clear the SPI0 reset.
1 SPI1_RST_N SPI1 reset control 1
0 Assert the SPI1 reset.
1 Clear the SPI1 reset.
2 UARTFRG_RST_N USART fractional baud rate generator
(UARTFRG) reset control
1
0 Assert the UARTFRG reset.
1 Clear the UARTFRG reset.

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Chapter 4: LPC800 System configuration (SYSCON)
4.6.3 System PLL control register
This register connects and enables the system PLL and configures the PLL multiplier and
divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various
clock sources. The input frequency is multiplied to a higher frequency and then divided
down to provide the actual clock used by the CPU, peripherals, and memories. The PLL
can produce a clock up to the maximum allowed for the CPU.
3 USART0_RST_N USART0 reset control 1
0 Assert the USART0 reset.
1 Clear the USART0 reset.
4 UART1_RST_N USART1 reset control 1
0 Assert the USART reset.
1 Clear the USART1 reset.
5 UART2_RST_N USART2 reset control 1
0 Assert the USART2 reset.
1 Clear the USART2 reset.
6 I2C_RST_N I2C reset control 1
0 Assert the I2C reset.
1 Clear the I2C reset.
7 MRT_RST_N Multi-rate timer (MRT) reset control 1
0 Assert the MRT reset.
1 Clear the MRT reset.
8 SCT_RST_N SCT reset control 1
0 Assert the SCT reset.
1 Clear the SCT reset.
9 WKT_RST_N Self wake-up timer (WKT) reset control 1
0 Assert the WKT reset.
1 Clear the WKT reset.
10 GPIO_RST_N GPIO and GPIO pin interrupt reset control 1
0 Assert the GPIO reset.
1 Clear the GPIO reset.
11 FLASH_RST_N Flash controller reset control 1
0 Assert the flash controller reset.
1 Clear the flash controller reset.
12 ACMP_RST_N Analog comparator reset control 1
0 Assert the analog comparator reset.
1 Clear the analog comparator controller reset.
31:12 - - Reserved -
Table 7. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit
description
Bit Symbol Value Description Reset
value