NXP Semiconductors LPC800 User manual

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UM10601
LPC800 User manual
Rev. 1.0 — 7 November 2012 Preliminary user manual
Document information
Info Content
Keywords ARM Cortex M0+, LPC800, USART, I2C, LPC810M021FN8,
LPC811M001FDH16, LPC812M101FDH16, LPC812M101FD20,
LPC812M101FDH20
Abstract LPC800 Preliminary user manual

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UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Preliminary user manual Rev. 1.0 — 7 November 2012 2 of 313
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NXP Semiconductors UM10601
LPC800 User manual
Revision history
Rev Date Description
1 20121107 Preliminary LPC800 user manual

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UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Preliminary user manual Rev. 1.0 — 7 November 2012 3 of 313
1.1 Introduction
The LPC800 are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at
CPU frequencies of up to 30 MHz. The UM10601 support up to 16 kB of flash memory
and 4 kB of SRAM.
The peripheral complement of the UM10601 includes a CRC engine, one I2C-bus
interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up
timer, and state-configurable timer, one comparator, function-configurable I/O ports
through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O
pins.
1.2 Features
•System:
–ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz.
–ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
–Micro Trace Buffer
–System tick timer
•Memory:
–16 kB on-chip flash programming memory.
–4 kB SRAM.
–In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
boot loader software.
•Boot ROM API support:
–UART drivers
–I2C drivers
–Power profiles
–IAP/ISP
•Digital peripherals:
–High-speed GPIO interface connected to the ARM Cortex-M0+ I/O port with up to
18 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.
–Pin interrupt generation capability with boolean pattern-matching feature onup to
eightselectable GPIO inputs.
–Switch matrix for flexible configuration of each I/O pin function.
–State Configurable Timer (SCT) with input and output functions (including capture
and match) assigned to pins through the switch matrix.
–Multiple-channel multi-rate timer for repetitive interrupt generation at up to four
programmable, fixed rates.
–Wake-up timer for self-timed wake-up from reduced power modes.
UM10601
Chapter 1: LPC800 Introductory information
Rev. 1.0 — 7 November 2012 Preliminary user manual

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Preliminary user manual Rev. 1.0 — 7 November 2012 4 of 313
NXP Semiconductors UM10601
Chapter 1: LPC800 Introductory information
–CRC engine.
–Windowed Watchdog timer
•Analog peripherals:
–Comparator with external voltage reference with pin functions assigned through
the switch matrix.
–Internal reference voltage.
•Serial interfaces:
–Three UART interfaces with pin functions assigned through the switch matrix.
–Two SPI controllers with pin functions assigned through the switch matrix.
–One I2C-bus interface with open-drain full I2C spec fast Modeplus.
•Clock generation:
–12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used
as a system clock.
–Crystal oscillator with an operating range of 1 MHz to 25 MHz.
–Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.
–PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the external clock input (CLKIN), the
system oscillator, or the internal RC oscillator.
•Power control:
–Integrated PMU (Power Management Unit) to minimize power consumption.
–Reduced power modes (Sleep, deep-sleep, power-down, deep power-down).
–Power-On Reset (POR).
–Brownout detect.
•Unique device serial number for identification.
•Single power supply.
•Available in a SO20 package, TSSOP20 package, TSSOP16, and DIP8 package.

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UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Preliminary user manual Rev. 1.0 — 7 November 2012 5 of 313
NXP Semiconductors UM10601
Chapter 1: LPC800 Introductory information
1.3 Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
LPC810M021FN8 DIP8 plastic dual in-line package; 8 leads (300 mil) SOT097-2
LPC811M001FDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
LPC812M101FDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
LPC812M101FD20 SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
LPC812M101FDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
Table 2. Ordering options
Type number Flash/kB SRAM/kB USART I2CSPI Comparator GPIO Package
LPC810M021FN8 4 1 2 1 1 1 6 DIP8
LPC811M001FDH16 8 2 2 1 1 1 14 TSSOP16
LPC812M101FDH16 16 4 3 1 2 1 14 TSSOP16
LPC812M101FD20 16 4 2 1 1 1 18 SO20
LPC812M101FDH20 16 4 3 1 2 1 18 TSSOP20

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UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Preliminary user manual Rev. 1.0 — 7 November 2012 6 of 313
NXP Semiconductors UM10601
Chapter 1: LPC800 Introductory information
1.4 Block diagram
Fig 1. LPC800 block diagram
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UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Preliminary user manual Rev. 1.0 — 7 November 2012 7 of 313
NXP Semiconductors UM10601
Chapter 1: LPC800 Introductory information
1.5 General description
1.5.1 ARM Cortex-M0+ core configuration
The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz. Integrated in
the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints.
The ARM Cortex-M0+ core supports a single-cycle I/O enabled port (IOP) for fast GPIO
access at address 0xA000 0000.
The core includes a single-cycle multiplier and a system tick timer (SysTick).

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Preliminary user manual Rev. 1.0 — 7 November 2012 8 of 313
2.1 How to read this chapter
The memory mapping is identical for all LPC800 parts. Different LPC800 parts support
different flash memory sizes.
2.2 General description
The LPC800 incorporates several distinct memory regions. Figure 2 shows the overall
map of the entire address space from the user program viewpoint following reset.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral is allocated 16 kB of space simplifying the address decoding.
The registers incorporated into the ARM Cortex-M0+ core, such as NVIC, SysTick, and
sleep mode control, are located on the private peripheral bus.
The GPIO port and pin interrupt/pattern match registers are accessed by the ARM
Cortex-M0+ single-cycle I/O enabled port (IOP).
UM10601
Chapter 2: LPC800 Memory mapping
Rev. 1.0 — 7 November 2012 Preliminary user manual

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UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Preliminary user manual Rev. 1.0 — 7 November 2012 9 of 313
NXP Semiconductors UM10601
Chapter 2: LPC800 Memory mapping
2.2.1 Memory mapping
2.2.2 Micro Trace Buffer (MTB)
The LPC800 supports the ARM Cortex-M0+ Micro Trace Buffer.
The private peripheral bus includes the ARM Cortex-M0+ peripherals such as the NVIC, SysTick, and the core control registers.
Fig 2. LPC800 Memory mapping
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UM10601 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Preliminary user manual Rev. 1.0 — 7 November 2012 10 of 313
3.1 How to read this chapter
The NVIC is identical on all LPC800 parts.
The SPI1 and USART2 interrupts are implemented on parts LPC812M101FDH20 and
LPC812M101FDH16 only.
3.2 Features
•Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0+.
•Tightly coupled interrupt controller provides low interrupt latency.
•Controls system exceptions and peripheral interrupts.
•The NVIC supports 32 vectored interrupts.
•Four programmable interrupt priority levels with hardware priority level masking.
•Software interrupt generation using the ARM exceptions SVCall and PendSV.
•Support for NMI.
•ARM Cortex M0+ Vector table offset register VTOR implemented.
3.3 General description
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0+. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
3.3.1 Interrupt sources
Tabl e 3 lists the interrupt sources for each peripheral function. Each peripheral device
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source. The interrupt number does not imply any
interrupt priority.
See Ref. 1 for a detailed description of the NVIC and the NVIC register description.
UM10601
Chapter 3: LPC800 Nested Vectored Interrupt Controller
(NVIC)
Rev. 1.0 — 7 November 2012 Preliminary user manual
Table 3. Connection of interrupt sources to the NVIC
Interrupt
number Name Description Flags
0 SPI0_IRQ SPI0 interrupt See Table 192 “SPI Interrupt Enable read and Set register
(INTENSET, addresses 0x4005 800C (SPI0) , 0x4005 C00C
(SPI1)) bit description”.
1 SPI1_IRQ SPI1 interrupt Same as SPI0_IRQ
2 - Reserved -