NXP Semiconductors MPC5566 User manual

© Freescale Semiconductor, Inc., 2012. All rights reserved.
Freescale Semiconductor MPC5566RM
Rev. 2.1, 05/2012
This MPC5566 Reference Manual set consists of the following files:
• MPC5566 Reference Manual Addendum, Rev 2
• MPC5566 Microcontroller Reference Manual, Rev 2
MPC5566 Microcontroller
Reference Manual

© Freescale Semiconductor, Inc., 2009–2012. All rights reserved.
Freescale Semiconductor
Reference Manual Addendum
MPC5566RMAD
Rev. 2, 05/2012
Table of Contents
This errata document describes corrections to the
MPC5566 Microcontroller Reference Manual, order
number MPC5566RM. For convenience, the addenda
items are grouped by revision. Please check our website
at http://www.freescale.com/powerarchitecture for the
latest updates.
The current version available of the MPC5566
Microcontroller Reference Manual is Revision 2.0.
MPC5566 Reference Manual
Addendum
1 Addendum for Revision 2.0. . . . . . . . . . . . . . . . . . 2
2 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . 9

MPC5566 Reference Manual Addendum, Rev. 2
Addendum for Revision 2.0
Freescale Semiconductor2
1 Addendum for Revision 2.0
Table 1. MPC5566RM Rev 2.0 addendum
Location Description
Section 12.4.2.7/Page 12-50 Change sentence “The bytes indicated as ‘—’ are not driven during that write cycle” to read “The
bytes indicated as ‘—’ are indeterminate and may be driven during that write cycle.”
Table 12-21, “Data Bus
Contents for Write
Cycles”/Page 12-50
Replace table with the one below to correct information about data bus contents for write cycles.
Note that only two columns have changed: under “32-Bit Port Size,” columns “D0:D7” and
“D8:D15.”
Table 9-23, “DMA Request
Summary for eDMA”/Page
9-43
Change two rows in the table to correct information about eSCI COMBTX DMA request.
Only the Transmit Data Register Empty and LIN Transmit Data Ready flags drive the DMA
request. The Transmit Complete flag is not used.
Transfer
Size
TSIZ
[0:1]
Address 32-Bit Port Size 16-Bit Port Size1
NOTES:
1Also applies when DBM=1 for 16-bit data bus mode.
A30 A31 D0:D7 D8:D15 D16:D23 D24:D31 D0:D7 D8:D15
Byte 01 0 0 OP0 — — — OP0 —
01 0 1 — OP1 — — — OP1
01 1 0 — — OP2 — OP2 —
01 1 1 — — — OP3 — OP3
16-bit 10 0 0 OP0 OP1 — — OP0 OP1
10 1 0 — — OP2 OP3 OP2 OP3
32-bit 00 0 0 OP0 OP1 OP2 OP3 OP0/
OP22
2This case consists of two 16-bit external transactions, the first writing OP0 and OP1,
the second writing OP2 and OP3.
OP1/OP3
DMA Request Channel Source Description
eSCIA_COMBTX 18 ESCIA.SR[TDRE] ||
ESCIA.SR[TC] ||
ESCIA.SR[TXRDY]
eSCIA combined DMA
request of the Transmit
Data Register Empty
and LIN Transmit Data
Ready DMA requests
eSCIB_COMBTX 34 ESCIB.SR[TDRE] ||
ESCIB.SR[TC] ||
ESCIB.SR[TXRDY]
eSCIB combined DMA
request of the Transmit
Data Register Empty
and LIN Transmit Data
Ready DMA requests

Addendum for Revision 2.0
MPC5566 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 3
Figure 5-2, “Master Privilege
Control Registers”/Page 5-5
Change read status for bits 20–31 from zero to reserved.
Table A-1, “Module Base
Addresses”/Page A-1
Correct names of peripheral bridge modules by adding underscore (PBRIDGEA becomes
PBRIDGE_A, PBRIDGEB becomes PBRIDGE_B). Only two rows of the table are changed.
Table A-2, “MPC5566 Detailed
Register Map”/Page A-2
Correct names of peripheral bridge A control registers by adding underscore (PBRIDGEA_x
becomes PBRIDGE_A_x).
Table 1. MPC5566RM Rev 2.0 addendum
Location Description
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RMB
W4
MT
R4
MT
W4
MPL
4
W
Reset0 11 1 01110111011 1
Access Field 4
Access Field 5
Access Field 6
Access Field 7
Module Base Address Page
Peripheral Bridge A (PBRIDGE_A) 0xC3F0_0000 Page A-2
Peripheral Bridge B (PBRIDGE_B) 0xFFF0_0000 Page A-35
Register Description Register Name Used
Size Address
Peripheral bridge A master privilege
control register
PBRIDGE_A_MPCR 32-bit Base + 0x0000
Reserved — — Base +
(0x0004-0x001F)
Peripheral bridge A peripheral access
control register 0
PBRIDGE_A_PACR0 32-bit Base + 0x0020
Reserved — — Base +
(0x0024-0x003F)
Peripheral bridge A off-platform
peripheral access control register 0
PBRIDGE_A_OPACR0 32-bit Base + 0x0040
Peripheral bridge A off-platform
peripheral access control register 1
PBRIDGE_A_OPACR1 32-bit Base + 0x0044
Peripheral bridge A off-platform
peripheral access control register 2
PBRIDGE_A_OPACR2 32-bit Base + 0x0048
Reserved — — Base + (0x004C-
0xC3F7_FFFF)

MPC5566 Reference Manual Addendum, Rev. 2
Addendum for Revision 2.0
Freescale Semiconductor4
Table A-2, “MPC5566 Detailed
Register Map”/Pages
A-36–A-37
Correct names of peripheral bridge B control registers by adding underscore (PBRIDGEB_x
becomes PBRIDGE_B_x).
Table 1. MPC5566RM Rev 2.0 addendum
Location Description
Register Description Register Name Used
Size Address
Peripheral bridge B master privilege
control register
PBRIDGE_B_MPCR 32-bit Base + 0x0000
Reserved — — Base +
(0x0004-0x001F)
Peripheral bridge B peripheral access
control register 0
PBRIDGE_B_PACR0 32-bit Base + 0x0020
Reserved — — Base +
(0x0024-0x0027)
Peripheral bridge B peripheral access
control register 2
PBRIDGE_B_PACR2 32-bit Base + 0x0028
Reserved — — Base +
(0x002C-0x003F)
Peripheral bridge B off-platform
peripheral access control register 0
PBRIDGE_B_OPACR0 32-bit Base + 0x0040
Peripheral bridge B off-platform
peripheral access control register 1
PBRIDGE_B_OPACR1 32-bit Base + 0x0044
Peripheral bridge B off-platform
peripheral access control register 2
PBRIDGE_B_OPACR2 32-bit Base + 0x0048
Peripheral bridge B off-platform
peripheral access control register 3
PBRIDGE_B_OPACR3 32-bit Base + 0x004C
Reserved — — (Base + 0x0050)-
0xFFF0_3FFF)

Addendum for Revision 2.0
MPC5566 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 5
Figure 17-13, “Unified
Channel Block Diagram”/Page
17-26
Reverse the arrow between the "Programmable Filter" and "Edge Detect".
Section 9.3.1 eDMA
Microarchitecture/ Page 9-33
In the Memory controller sub-bullet, delete the line "The hooks to a BIST controller for the local
TCD memory are included in this module".
Section 9.2.2.13, “eDMA
Interrupt Request Registers
(EDMA_IRQRH,
EDMA_IRQRL)”/ Page 9-19
In the third paragraph, remove the last line "without the need to perform a read-modify-write
sequence to the EDMA_IRQRH and EDMA_IRQRL".
Section 8.3: Initialization and
Application Information/Page
8-15
Change the sentence, “There are eight ECC check bits for each 64-bit data doubleword” to the
following:
• SRAM—Eight ECC check bits for each 64-bit SRAM data doubleword.
• Flash—Eight ECC check bits for each 64-bit flash data doubleword.
Table 6-152, “SIU_DISR Field
Descriptions”/ Page 6-113
• Bit 14-15–TRIGSELB: Correct the input select description as follows:
00: Replace the term “Invalid value” with “No Trigger”
• Bit 22-23–TRIGSELC: Correct the input select description as follows:
00: Replace the term “Invalid value” with “No Trigger”
• Bit 30-31–TRIGSELD: Correct the input select description as follows:
00: Replace the term “Invalid value” with “No Trigger”
Table 1. MPC5566RM Rev 2.0 addendum
Location Description

MPC5566 Reference Manual Addendum, Rev. 2
Addendum for Revision 2.0
Freescale Semiconductor6
Figure 11-9, “Synthesizer
Status Register
(FMPLL_SYNSR)”/Page
11-16
Correct the figure to reflect bits 23:28 and bits 30:31 as read-only.
Section 10.3.1.3, “INTC
Interrupt Acknowledge
Register
(INTC_IACKR)”/Page 10-12
Remove the first paragraph from the “Note”:
“The INTC_IACKR must not be read speculatively while in software vector mode. Therefore, for
future compatibility, the TLB entry covering the INTC_IACKR must be configured to be guarded.”
Table 10-3. INTC Memory
Map/Page 10-9
Add the following note at the end of this table:
Note:
To ensure compatibility with all PowerPC processors, the TLB entry covering the INTC memory
map must be configured as guarded, both in software and hardware vector modes.
• In software vector mode, the INTC_IACKR must not be read speculatively.
• In hardware vector mode, guarded writes to the INTC_CPR or INTC_EOIR complete before
the interrupt acknowledge signal from the processor asserts.
Table 10-9. MPC5566
Interrupt Request Sources/
Page 10-28
Update the note at the end of this table as follows:
Note:
The INTC has no spurious vector support. Therefore, if an asserted peripheral or software
settable interrupt request (whose PRI value in INTC_PSRn is higher than the PRI value in
INTC_CPR) negates before the interrupt request to the processor for that peripheral or software
settable interrupt request is acknowledged, the interrupt request to the processor still can assert
or remain asserted for that peripheral or software settable interrupt request. If the interrupt
request to the processor does assert or does remain asserted:
• The interrupt vector will correspond to that peripheral or software settable interrupt request.
• The PRI value in the INTC_CPR will be updated with the corresponding PRI value in
INTC_PSRn.
Furthermore, clearing the peripheral interrupt request's enable bit in the peripheral or,
alternatively, setting its mask bit has the same consequences as clearing its flag bit.Setting its
enable bit or clearing its mask bit while its flag bit is asserted has the same effect on the INTC
as an interrupt event setting the flag bit.
Table 1. MPC5566RM Rev 2.0 addendum
Location Description
Address: Base + 0x0004 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 00 0 000 0 0000
W
Reset0000000 0 000 0 0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
000000LOLFLOC
MO
DE
PLL
SEL
PLL
REF
LOC
KS
LOC
K
LOC
F
CAL
DO
NE
CAL
PAS
S
Ww1c w1c
Reset000000 0 0 —
1—1—1—1—2000
1Reset state determined during reset configuration.
2Reset state determined during reset.
Note: “w1c” signifies that this bit is cleared by writing a 1 to it.
Synthesizer Status Register (FMPLL_SYNSR)

Addendum for Revision 2.0
MPC5566 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 7
Section 10.4.2.1.4, “Priority
Comparator Submodule”/
Page 10-30
Add the following paragraph to this section:
One consequence of the priority comparator design is that once a higher priority interrupt is
captured, it must be acknowledged by the CPU before a subsequent interrupt request of even
higher priority can be captured. For example, if the CPU is executing a priority level 1 interrupt,
and a priority level 2 interrupt request is captured by the INTC, followed shortly by a priority level
3 interrupt request to the INTC, the level 2 interrupt must be acknowledged by the CPU before a
new level 3 interrupt will be generated.
Section 10.5.5.2, “Ensuring
Coherency”/ Page 10-37
Move the content of this section under a new heading Section 10.5.5.2.1, “Interrupt with Blocked
Priority”.
Add the following paragraph to this section:
Section 10.5.5.2.2: Raised Priority Preserved
Before the instruction after the GetResource system service executes, all pending transactions
have completed. These pending transactions can include an ISR for a peripheral or software
settable interrupt request whose priority was equal to or lower than the raised priority. Also,
during the epilog of the interrupt exception handler for this preempting ISR, the raised priority
has been restored from the LIFO to PRI in INTC_CPR. The shared coherent data block now can
be accessed coherently. Following figure shows the timing diagram for this scenario, and the
table explains the events. The example is for software vector mode, but except for the method of
retrieving the vector and acknowledging the interrupt request to the processor, hardware vector
mode is identical.
Raised Priority Preserved Timing Diagram
Table 1. MPC5566RM Rev 2.0 addendum
Location Description
Last In / First Out
Entry in LIFO
Write
INTC_CPR
Clock
Interrupt Request
to Processor
Hardware Vector
Enable
Interrupt
Acknowledge
Interrupt Vector
Read
INTC_IACKR
Write
INTC_EOIR
INTVEC in
INTC_IACKR
PRI in
INTC_CPR
Peripheral Interrupt
Request 100
0
108
1
208
23
Peripheral Interrupt
Request 200
030
3
A
B
C
D
E
F
G
H
I

MPC5566 Reference Manual Addendum, Rev. 2
Revision history
Freescale Semiconductor8
2 Revision history
Table 2 provides a revision history for this document.
Section 6.3.1.125 “Pad
Configuration Register 218
(SIU_PCR218)”
• Changed PA field from two bits to one bit
• Figure 6-126: Change note 2 to “... set the PA field to 0b0”.
• Table 6-122. PCR218 “PA Field Definition” change as shown below:
0b0 FCK
0b1 AN[15]
Section 19.4.5.4.1
“Calibration Overview”
Remove the braces from the equation “CAL_RES = GCC x (RAW_RES + OCC + 2)”.
Section 11.3.1.1
“Synthesizer Control Register
(FMPLL_SYNCR)”
Deleted the last note in PREDIV field description that states:
“To use the 8–20 MHz OSC, the PLL predivider must be configured for divide-by-two operation
by tying PLLCFG[2] low (set PREDIV to 0b000).”
Table 1. MPC5566RM Rev 2.0 addendum
Location Description
Raised Priority Preserved Events
Event Description
A Peripheral interrupt request 200 asserts during execution of ISR108 running at
priority 1.
B Interrupt request to processor asserts. INTVEC in INTC_IACKR updates with vector
for that peripheral interrupt request.
C ISR108 writes to INTC_CPR to raise priority to 3 before accessing shared coherent
data block.
D PRI in INTC_CPR now at 3, reflecting the write. This write, just before accessing
data block, is the last instruction the processor executes before being interrupted.
E Interrupt exception handler prolog acknowledges interrupt by reading INTC_IACKR.
F PRI of 3 pushed onto LIFO. PRI in INTC_CPR updates to 2, the priority of ISR208.
G ISR208 clears its flag bit, deasserting its peripheral interrupt request.
H Interrupt exception handler epilog writes to INTC_EOIR.
I LIFO pops 3, restoring the raised priority onto PRI in INTC_CPR. Next value to pop
from LIFO is the priority from before peripheral interrupt request 100 interrupted.
ISR108 now can access data block coherently after interrupt exception handler
executes rfi instruction.

Revision history
MPC5566 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 9
Table 2. Revision history
Revision Substantive changes Date of release
1.0 • Initial release. Corrected errors in chapter 12, “External Bus Interface (EBI).” 10/2009
2.0 • Corrected errors in chapter 9, “Enhanced Direct Memory Access (eDMA).”
• Corrected errors in chapter 5, “Peripheral Bridge (PBRIDGE A and PBRIDGE
B).”
• Corrected peripheral bridge name errors in appendix A, “MPC5566 Register
Map.”
• Corrected unified channel block diagram in chapter 16, “Enhanced Modular
Input/Output Subsystem (eMIOS).
• Clarified the description in Section 9.4.1, “eDMA Microarchitecture”.
• Clarified the description in Section 9.3.1.13, “eDMA Interrupt Request
Registers (EDMA_IRQRL).
• Clarified note in the INTC Interrupt Acknowledge Register
• Added a note in the INTC Memory Map table
• Clarified note at the end of the MPC5566 Interrupt Request Sources table
• Added a paragraph to the Section 10.4.2.1.4, “Priority Comparator
Submodule”
• Updated Section 10.5.5.2, “Ensuring Coherency”
• Corrected table “PCR218 PA Field Definition” and figure “AN[15]_FCK Pad
Configuration Register (SIU_PCR218)” and note 2 under figure.
• Deleted the last note in PREDIV field description of Synthesizer Control
Register (FMPLL_SYNCR) that states
05/2012