NXP Semiconductors MC92602 User manual

MC92602
Reduced Interface SerDes
Design Verification Board
User’s Guide
MC92602DVBUG
Rev. 3, 06/2005

MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3
Freescale Semiconductor iii
Contents
Paragraph Page
Number Title Number
Chapter 1
General Information
1.1 Introduction...................................................................................................................... 1-1
1.2 Design Verification Board Features................................................................................. 1-1
1.3 Specifications................................................................................................................... 1-2
1.4 Abbreviation List ............................................................................................................. 1-2
1.5 Related Documentation.................................................................................................... 1-3
1.6 Block Diagram................................................................................................................. 1-3
1.7 Board Components .......................................................................................................... 1-3
1.8 Contact Information......................................................................................................... 1-3
Chapter 2
Hardware Preparation and Installation
2.1 Unpacking Instructions .................................................................................................... 2-1
2.2 MC92602DVB Package Contents ................................................................................... 2-1
2.3 Hardware Preparation ...................................................................................................... 2-1
2.3.1 Setting the Power Supply and Voltage Regulators ...................................................... 2-1
2.3.2 Setting the Voltage Regulators..................................................................................... 2-2
2.3.3 HSTL Voltage Reference Regulator ............................................................................ 2-3
2.4 Reference Clock Source................................................................................................... 2-3
2.4.1 Using the Onboard Oscillator ...................................................................................... 2-4
2.4.2 External Reference Clock Source................................................................................ 2-4
2.4.3 Supplying a Clock to the MC92602 ............................................................................ 2-4
2.4.4 3.3V_CLK_OUTnSMA Connectors .......................................................................... 2-5
2.4.5 Clock Frequency Selection .......................................................................................... 2-5
2.5 Interface Components ...................................................................................................... 2-6
2.5.1 Parallel Inputs and Outputs.......................................................................................... 2-6
2.5.1.1 Parallel Inputs .......................................................................................................... 2-6
2.5.1.2 Parallel Outputs ....................................................................................................... 2-7
2.5.2 +VDDQ and Ground (GND) Access Connections........................................................ 2-7
2.5.3 Serial Inputs and Outputs............................................................................................. 2-7
2.6 Special Test Connection................................................................................................... 2-7
2.7 Test Traces ....................................................................................................................... 2-8

MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3
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Paragraph Page
Number Title Number
Chapter 3
Laboratory Equipment and Quick Setup Evaluation
3.1 Recommended Laboratory Equipment ............................................................................ 3-1
3.2 Quick Setup Data-Eye Diagram ...................................................................................... 3-2
3.2.1 Quick Setup Data-Eye Generation and Observation ................................................... 3-3
3.2.1.1 Equipment Setup...................................................................................................... 3-3
3.2.1.2 Parallel Input Connections....................................................................................... 3-4
3.2.2 Basic Eye Observation—Test Procedure..................................................................... 3-5
3.2.3 Quick Setup Bit Error Rate Checking.......................................................................... 3-6
3.2.3.1 Equipment Setup...................................................................................................... 3-6
3.2.3.2 Parallel I/O Connections.......................................................................................... 3-7
3.2.3.3 Quick Setup BERC Test Procedure ......................................................................... 3-7
Chapter 4
Test Setups
4.1 Serial Link Verification Using a Serial Bit Error Rate Tester (BERT) ............................ 4-1
4.1.1 Test Setup for Full-Speed Mode .................................................................................. 4-2
4.1.2 Test Setup for Half-Speed Mode ................................................................................. 4-2
4.2 Jitter Testing..................................................................................................................... 4-3
4.2.1 Jitter Test System Calibration ...................................................................................... 4-3
4.2.2 Reference Clock Jitter Transfer Test............................................................................ 4-4
4.2.3 Reference Clock Jitter Tolerance Test ......................................................................... 4-5
4.2.4 Data Jitter Tolerance Test............................................................................................. 4-6
Appendix A
Connector Signals
A.1 Input: 2×10 (0.100") Connectors.................................................................................... A-1
A.1.1 Control Signal Input Connectors ................................................................................ A-1
A.1.2 Transmitter Parallel Data Input Connectors ............................................................... A-3
A.2 Output: 2×20 (0.100") Connectors................................................................................. A-4
A.3 TEST_0 Connector ......................................................................................................... A-5
Appendix B
Parts List
B.1 Design Verification Board Parts List ...............................................................................B-1

MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3
Freescale Semiconductor v
Paragraph Page
Number Title Number
Appendix C
Prescaler for Jitter Measurement
C.1 Divide-by-xx Prescaler Description .................................................................................C-1
C.2 Prescaler Components......................................................................................................C-2
Appendix D
Revision History

MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3
vi Freescale Semiconductor

MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3
Freescale Semiconductor 1-1
Chapter 1
General Information
1.1 Introduction
This user’s guide describes the MC92602 design verification board, Rev. B and higher. The design
verification board (DVB) facilitates the full evaluation of the MC92602 Quad Reduced Interface SerDes.
It should be read in conjunction with the MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference
Guide. This design verification board is intended for evaluation and testing purposes only. Freescale does
not guarantee its performance in a production environment.
This board was designed to be used with laboratory equipment (pattern generators, data analyzers, BERT,
scopes, etc.) or connected to other evaluation boards. Access to the MC92602 device (verification chip) is
through connectors to each pin, to allow complete in-depth ‘design verification’ testing of the chip design.
This allows the user to check any or all features/functions of the MC92602 device.
The four parallel data input ports and all configuration/control signal pins, are accessed through common
2×10, 0.100" male connectors (headers). The parallel data output ports are accessed through 2×20, 0.100"
connectors. Device JTAG port signals are also accessed with a separate connector.
The MC92602 high-speed serial receivers and transmitters are accessed via SMA coaxial connectors for
signal integrity measurements.
A single 5.0-V power source is required for the DVB operation. All necessary voltages are generated by
regulators onboard. The reference clock for the MC92602 chip may be provided using either an external
clock or the onboard crystal oscillator. Clock drivers on the DVB provide additional clock signals for
triggering analyzer instrumentation and scopes.
1.2 Design Verification Board Features
The functional, physical, and performance features of the MC92602DVB are as follows:
• A single external 5.0-V to onboard regulators supply power to all onboard circuitry.
• Reference clock source is a 250-MHz crystal oscillator or an external clock source.
• Parallel data and control interfaces accessible through standard 0.100", 2 row connectors for data
generators and analyzers.
• The full-duplex differential data links accessible through SMA connectors.
• Two pairs of 50-Ωtest traces with SMA connections facilitate TDR measurements of the
characteristic impedance of representative board traces.
• Connector provided for JTAG test access port

General Information
MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3
1-2 Freescale Semiconductor
1.3 Specifications
The MC92602DVB design verification board specifications are provided in Table 1-1.
1.4 Abbreviation List
Table 1-2 contains abbreviations used in this document.
Table 1-1. MC92602DVB Design Verification Board Specifications
Characteristics Specifications
Board revision Rev. B and higher
External power supply +5 V DC ± 0.5 V DC < 2.0 A typical
Support circuit regulator 3.3 V ± 0.3 V DC
MC92602 core and link I/O regulator 1.8 V ± 0.15 V DC
Interface I/O (VDDQ) regulator 2.5 V ± 0.2 or 3.3 V ± 0.3 V DC
MC92602 package 196 MAPBGA
Operating temperature 0°−30°C
Material FR-4
Dimensions Height 14.8", 377 mm
Width 12.3", 312 mm
Thickness 0.1", 2.4 mm
Conducting layers Four ground planes, one split power plane, three signal routing layers, top and
bottom component layers with some additional signal routing.
Table 1-2. Acronyms and Abbreviated Terms
Term Meaning
‘1’ High logic level (nominally 1.5 or 3.3 V)
‘0’ Low logic level (nominally 0.0 V)
BIST Built-in self-test
DVB Design verification board
I/F Interface
N/C No connection
PN Pseudo-noise
PRBS Pseudo random bit sequence
TAP Test access port
TDR Time delay reflectometry
UIp-p Peak-to-peak unit interval

General Information
MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3
Freescale Semiconductor 1-3
1.5 Related Documentation
Related documentation includes the following:
•MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Guide (MC92602RM)
• MC92602DVB schematics
• MC100ES6222 data sheet
• MC100ES8111 data sheet
• MPC9456 data sheet
1.6 Block Diagram
Figure 1-1 shows the MC92602 design verification board block diagram.
1.7 Board Components
Table 1-3 is a list of major components of the MC92602 design verification board. A complete parts listing
can be found in Appendix B, “Parts List.”
1.8 Contact Information
For questions concerning the MC92602 design verification kit or to place an order for a kit, contact your
local Freescale field applications engineer.
Table 1-3. Major Board Components
Component Description
MC92602ZT Freescale Quad 1.25 Gbaud Reduced Interface SerDes
2 ×10, 0.100" connectors PG1–PG11, and PG13 provide access to the parallel inputs and control signals
2 ×20, 0.100" connectors LA1–LA4 provide access to the parallel outputs
2 ×8, 0.100" connectors PG12 and PG14 provide access to the SFP connector and +VDD/ground planes,
respectively.
SMA connectors SMA1–SMA16: Serial transmit and receive connections
TST1–TST8: Impedance test trace connections
CLK_OUT1–CLK_OUT6: Reference clock outputs
CLK_IN: External reference clock input
CLK_A_PG - CLK_D_PG: Input clock connectors
LT1587 voltage regulators VR33, VR18, and VR1: +3.3 V, +1.8 V, and +1.5 (VDDQ) voltage regulators
Potentiometers R12V, R22V, R22V1, and R22V2: Potentiometers for setting +3.3 V, +1.8 V,
+1.5 VDDQ, and HSTL reference voltage levels
XTAL oscillator Y1, Y2: Onboard 250-MHz crystal oscillator
MC100ES6222 clock buffer U2: Divide-by-1 or divide-by-2 clock buffer
MPC9456 clock buffer U3: +3.3-V LVCMOS clock buffer
MC100ES8111 clock buffer U4: Level shift and clock buffer

General Information
MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3
1-4 Freescale Semiconductor
Figure 1-1. MC92602 Design Verification Board Block Diagram
MC92602
2 ×20, 0.100"
RECV_A
2×10, 0.100" Connectors
XMIT_A
+3.3-V
Regulator
+1.5-V
Regulator
+5 V
MC100
MPC9456
Horizontal 50- Ω
Te s t Tr a c e s
Vertical 50-Ω
Te s t Tr a c e s
XMIT_B Ctrl/Tst
RECV_B
RECV_C
RECV_D
XMIT_C XMIT_D
Control
2×10, 0.100" Connectors
SW1
Connectors
1.5V_CLK_OUT5
1.5V_CLK_OUT6
CLK_IN
RLINK_D0
RLINK_C0
RLINK_B0
RLINK_A0
XLINK_D0
XLINK_C0
XLINK_B0
XLINK_A0
TST1 TST2
TST5 TST6
TST3 TST7
TST4 TST8
0.100" Connector
+1.5 V/GND
R22V1
R12V
+3.3 V
TPA
GND
+1.8-V
Regulator
R22V
3.3V_CLK_OUT2
3.3V_CLK_OUT3
HSTL_VREF
R22V2
X-TAL
Osc
CLK_B_PG
CLK_A_PG
CLK_C_PG
CLK_D_PG
ES6222
MC100
ES8111
3.3V_CLK_OUT1
HSTL_VREF
LA4
LA3
LA2
LA1
PG1
PG6
PG7 PG4
PG5
+1.5 V
+1.8 V
Reduced Interface
SerDes
PG10
PG11
PG8PG8
PG3
PG13PG2
3.3V_CLK_OUT4
PG9