Oki MSM9225B User manual

MSM9225B
User’s Manual
CAN (Controller Area Network) Controller
Oki Electric Industry Co., Ltd.
Ver. 4.0
July 2001
FEUL9225B-04 1

NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the
product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the
standard action and performance of the product. When planning to use the product, please ensure that the external conditions
are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the specified operating
ranges including, but not limited to, operating voltage, power dissipation, and operating temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from
misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or
electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or
operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in
connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by
us for any infringement of a third party’s right which may result from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,
office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not
authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in
any system or application where the failure of such system or application may result in the loss or damage of property, or death
or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment,
nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular countries. The
purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and
necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2001 Oki Electric Industry Co., Ltd.

Preface
This manual describes the hardware and operation of the MSM9225B CAN Controller
which conforms to the CAN protocol specification (Bosch, V2.0 part B/Active).
In this manual, additions and modifications that have been made on the upgrade to the
MSM9225B from the MSM9225 are indicated by “ ” on their respective pages.
This document is subject to change without notice.
B

Notation
Classification Notation Description
♦Numeric value xxhex, xxh, xxH Indicates a hexadecimal number. x: Any value in the range of 0 to F
xxb Indicates a binary number; “b” may be omitted. x: A value 0 or 1
♦Unit word, W 1 word = 16 bits
byte, B 1 byte = 2 nibbles = 8 bits
nibble, N 1 nibble = 4 bits
maga-, M 106
kilo-, K 210 = 1024
kilo-, k 103= 1000
milli-, m 10-3
micro-, µ 10-6
nano-, n 10-9
second, s (lower case) second
♦Symbol x0hex x indicates any value in the range of 0 to F of the high-order 4 bits.
♦Terminology “H” level, “1” level Indicates high voltage signal levels VIH and VOH as specified by the
electrical characteristics.
“L” level, “0” level Indicates low voltage signal levels VIL and VOL as specified by the
electrical characteristics.
♦Register description
Read/write attribute: R indicates a readable bit and W indicates a writable bit.
MSB/LSB: Most significant bit of the 8-bit register (memory)/least significant bit of the 8-bit register
(memory).
♦Additions and modifications that have been made in the MSM9225B
Indicated by “ ”.
Bit name
Function/meaning
of corresponding
bit value
MSB MMA OW TRQ RCS EIR EIT ERM ARES LSB MCR (x0hex), R/W: R/W
Initial
value: 00000000
0Data frame automatic
transmission disabled for
remote frame reception
1Data frame automatic
transmission enabled for
remote frame reception
Read/write
attribute
A
ddress
Re
g
ister name
Value of the bit
Initial value after
a reset
B

MSM9225B User’s Manual
Contents
Contents – 1
Table of Contents
Chapter 1 Overview
1.1 Overview.....................................................................................................................................................1-1
1.2 Features.......................................................................................................................................................1-1
1.3 Block Diagram............................................................................................................................................1-2
1.4 Configuration Example...............................................................................................................................1-2
1.5 Pin Configuration........................................................................................................................................1-3
1.6 Pin Descriptions..........................................................................................................................................1-4
Chapter 2 Register Descriptions
2.1 Memory Space............................................................................................................................................ 2-1
2.2 Message Memory........................................................................................................................................ 2-3
2.3 Message Memory Related Register ............................................................................................................2-4
2.3.1 Message Control Register (MCR: x0hex).............................................................................................2-4
2.3.2 Identifier 0 (IDR0: x1hex).....................................................................................................................2-7
2.3.3 Identifier 1 (IDR1: x2hex).....................................................................................................................2-8
2.3.4 Identifiers 2, 3, 4/Messages 0-7 (MSG0-7 in the case of standard format;
IDR2-4, TMSG0-7 in the case of extended format: x3 to xDhex)........................................................ 2-8
2.4 Control Registers ......................................................................................................................................2-16
2.4.1 CAN Control Register (CANC: 0Ehex)..............................................................................................2-17
2.4.2 CAN Interrupt Control Register (CANI: 0Fhex).................................................................................2-19
2.4.3 Message Box Count Setting Register (NMES: 1Ehex)....................................................................... 2-21
2.4.4 CAN Bus Timing Register 0 (BTR0: 1Fhex)......................................................................................2-21
2.4.5 CAN Bus Timing Register 1 (BTR1: 2Ehex) .....................................................................................2-23
2.4.6 Communication Input/Output Control Register (TIOC: 2Fhex).........................................................2-27
2.4.7 Group Message Register (GMR0: 3Ehex, GMR1: 3Fhex) .................................................................2-30
2.4.8 Group Message Mask Register (GMSK) ............................................................................................ 2-31
2.4.9 Standby Control Register (STBY: 8Ehex)..........................................................................................2-33
2.4.10 CAN Control Register 2 (CANC2: 8Fhex)......................................................................................... 2-34
2.4.11 Communication Message Box Number Register (TMN: 9Ehex)........................................................2-35
2.4.12 CAN Status Register (CANS: 9Fhex)................................................................................................. 2-36
2.4.13 Transmit Error Counter (TEC: AEhex)............................................................................................... 2-37
2.4.14 Receive Error Counter (REC: AFhex) ................................................................................................2-37
2.4.15 CAN Status Register 2 (CANS2: BEhex)...........................................................................................2-38
2.4.16 Bus Off Release Counter (BOCO: BFhex) .........................................................................................2-39
Chapter 3 Operational Description
3.1 Operational Procedure ................................................................................................................................3-1
3.1.1 Initial Setting......................................................................................................................................... 3-1
3.1.2 Transmit Procedure...............................................................................................................................3-2
3.1.3 Receive Procedure.................................................................................................................................3-3
3.1.4 Message Box Rewrites during Operation.............................................................................................. 3-4
3.1.5 Remote Frame Operation......................................................................................................................3-5
3.1.5.1 Automatic Response........................................................................................................................3-5
3.1.5.2 Manual Response.............................................................................................................................3-7
B
B
B

MSM9225B User’s Manual
Contents
Contents – 2
Chapter 4 Microcontroller Interface
4.1 Serial Interface............................................................................................................................................4-1
4.2 Parallel Interface.........................................................................................................................................4-3
4.3 MSM9225B Connection Examples ............................................................................................................4-4
4.3.1 Microcontroller Interface ......................................................................................................................4-4
4.3.1.1 Address/Data Separate Bus (No Address Latch Signal)..................................................................4-4
4.3.1.2 Address/Data Separate Bus (With Address Latch Signal)...............................................................4-5
4.3.1.3 Address/Data Multiplexed Bus........................................................................................................ 4-5
4.3.1.4 Serial Interface.................................................................................................................................4-6
4.3.2 CAN Bus Interface................................................................................................................................4-7
4.3.2.1 Electrically Isolated from Bus Transceiver (PCA82C250)..............................................................4-7
4.3.2.2 Directly Connected to Bus Transceiver (PCA82C250)................................................................... 4-7
4.3.2.3 Monitoring the CAN Bus.................................................................................................................4-8
Chapter 5 Electrical Characteristics
5.1 Electrical Characteristics ............................................................................................................................5-1
5.1.1 Absolute Maximum Ratings..................................................................................................................5-1
5.1.2 Recommended Operating Conditions ...................................................................................................5-1
5.1.3 DC Characteristics ................................................................................................................................ 5-2
5.1.4 Rx0, Rx1 Characteristics.......................................................................................................................5-2
5.1.5 Tx0, Tx1 Characteristics....................................................................................................................... 5-2
5.1.6 AC Characteristics ................................................................................................................................ 5-3
5.2 Timing Diagrams........................................................................................................................................5-5
5.2.1 Separate Bus Mode ...............................................................................................................................5-5
5.2.2 Separate Bus/Address Latch Mode .......................................................................................................5-6
5.2.3 Multiplexed Bus Mode..........................................................................................................................5-7
5.2.4 Serial Mode........................................................................................................................................... 5-8
5.2.5 Other Timing.........................................................................................................................................5-9
Apppendixes
Appendix A Package Dimensions ...................................................................................................................... A-1
Appendix B MSM9225B Memory Map............................................................................................................. A-2
Appendix C MSM9225B User’s Manual Contents of Revision From 2nd Version to 3rd Version................. A-10

Chapter 1
Overview

MSM9225B User’s Manual
Chapter 1 Overview
1 – 1
Chapter 1 Overview
1.1 Overview
The MSM9225B is a microcontroller peripheral LSI which conforms to the CAN protocol for high-speed LANs
in automobiles.
1.2 Features
•Conforms to CAN protocol specification (Bosch, V2.0 part B/Active)
•Maximum of 1 Mbps bit rate
•Communication method:
Transmission line is bi-directional, two-wire serial communication
NRZ (Non-Return to Zero) system using bit stuff function
Multi-master system
Broadcast system
•Up to 16 message boxes can be used, and messages up to 8 bytes long can be transmitted or received for each
message box.
Number of received messages can be extended by group message function (up to 2 groups can be set)
Overwrite flag is provided
•Priority control by identifier
2032 types in standard format, 2032 ×218 types in extended format
•Microcontroller interface
Corresponding to both parallel and serial interface
Parallel interface: Separate address/data bus type (with address latch signal/no address latch signal) and
multiplexed address/data bus type
Serial interface: Synchronous communication type
Three interrupt sources: transmission/receive/error
•Error control:
Bit error/stuff error/CRC error/form error/acknowledgment error detection functions
Retransmission/error status monitoring function when error occurs
Bit error flag/stuff error flag/CRC error flag/form error flag/acknowledge error flag are provided
•Communication control by remote data request function
•Sleep/Stop mode function
•Supply voltage: 5 V±10%
•Operating temperature: –40 to +125°C
•Package: 44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name: MSM9225BGA-2K)
B
B

MSM9225B User’s Manual
Chapter 1 Overview
1 – 2
1.3 Block Diagram
Figure 1-1 Block Diagram
1.4 Configuration Example
CAN
ABS
Engine
controller
CAN
CAN
Transmission Automatic
air conditioner
CAN
Seat-position controller
CAN
CAN
Outside mirror controller
CAN
Power window
Suspension
CAN
CAN Bus
Power steering
CAN
Figure 1-2 Configuration Example
B
Rx0
Tx0
Tx1
Rx1
VDD
GND
Bit stream
logic
(BSL)
Transmission
control logic
(TCL)
Error
management
logic (EML)
Bit timing logic (BTL)
Message
memory
Control
register
Data
manage-
ment
logic
Receive
control logic
(RCL)
XT
X
T
RESET
Timing
generator
microcontroller Interface
8
Serial I/F Parallel I/F
A7-0 8
AD7-0/D7-0
PALE
P
WR
P
RDW/SRW
P
RDY/SWAIT RW
WAIT
SCLK
SDI
SDO
R
D
R
DY
Mode1, 0
C
S
I
NT

MSM9225B User’s Manual
Chapter 1 Overview
1 – 3
1.5 Pin Configuration
Connect all VDD pins. Connect all GND pins.
Figure 1-3 44-Pin Plastic QFP (Top View)
B
B
33 32 31 30 29 28 27 26 25 24 23
1 2 3 4 5 6 7 8 9
10
11
A4 A5
A6
A7
SDO
GND
SDI
SCLK
PRD W
/SR
CS
INT
AD2/D2 AD1/D1 AD0/D0 Mode1 Mode0 GND PALE PWR RESET V
DD
T1
X
34
35
36
37
38
39
40
41
42
43
44
A3
A2
A1
A0
V
DD
GND
AD7/D7
AD6/D6
AD5/D5
AD4/D4
AD3/D3
12
13
14
22
21
20
19
18
17
16
15
V
DD
XT
XT
GND
PRDY
/SWAIT
GND
R0
X
R1
X
V
DD
GND
T0
X

MSM9225B User’s Manual
Chapter 1 Overview
1 – 4
1.6 Pin Descriptions
Table 1-1 Pin Description
Symbol Pin Type Description
CS 10 I Chip select pin. When “L”, PALE, PWR, PRD/SRW, SCLK and SDO pins
(microcontroller interface pins) are valid.
When “H”, these pins are invalid.
A7-0 41-44,
1-4 IAddress bus pins (when using separate buses). If used with a multiplexed bus
or if used in the serial mode, fix these pins at “H” or “L” levels.
AD7-0/
D7-0 31-38 I/O Multiplexed bus: Address/data pins (AD7-0)
Separate buses: Data pins (D7-0)
If used in the serial mode, fix these pins at a “L” level.
PWR 26 I Write input pin if used in the parallel mode. Data is captured when this pin is at a “L” level.
If used in the serial mode, fix this pin at a “L” level.
PRD/
SRW9I
Parallel mode: Read signal pin (PRD)
When at a “L” level, data is output from the data pins.
Serial mode: Read/write signal pin (SRW)
When at a “H” level, data is output from the SDO pin.
When at a “L” level, the SDO pin is at high impedance, and data is captured
beginning with the second byte of data input from the SDI pin.
PALE 27 I
Address latch signal pin
When at a “H” level, addresses are captured.
If used in the parallel mode and the address latch signal is unnecessary or in
the serial mode, fix this pin at a “H” or “L” level.
SDI 7 I Serial data input pin Addresses (1st byte) and data (beginning from the 2nd byte) are input to this
pin, LSB first. If used in the parallel mode, fix this pin at a “H” or “L” level.
SDO 5 O
Serial data output pin
When the CS pin is at a “H” level, this pin is at high impedance. When CS is at
a “L” level, data is output from this pin, LSB first.
If used in the parallel mode, fix this pin at a “H” or “L” level.
SCLK 8 I Shift clock input pin for serial data
At the rising edge of the shift clock, SDI pin data is captured. At the falling
edge, data is output from the SDO pin.
PRDY/
SWAIT 16 O
Ready output pin
When required by the MSM9225B, a signal may be output to extend the bus
cycle until the internal access is completed.
Internal access in progress After completion of access
Parallel mode
(PRDY)“L” level output High impedance output
Serial mode
(SWAIT) “H” level output “L” level output

MSM9225B User’s Manual
Chapter 1 Overview
1 – 5
Table 1-1 Pin Description (continued)
Symbol Pin Type Description
Mode1, 0 29, 30 I
Microcontroller interface select pins
INT 11 O
Interrupt request output pin
When an interrupt request occurs, a “L” level is output. This pin automatically
outputs a “H” level after 32 Ts (T = 1/fosc).
Three types of interrupts share this pin: transmission complete, reception
complete, and error.
RESET 25 I Reset pin
System is reset when this pin is at a “L” level.
XT 13 I
XT 14 O Clock pins. If internal oscillator is used, connect a crystal (ceramic resonator).
If external clock is used, input clock via XT pin. The XT pin should be left open.
Rx0, Rx1 18, 19 I Receive input pin. Differential amplifier included.
Tx0, Tx1 22, 23 O Transmission output pin
VDD 12, 20, 24, 40 — Power supply pin: Connect all VDD pins to the power supply source.
GND 6, 15, 17, 21, 28,
39 — GND pin: Connect all GND pins to ground.
Mode1 Mode0 Interface
0 0 No address latch signal
01 Separate
buses With address latch signal
10
Parallel mode
Multiplexed buses
1 1 Serial mode

Chapter 2
Register Descriptions

MSM9225B User’s Manual
Chapter 2 Register Descriptions
2 – 1
Chapter 2 Register Descriptions
2.1 Memory Space
The MSM9225B has 256 bytes of memory space for the message memory and control registers. Before starting
communication, messages for communication and various control registers must be set.
Figure 2-1 shows the configuration of memory space.
The message memory and the control registers are selected by an 8-bit address.
The message memory consists of 16 message boxes (message box 0 to message box F). Each message box is
selected by the high-order 4 bits (0hex to Fhex) of the address, and the message control register, the identifier,
and the area for storing the message contents are selected by the low-order 4 bits (0hex to Dhex) of the address.
It is possible to store a 2-byte (standard format) or a 5-byte (extended format) identifier and a message of a
maximum of 8 bytes can be stored in each message box. The control registers are selected by the low-order 4
bits (Ehex, Fhex) of the address. Table 2-1 shows the configuration of the control registers.
Figure 2-1 Memory Space Configuration
Message memory
Control registers
H(hex)
L(hex)
Lower
addresses
0 to D
E
F
Higher addresses 0 to F
Message control register (MCR)
Identifier 0 (IDR0)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
H(hex)
L(hex) Standard format
Message boxes specified by high-order 4 bits of addresses
“H” indicates high-order 4 bits and
“L” indicates low-order 4 bits.
Identifier 1 (IDR1)
Not used
Message 0 (MSG0) Identifier 2 (IDR2)
Extended format
Message 1 (MSG1)
Message 2 (MSG2)
Message 3 (MSG3)
Message 4 (MSG4)
Message 5 (MSG5)
Message 6 (MSG6)
Message 7 (MSG7)
Not used
Not used
Identifier 3
(
IDR3
)
Identifier 4 (IDR4)
Message 0 (TMSG0)
Message 1 (TMSG1)
Message 2 (TMSG2)
Message 3 (TMSG3)
Message 4 (TMSG4)
Message 5 (TMSG5)
Message 6 (TMSG6)
Message 7 (TMSG7)

MSM9225B User’s Manual
Chapter 2 Register Descriptions
2 – 2
Table 2-1 Control Register Configuration
Address Symbol Name
0EH CANC CAN control register
0FH CANI CAN interrupt control register
1EH NMES Message box count setting register
1FH BTR0 CAN bus timing register 0
2EH BTR1 CAN bus timing register 1
2FH TIOC Communication input/output control register
3EH GMR0 Group message register 0
3FH GMR1 Group message register 1
4EH GMSK00 Message mask register 00
4FH GMSK01 Message mask register 01
5EH GMSK02 Message mask register 02
5FH GMSK03 Message mask register 03
6EH GMSK10 Message mask register 10
6FH GMSK11 Message mask register 11
7EH GMSK12 Message mask register 12
7FH GMSK13 Message mask register 13
8EH STBY Standby control register
8FH CANC2 CAN control register 2
9EH TMN Communication message box number register
9FH CANS CAN status register
AEH TEC Transmission error counter
AFH REC Receive error counter
BEH CANS2 CAN status register 2
BFH BOCO Bus off release counter
CEH
CFH
DEH
DFH
EEH
EFH
FEH
FFH
— Not used (reserve area)
B
B
B

MSM9225B User’s Manual
Chapter 2 Register Descriptions
2 – 3
2.2 Message Memory
The message memory is the memory for setting and storing messages to be transmitted and received. The
message memory consists of 16 message boxes from message box 0 to message box F.
It is possible to transmit only the messages that have been stored in the message boxes, and the transmission is
done starting from the message box with the higher priority for which a transmission request is present.
Reception is possible only of messages having identifiers stored in the message boxes. When a message has
been received normally without generating an error, and if the identifier matches with the identifier stored in a
message box, the data of the message is stored in the corresponding message box in the message memory. Set
the highest message box number to be used in the register NMES (see Section 2.4.3).
Note when reading Message Memory Related Register
When the Message Memory Related Register (MCR, IDR0, IDR1, MSG0-7 in the case of the standard
format, IDR2-4 and TMSG0-7 in the case of the extended format) is polled, the same data are read out from
it as long as the same address is specified consecutively even if the Message Memory Related Register is
overwritten by the completion of message transfer between each polling.
However the MMA bit of Message Control Register (MCR, ×0hex) and Control Registers located at ×Ehex
and ×Fhex addresses are excluded.
When the Message Memory Related Register is polled, insert the dummy read access to the different
address after each reading out.

MSM9225B User’s Manual
Chapter 2 Register Descriptions
2 – 4
2.3 Message Memory Related Register
2.3.1 Message Control Register (MCR: x0hex)
This register performs various controls for a message.
Set this register for each message box.
The bit configuration is as follows:
MSB MMA OW TRQ RCS EIR EIT FRM ARES LSB MCR (x0hex), R/W: R/W
Initial
value: 00000000
0Data frame automatic transmission
disabled for remote frame reception.
1Data frame automatic transmission
enabled for remote frame reception.
0 Frame type specification
1 See Table 2-2 for details.
0Setting the transmission completion
interrupt request flag (ITF) is disabled.
1Setting the transmission completion
interrupt request flag (ITF) is enabled.
0Setting the receive completion interrupt
request flag (IRF) is disabled.
1Setting the receive completion interrupt
request flag (IRF) is enabled.
0 Cleared to “0” by the microcontroller.
1 “1” is set at the completion of reception.
0Cleared to “0” at the end of
transmission.
1Write a “1” for transmission
(transmission request).
0 No message overwrite
1 Message has been overwritten
0Writing disabled from the microcontroller to the message box. Transmission and reception are
possible.
1Writing enabled from the microcontroller to the message box. Transmission and reception
stopped.
Figure 2-2 Message Control Register (MCR)
B

MSM9225B User’s Manual
Chapter 2 Register Descriptions
2 – 5
(1) Automatic transmission: ARES
If the automatic transmission of the data frame is used for remote frame reception, set this bit to “1”.
At reset, the ARES bit is set to “0”. The ARES bit is invalid if the message is specified as a group
message.
Notes on Automatic Transmission
Following shows how the transmission is carried out for the messages for which ARES is set to “1”
when a remote frame is received.
The MSM9225B detects the transmission priority of all the messages for which the TRQ (transmission
request) bit is set to “1”, then transmits the messages in sequence from the one with the highest priority.
Note, therefore, that messages for which automatic transmission is set will not always be transmitted
immediately after remote frame reception if there are any other messages to be transmitted.
Also in cases where there are some messages for which TRQ is set to “1”, whereas the TIRS bit of
CANC is not set to “1” because it is not yet desired to transmit them, those messages for which TRQ bit
is set to “1” will be transmitted.
(2) Frame type setting: FRM
This flag sets the frame type of the message to be transmitted/received. A message of a frame type other
than the specified frame type cannot be transmitted/received.
Table 2-2 shows the relationship between setting and frame type.
At reset, the FRM bit is set to “0”.
Table 2-2 Frame Types
Specified as group message FRM Transmission frame Receive frame
0 Data frame Remote frame
No 1 Remote frame Data frame
0 Data frame
Yes 1Transmission not activated Remote frame
(3) Transmission completion interrupt enable: EIT
This is a flag to enable setting (“1”) the transmission interrupt request flag (ITF) when transmission
completes.
Set this flag from the microcontroller.
The EIT bit is valid when the EINTT bit of the CANI register is “1”. (See Section 2.4.2.)
At reset, the EIT bit is set to “0”.
(4) Receive completion interrupt enable: EIR
This is a flag to enable setting (“1”) the receive interrupt request flag (IRF) when receiving completes.
Set this flag from the microcontroller.
The EIR bit is valid when the EINTR bit of the CANI register is “1”. (See Section 2.4.2.)
At reset, the EIR bit is set to “0”.
(5) Receive status: RCS
When receiving completes, the RCS bit becomes “1”. Write “0” to the RCS bit before the micro-
controller reads receive data. When receiving the remote frame, the RCS bit becomes “1” just after the
reception. When receiving the data frame, it becomes “1” after receive data is written to the message
box.
At reset, the RCS bit is set to “0”.

MSM9225B User’s Manual
Chapter 2 Register Descriptions
2 – 6
(6) Transmission request: TRQ
When a message box is used for transmission, write “1” to this bit from the microcontroller. When
transmission ends normally, “0” is written to this bit. This means that the TRQ bit is “1” during
transmission. Therefore, to request transmission, confirm that the TRQ bit is “0” first, and then write “1”
to the TRQ bit. Set the TIRS bit of CANC to start transmission.
When the remote frame is received while the ARES bit is “1”, the TRQ bit is set to “1”.
At reset, the TRQ bit is set to “0”
(7) Overwrite flag: OW
When the RCS bit is “1”, this bit is set to “1” if data has been received by the same message box again.
That is, OW is a flag to indicate that receive data has been overwritten.
At reset, the OW bit is set to “0”.
(8) Message box access request/enable bit: MMA
Be sure to write a “1” to the MMA bit before writing to a message box from the microcontroller. Then
read the MMA bit. If “1” is read, the message box is accessible. If “0” is read, write a “1” in a loop
until the MMA bit actually becomes “1”.
After a “1” has been written to the MMA bit and the message box has been rewritten, be sure to write a
“0” to the MMA bit. Then read the MMA bit. If “1” is read, write a “0” in a loop until the MMA bit
actually becomes “0”.
The initialization bit INIT of the CAN control register (CANC: 0Ehex) has priority over the MMA bit.
That is, when INIT is “1”, the MMA bit is read as “1” irrespective of whether the MMA bit content is
“0” or “1”, so that the message box becomes accessible. In addition, after INIT is reset to “0”, all the
MMA bits will be set to “0”.
At reset, the MMA bit is set to “0”. It is possible to rewrite the contents of the other bits in the message
control register (MCR) at the same time that the MMA bit is overwritten.
When the MMA bit of a message box is set to “1”, do not set the MMA bit of other message box to “1”.
B

MSM9225B User’s Manual
Chapter 2 Register Descriptions
2 – 7
2.3.2 Identifier 0 (IDR0: x1hex)
This register sets the frame format, data length code, and a part of the identifier.
The bit configuration is as follows:
MSB IDFM DLC3 DLC2 DLC1 DLC0 IDB28 IDB27 IDB26 LSB IDR0 (x1hex), R/W: R/W
Initial
value: Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
0ID26
1
0ID27
1
0ID28
1
DLC3 DLC2 DLC1 DLC0 Number of bytes of a data field
0000 0
0001 1
•••• •
•••• •
0111 7
1000 8
0 Standard format (ID = 11 bits)
1 Extended format (ID = 29 bits)
Figure 2-3 Identifier 0 (IDR0)
(1) Identifier: IDB28 to IDB26
These bits set the identifier field.
For standard format (IDFM = 0), the higher 3 bits (ID28 to ID26) of the 11 bits (ID28 to ID18) are set.
For extended format (IDFM = 1), the higher 3 bits (ID28 to ID26) of the 29 bits (ID28 to ID0) are set.
At reset, these bits are undefined.
Note on Identifier
The identifier field (ID28 to ID18 for standard format, and ID28 to ID0 for extended format) is
overwritten with the received message’s identifier, when the message box for which the group message
function has been specified receives the message.
(2) Data length code: DLC3 to DLC0
These bits set the number of bytes of a data field. 0 to 8 can be set. Do not set values other than 0 to 8.
At reset, these bits are undefined.
Notes on Data Length Code
When the received data length code (hereafter DLC) matches the DLC set in the message box, the
number of bytes of data indicated by the received DLC is received and written to the message box.
When the received DLC does not match the DLC set in the message box, the MSM9225B operates as
follows:
- The received DLC is written into the DLC field in the message box.
- The number of bytes of data indicated by the received DLC is received and written to the message box.
(3) Frame format setting: IDFM
This bit sets the frame format.
At reset, the IDFM bit is undefined.
Table 2-3 Frame Format
IDFM Operation
0 Standard format (ID = 11 bits)
1 Extended format (ID = 29 bits)
B
B