Epson S1D13706 User manual

S1D13706 Embedded Memory LCD Controller
S1D13706
TECHNICAL MANUAL
Document Number: X31B-Q-001-06
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

Page 2 Epson Research and Development
Vancouver Design Center
S1D13706 TECHNICAL MANUAL
X31B-Q-001-06 Issue Date: 01/04/17
THIS PAGE LEFT BLANK

Epson Research and Development Page 3
Vancouver Design Center
TECHNICAL MANUAL S1D13706
Issue Date: 01/04/17 X31B-Q-001-06
COMPREHENSIVE SUPPORT TOOLS
EPSON provides the designer and manufacturer a complete set of resources and tools for the development of LCD
Graphics Systems.
Documentation
• Technical manuals
• Evaluation/Demonstration board manual
Evaluation/Demonstration Board
• Assembled and fully tested Graphics Evaluation/Demonstration board
• Schematic of Evaluation/Demonstration board
• Parts List
• Installation Guide
• CPU Independent Software Utilities
• Evaluation Software
• Display Drivers
Application Engineering Support
EPSON offers the following services through their Sales and Marketing Network:
• Sales Technical Support
• Customer Training
• Design Assistance
Application Engineering Support
Engineering and Sales Support is provided by:
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: [phone]
Fax: [phone]
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: [phone]
Fax: [phone]
Taiwan
Epson Taiwan Technology
& Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan
Tel: [phone]
Fax: [phone]
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: [phone]
Fax: [phone]
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: [phone]
Fax: [phone]
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: [phone]
Fax: [phone]
http://www.eea.epson.com

Page 4 Epson Research and Development
Vancouver Design Center
S1D13706 TECHNICAL MANUAL
X31B-Q-001-06 Issue Date: 01/04/17
THIS PAGE LEFT BLANK

X31B-C-001-03 1
GRAPHICS
S1D13706
ENERGY
SAVING
EPSON
March 2001
S1D13706 Embedded Memory LCD Controller
The S1D13706 is a color/monochrome LCD graphics controller with an embedded 80K byte SRAM
displaybuffer.Whilesupportingallotherpanel types,theS1D13706istheonlyLCDcontrollertodirectly
interface to both the Epson D-TFD and the Sharp HR-TFT family of products thus removing the
requirement of an external Timing Control IC. This high level of integration provides a low cost, low
power,singlechipsolutiontomeetthe demandsofembeddedmarketssuchasMobileCommunications
devices and Palm-size PCs, where board size and battery life are major concerns.
The S1D13706 utilizes a guaranteed low-latency CPU architecture thus providing support for micropro-
cessors without READY/WAIT# handshaking signals. The 32-bit internaldata path provideshigh perfor-
mance bandwidth into display memory allowing for fast screen updates.
Products requiring a rotated display image can take advantage of the SwivelViewTM feature which
provides hardware rotation of the display memory transparent to the software application. The
S1D13706 also provides support for “Picture-in-Picture Plus” (a variable size Overlay window).
The S1D13706 provides impressive support for Palm OShandhelds, however its impartiality to CPU
type or operating system makes it an ideal display solution for a wide variety of applications.
■FEATURES
■SYSTEM BLOCK DIAGRAM
•Embedded Display Buffer.
•Low Operating Voltage.
•Low-latency CPU interface.
•Direct support for the multiple CPU types.
•Programmable Resolutions and Color depths.
•STN LCD support.
•Active Matrix LCD support.
•Reflective Active Matrix support.
•SwivelViewTM (90, 180, 270° hardware
rotation of displayed image).
•“Picture-in-Picture Plus”.
•Software Initiated Power Save Mode.
•Hardware or Software Video Invert.
•100-pin TQFP15 package.
•104-pin CFLGA package.
S1D13706
Flat Panel
Data and
CPU Control Signals Digital Out

X31B-C-001-032
GRAPHICS
S1D13706
■DESCRIPTION
Memory Interface
• Embedded 80K byte SRAM display buffer.
CPU Interface
• ‘Fixed’ low-latency CPU access times.
• Direct support for:
Hitachi SH-4 / SH-3.
Motorola M68xxx (REDCAP2, DragonBall, ColdFire).
MPU bus interface with programmable READY.
Display Support
• 4/8-bit monochrome LCD interface.
• 4/8/16-bit color STN LCD interface.
• Single-panel, single-drive passive displays.
• 9/12/18-bit Active matrix TFT interface.
• ‘Direct’ support for Epson D-TFD and Sharp HR-TFT
(external timing control IC not required).
• Typical resolutions supported:
- 320x240@8bpp
- 160x160 @16bpp
- 160x240 @16bpp
Clock Source
• Two clock inputs (single clock possible).
• Clock source can be internally divided down for a
higher frequency clock input.
Display Modes
• 1/2/4/8/16 bit-per-pixel (bpp) support.
• Up to 64 gray shades using FRM and dithering on
monochrome passive LCD panels.
• Up to 64K colors on passive STN panels.
• Up to 64K colors on active matrix panels.
• SwivelView: direct hardware rotation of display image
by 90°, 180°, 270°.
• “Picture-in-Picture Plus”: displays a variable size
window overlaid over background image.
• Double Buffering/multi-pages: provides smooth
animation and instantaneous screen update.
Power Down Modes
• Software Initiated Power Save Mode.
Operating Voltage
•CORE
VDD 1.8 to 2.2 volts and 3.0 to 3.6 volts.
•HIO
VDD 1.8 to 2.2 volts and 3.0 to 3.6 volts.
•NIO
VDD 3.0 to 3.6 volts.
Package
• 100-pin TQFP15.
•104-pinCFLGA.
CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS
• S1D13706 Technical
Manual •PalmOS
Hardware
Abstraction Layer
• S5U13706 Evaluation Boards • WindowsCE Display Driver
• CPU Independent Software
Utilities •VXWorks
TornadoTM Display
Driver
Japan
Seiko Epson Corporation
Electronic Devices Marketing Division
421-8, Hino, Hino-shi
Tokyo 191-8501, Japan
Tel: [phone]
Fax: [phone]
http://www.epson.co.jp
Hong Kong
Epson Hong Kong Ltd.
20/F., Harbour Centre
25 Harbour Road
Wanchai, Hong Kong
Tel: [phone]
Fax: [phone]
Taiwan
Epson Taiwan Technology & Trading Ltd.
10F, No. 287
Nanking East Road
Sec. 3, Taipei, Taiwan
Tel: [phone]
Fax: [phone]
Singapore
Epson Singapore Pte., Ltd.
No. 1
Temasek Avenue #36-00
Millenia Tower
Singapore, 039192
Tel: [phone]
Fax: [phone]
Europe
Epson Europe Electronics GmbH
Riesstrasse 15
80992 Munich, Germany
Tel: [phone]
Fax: [phone]
North America
Epson Electronics America, Inc.
150 River Oaks Parkway
San Jose, CA 95134, USA
Tel: [phone]
Fax: [phone]
http://www.eea.epson.com
Copyright © 2000, 2001 Epson Research and Development, Inc. All rights reserved. VDC
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/
EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are
accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. Palm Computing is a registered trademark and the Palm OS platform Platinum logo is a trademark
of Palm Computing, Inc., 3Com or its subsidiaries. Microsoft, Windows, and the Windows Embedded Partner Logo are registered trademarks of Microsoft Corpo-
ration. All other trademarks are the property of their respective owners.

S1D13706 Embedded Memory LCD Controller
Hardware Functional Specification
Document Number: X31B-A-001-08
Copyright © 1999, 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners

Page 2 Epson Research and Development
Vancouver Design Center
S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
THIS PAGE LEFT BLANK

Epson Research and Development Page 3
Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Integrated Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 Display Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.6 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.7 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Typical System Implementation Diagrams . . . . . . . . . . . . . . . . . . . . . . 14
4 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Pinout Diagram - TQFP15 - 100pin . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Pinout Diagram - CFLGA - 104pin . . . . . . . . . . . . . . . . . . . . . . 19
4.3 Pinout Diagram - Die Form . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4.1 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4.2 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.4.3 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4.4 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4.5 Power And Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.5 Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . 29
4.6 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . 30
4.7 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 31
5 D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6 A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.1 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.2 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.2 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2.1 Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2.2 Generic #2 Interface Timing (e.g. ISA) . . . . . . . . . . . . . . . . . . . . . . . . 38
6.2.3 Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.2.4 Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.2.5 Motorola MC68K #1 Interface Timing (e.g. MC68000) . . . . . . . . . . . . . . . 44

Page 4 Epson Research and Development
Vancouver Design Center
S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
6.2.6 Motorola MC68K #2 Interface Timing (e.g. MC68030) . . . . . . . . . . . . . . . 46
6.2.7 Motorola REDCAP2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 48
6.2.8 Motorola DragonBall Interface Timing with DTACK
(e.g. MC68EZ328/MC68VZ328) . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.2.9 Motorola DragonBall Interface Timing w/o DTACK
(e.g. MC68EZ328/MC68VZ328) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3 LCD Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6.3.1 Passive/TFT Power-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.2 Passive/TFT Power-Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.4 Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
6.4.1 Generic STN Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.4.2 Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . 60
6.4.3 Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . 62
6.4.4 Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.4.5 Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . 66
6.4.6 Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . 68
6.4.7 Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.4.8 Generic TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.4.9 9/12/18-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.4.10 160x160 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ031B1DDxx) . . . . . . . 76
6.4.11 320x240 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ039Q2DS01) . . . . . . . . 80
6.4.12 160x240 Epson D-TFD Panel Timing (e.g. LF26SCR) . . . . . . . . . . . . . . . . 82
6.4.13 320x240 Epson D-TFD Panel Timing (e.g. LF37SQR) . . . . . . . . . . . . . . . . 86
7 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
7.1 Clock Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
7.1.1 BCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.1.2 MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.1.3 PCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
7.1.4 PWMCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
7.2 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
7.3 Clocks versus Functions . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
8.1 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
8.2 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
8.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
8.3.1 Read-Only Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 96
8.3.2 Clock Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
8.3.3 Look-Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8.3.4 Panel Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.3.5 Display Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Epson Research and Development Page 5
Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
8.3.6 Picture-in-Picture Plus (PIP+) Registers . . . . . . . . . . . . . . . . . . . . . . .115
8.3.7 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
8.3.8 General IO Pins Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
8.3.9 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
9 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
10 Display Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
11 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
11.1 Monochrome Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
11.2 Color Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
12 SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.1 Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
12.2 90° SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
12.2.1 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
12.3 180° SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
12.3.1 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
12.4 270° SwivelView™ . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
12.4.1 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
13 Picture-in-Picture Plus (PIP+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
13.1 Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
13.2 With SwivelView Enabled . . . . . . . . . . . . . . . . . . . . . . . . .144
13.2.1 SwivelView 90° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
13.2.2 SwivelView 180° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
13.2.3 SwivelView 270° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
14 Big-Endian Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
14.1 Byte Swapping Bus Data . . . . . . . . . . . . . . . . . . . . . . . . . .146
14.1.1 16 Bpp Color Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
14.1.2 1/2/4/8 Bpp Color Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
15 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
16 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
17 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
18 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Page 6 Epson Research and Development
Vancouver Design Center
S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
THIS PAGE LEFT BLANK

Epson Research and Development Page 7
Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
List of Tables
Table 4-1: CFLGA Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4-2: Pinout Assignments - Die Form (S1D13706D00A) . . . . . . . . . . . . . . . . . . . . 21
Table 4-3: Host Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 4-4: LCD Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 4-5: Clock Input Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 4-6: Miscellaneous Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 4-7: Power And Ground Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 4-8: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 4-9: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 4-10: LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 5-1: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 5-2: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 5-3: Electrical Characteristics for VDD = 3.3V typical. . . . . . . . . . . . . . . . . . . . . 32
Table 6-1: Clock Input Requirements for CLKI when CLKI to BCLK divide > 1 . . . . . . . . . . 33
Table 6-2: Clock Input Requirements for CLKI when CLKI to BCLK divide = 1 . . . . . . . . . . 34
Table 6-3: Clock Input Requirements for CLKI2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 6-4: Internal Clock Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 6-5: Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 6-6: Generic #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 6-7: Hitachi SH-4 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 6-8: Hitachi SH-3 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 6-9: Motorola MC68K #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 6-10: Motorola MC68K #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 6-11: Motorola REDCAP2 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 6-12: Motorola DragonBall Interface with DTACK Timing. . . . . . . . . . . . . . . . . . . 51
Table 6-13: Motorola DragonBall Interface without DTACK Timing . . . . . . . . . . . . . . . . . 53
Table 6-14: Passive/TFT Power-On Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 6-15: Passive/TFT Power-Off Sequence Timing. . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 6-16: Panel Timing Parameter Definition and Register Summary . . . . . . . . . . . . . . . . 57
Table 6-17: Single Monochrome 4-Bit Panel A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . 61
Table 6-18: Single Monochrome 8-Bit Panel A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . 63
Table 6-19: Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 6-20: Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . 67
Table 6-21: Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . 69
Table 6-22: Single Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 6-23: TFT A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 6-24: 160x160 Sharp ‘Direct’ HR-TFT Horizontal Timing . . . . . . . . . . . . . . . . . . . 77

Page 8 Epson Research and Development
Vancouver Design Center
S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
Table 6-25: 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing . . . . . . . . . . . . . . . . . 79
Table 6-26: 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing . . . . . . . . . . . . . . . . 81
Table 6-27: 320x240 Sharp ‘Direct’ HR-TFT Panel Vertical Timing . . . . . . . . . . . . . . . . . 81
Table 6-28: 160x240 Epson D-TFD Panel Horizontal Timing . . . . . . . . . . . . . . . . . . . . . 83
Table 6-29: 160x240 Epson D-TFD Panel GCP Horizontal Timing . . . . . . . . . . . . . . . . . . 84
Table 6-30: 160x240 Epson D-TFD Panel Vertical Timing . . . . . . . . . . . . . . . . . . . . . . 85
Table 6-31: 320x240 Epson D-TFD Panel Horizontal Timing . . . . . . . . . . . . . . . . . . . . . 87
Table 6-32: 320x240 Epson D-TFD Panel GCP Horizontal Timing . . . . . . . . . . . . . . . . . . 88
Table 6-33: 320x240 Epson D-TFD Panel Vertical Timing . . . . . . . . . . . . . . . . . . . . . . 89
Table 7-1: BCLK Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 7-2: MCLK Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 7-3: PCLK Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 7-4: Relationship between MCLK and PCLK. . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 7-5: PWMCLK Clock Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 7-6: S1D13706 Internal Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 8-1: S1D13706 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 8-2: MCLK Divide Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 8-3: PCLK Divide Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 8-4: PCLK Source Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 8-5: Panel Data Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Table 8-6: Active Panel Resolution Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Table 8-7: LCD Panel Type Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Table 8-8: Inverse Video Mode Select Options . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Table 8-9: LCD Bit-per-pixel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
Table 8-10: SwivelViewTM Mode Select Options . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Table 8-11: 32-bit Address Increments for Color Depth . . . . . . . . . . . . . . . . . . . . . . . .116
Table 8-12: 32-bit Address Increments for Color Depth . . . . . . . . . . . . . . . . . . . . . . . .117
Table 8-13: 32-bit Address Increments for Color Depth . . . . . . . . . . . . . . . . . . . . . . . .118
Table 8-14: 32-bit Address Increments for Color Depth . . . . . . . . . . . . . . . . . . . . . . . .119
Table 8-15: PWM Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Table 8-16: CV Pulse Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Table 8-17: PWM Clock Divide Select Options . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Table 8-18: CV Pulse Divide Select Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Table 8-19: PWMOUT Duty Cycle Select Options . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Table 15-1: Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Epson Research and Development Page 9
Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
List of Figures
Figure 3-1: Typical System Diagram (Generic #1 Bus) . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 3-2: Typical System Diagram (Generic #2 Bus) . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 3-3: Typical System Diagram (Hitachi SH-4 Bus) . . . . . . . . . . . . . . . . . . . . . . .15
Figure 3-4: Typical System Diagram (Hitachi SH-3 Bus) . . . . . . . . . . . . . . . . . . . . . . .15
Figure 3-5: Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000) . . . . . . . . . . . . .16
Figure 3-6: Typical System Diagram (MC68K #2, Motorola 32-Bit 68030). . . . . . . . . . . . . .16
Figure 3-7: Typical System Diagram (Motorola REDCAP2 Bus) . . . . . . . . . . . . . . . . . . .17
Figure 3-8: Typical System Diagram (Motorola MC68EZ328/MC68VZ328 “DragonBall” Bus). . .17
Figure 4-1: Pinout Diagram - TQFP15 - 100pin (S1D13706F00A) . . . . . . . . . . . . . . . . . .18
Figure 4-2: Pinout Diagram - CFLGA - 104pin (S1D13706B00A) . . . . . . . . . . . . . . . . . .19
Figure 4-3: Pinout Diagram - Die Form (S1D13706D00A) . . . . . . . . . . . . . . . . . . . . . .20
Figure 6-1: Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 6-2: Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Figure 6-3: Generic #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 6-4: Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 6-5: Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 6-6: Motorola MC68K #1 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .44
Figure 6-7: Motorola MC68K #2 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 6-8: Motorola REDCAP2 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .48
Figure 6-9: Motorola DragonBall Interface with DTACK Timing . . . . . . . . . . . . . . . . . . .50
Figure 6-10: Motorola DragonBall Interface without DTACK# Timing . . . . . . . . . . . . . . . .52
Figure 6-11: Passive/TFT Power-On Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . .54
Figure 6-12: Passive/TFT Power-Off Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 6-13: Panel Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure 6-14: Generic STN Panel Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Figure 6-15: Single Monochrome 4-Bit Panel Timing. . . . . . . . . . . . . . . . . . . . . . . . . .60
Figure 6-16: Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . .61
Figure 6-17: Single Monochrome 8-Bit Panel Timing. . . . . . . . . . . . . . . . . . . . . . . . . .62
Figure 6-18: Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . .63
Figure 6-19: Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Figure 6-20: Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Figure 6-21: Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . .66
Figure 6-22: Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . .67
Figure 6-23: Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . .68
Figure 6-24: Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . .69
Figure 6-25: Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Figure 6-26: Single Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . .71

Page 10 Epson Research and Development
Vancouver Design Center
S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
Figure 6-27: Generic TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Figure 6-28: 18-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Figure 6-29: TFT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Figure 6-30: 160x160 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing . . . . . . . . . . . . . . . .76
Figure 6-31: 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing. . . . . . . . . . . . . . . . . .78
Figure 6-32: 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing . . . . . . . . . . . . . . . .80
Figure 6-33: 320x240 Sharp ‘Direct’ HR-TFT Panel Vertical Timing. . . . . . . . . . . . . . . . . .81
Figure 6-34: 160x240 Epson D-TFD Panel Horizontal Timing . . . . . . . . . . . . . . . . . . . . .82
Figure 6-35: 160x240 Epson D-TFD Panel GCP Horizontal Timing . . . . . . . . . . . . . . . . . .84
Figure 6-36: 160x240 Epson D-TFD Panel Vertical Timing. . . . . . . . . . . . . . . . . . . . . . .85
Figure 6-37: 320x240 Epson D-TFD Panel Horizontal Timing . . . . . . . . . . . . . . . . . . . . .86
Figure 6-38: 320x240 Epson D-TFD Panel GCP Horizontal Timing . . . . . . . . . . . . . . . . . .88
Figure 6-39: 320x240 Epson D-TFD Panel Vertical Timing. . . . . . . . . . . . . . . . . . . . . . .89
Figure 7-1: Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Figure 8-1: Display Data Byte/Word Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 8-2: PWM Clock/CV Pulse Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 10-1: 4/8/16 Bit-Per-Pixel Display Data Memory Organization . . . . . . . . . . . . . . . . 131
Figure 11-1: 1 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 132
Figure 11-2: 2 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 132
Figure 11-3: 4 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 133
Figure 11-4: 8 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 133
Figure 11-5: 1 Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 134
Figure 11-6: 2 Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 135
Figure 11-7: 4 Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 136
Figure 11-8: 8 Bit-per-pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 137
Figure 12-1: Relationship Between The Screen Image and the Image Refreshed in 90° SwivelView. 138
Figure 12-2: Relationship Between The Screen Image and the Image Refreshed in 180° SwivelView.140
Figure 12-3: Relationship Between The Screen Image and the Image Refreshed in 270° SwivelView.141
Figure 13-1: Picture-in-Picture Plus with SwivelView disabled . . . . . . . . . . . . . . . . . . . . 143
Figure 13-2: Picture-in-Picture Plus with SwivelView 90° enabled . . . . . . . . . . . . . . . . . . 144
Figure 13-3: Picture-in-Picture Plus with SwivelView 180° enabled . . . . . . . . . . . . . . . . . 144
Figure 13-4: Picture-in-Picture Plus with SwivelView 270° enabled . . . . . . . . . . . . . . . . . 145
Figure 14-1: Byte-swapping for 16 Bpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 14-2: Byte-swapping for 1/2/4/8 Bpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 16-1: Mechanical Data 100pin TQFP15 (S1D13706F00A) . . . . . . . . . . . . . . . . . . 150
Figure 16-2: Mechanical Data 104pin CFLGA (S1D13706B00A). . . . . . . . . . . . . . . . . . . 151

Epson Research and Development Page 11
Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
1 Introduction
1.1 Scope
This is the Hardware Functional Specification for the S1D13706 Embedded Memory LCD
Controller. Included in this document are timing diagrams, AC and DC characteristics,
register descriptions, and power management descriptions. This document is intended for
two audiences: Video Subsystem Designers and Software Developers.
For additional documentation related to the S1D13706 see Section 17, “References” on
page 152.
This document is updated as appropriate. Please check the Epson Research and Devel-
opment Website at www.erd.epson.com for the latest revision of this document before
beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
documentati[email protected]n.com.
1.2 Overview Description
The S1D13706 is a color/monochrome LCD graphics controller with an embedded 80K
byte SRAM display buffer. While supporting all other panel types, the S1D13706 is the
only LCD controller to directly interface to both the Epson D-TFD and the Sharp HR-TFT
family of products thus removing the requirement of an external Timing Control IC. This
high level of integration provides a low cost, low power, single chip solution to meet the
demands of embedded markets such as Mobile Communications devices and Palm-size
PCs, where board size and battery life are major concerns.
The S1D13706 utilizes a guaranteed low-latency CPU architecture providing support for
microprocessors without READY/WAIT# handshaking signals. The 32-bit internal data
path provides high performance bandwidth into display memory allowing for fast screen
updates.
Products requiring a rotated display image can take advantage of the SwivelView TM feature
which provides hardware rotation of the display memory transparent to the software appli-
cation. The S1D13706 also provides support for “Picture-in-Picture Plus” (a variable size
Overlay window).
The S1D13706 provides impressive support for Palm OShandhelds, however its impar-
tiality to CPU type or operating system makes it an ideal display solution for a wide variety
of applications.

Page 12 Epson Research and Development
Vancouver Design Center
S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
2 Features
2.1 Integrated Frame Buffer
• Embedded 80K byte SRAM display buffer.
2.2 CPU Interface
• Direct support of the following interfaces:
Generic MPU bus interface using WAIT# signal.
Hitachi SH-3.
Hitachi SH-4.
Motorola M68K.
Motorola MC68EZ328/MC68VZ328 DragonBall.
Motorola “REDCAP2” - no WAIT# signal.
• 8-bit processor support with “glue logic”.
• “Fixed” low-latency CPU access times.
• Registers are memory-mapped - M/R# input selects between memory and register
address space.
• The complete 80K byte display buffer is directly and contiguously available through the
17-bit address bus.
• Single level CPU write buffer.
2.3 Display Support
• Single-panel, single-drive passive displays.
• 4/8-bit monochrome LCD interface.
• 4/8/16-bit color LCD interface.
• Active Matrix TFT interface.
• 9/12/18-bit interface.
• ‘Direct’ support for 18-bit Epson D-TFD interface.
• ‘Direct’ support for 18-bit Sharp HR-TFT interface.

Epson Research and Development Page 13
Vancouver Design Center
Hardware Functional Specification S1D13706
Issue Date: 01/11/13 X31B-A-001-08
2.4 Display Modes
• 1/2/4/8/16 bit-per-pixel (bpp) color depths.
• Up to 64 gray shades using Frame Rate Modulation (FRM) and dithering on mono-
chrome passive LCD panels.
• Up to 64K colors on passive STN panels.
• Up to 64K colors on active matrix LCD panels.
• Example resolutions:
320x240 at a color depth of 8 bpp
160x160 at a color depth of 16 bpp
160x240 at a color depth of 16 bpp
2.5 Display Features
• SwivelView™: 90°, 180°, 270° counter-clockwise hardware rotation of display image.
• “Picture-in-Picture Plus”: displays a variable size window overlaid over background
image.
• Double Buffering/Multi-pages: provides smooth animation and instantaneous screen
updates.
2.6 Clock Source
• Two clock inputs: CLKI and CLKI2. It is possible to use one clock input only.
• Bus clock is derived from CLKI and can be internally divided by 2, 3, or 4.
• Memory clock is derived from bus clock. It can be internally divided by 2, 3, or 4.
• Pixel clock can be derived from CLKI, CLKI2, bus clock, or memory clock. It can be
internally divided by 2, 3, 4, or 8.
2.7 Miscellaneous
• Hardware/Software Video Invert.
• Software Power Save mode.
• General Purpose Input/Output pins are available.
• 100-pin TQFP15 package.
• 104-pin CFLGA package.
• Die form available.

Page 14 Epson Research and Development
Vancouver Design Center
S1D13706 Hardware Functional Specification
X31B-A-001-08 Issue Date: 01/11/13
3 Typical System Implementation Diagrams
.
Figure 3-1: Typical System Diagram (Generic #1 Bus)
.
Figure 3-2: Typical System Diagram (Generic #2 Bus)
S1D13706
FPLINE
FPFRAME
FPSHIFT
DRDY
FPDAT[15:0]
CLKI2
Oscillator
FPLINE
FPFRAME
FPSHIFT
MOD
D[15:0] 16-bit
Generic #1
BUS
RESET#
D[15:0]
RD0#
WAIT#
A[16:1]
BUSCLK
RD/WR#
AB[16:1]
DB[15:0]
WE1#
RD#
M/R#
CS#
CLKI
WAIT#
RESET#
A[27:17]
CSn#
WE1# GPO
Decoder
WE0#
WE0#
Single
LCD
Display
Bias Power
BS#
HIOVDD
RD1#
VSS AB0
S1D13706
FPLINE
FPFRAME
FPSHIFT
DRDY
FPDAT[8:0]
CLKI2
Oscillator
FPLINE
FPFRAME
FPSHIFT
DRDY
D[8:0] 9-bit
Generic #2
BUS
RESET#
D[15:0]
RD#
WAIT#
A[16:0]
BUSCLK
RD/WR#
AB[16:0]
DB[15:0]
WE1#
RD#
M/R#
CS#
CLKI
WAIT#
RESET#
A[27:17]
CSn#
BHE# GPO
Decoder
WE0#
WE#
TFT
Bias Power
BS#
VDD
Display