Panasonic Sv-3500 Quick start guide

Panasonic

e

K

Audio

Division

Matsushita

Electric

Industrial

Co.

Ltd.

ORDER

NO.

AD8809230T

D 3

ffifcofl

Guide

■

.

L

Contents

i

1.

General

3

2.

Major

Blocks

and

Their

Operation

5

3.

RF

Section

14

4.

Signal

Processing

Circ it

51

5.

A dio

Section

66

6.

Panel

Control

77

System

Control

Circ it

7.

101

8.

Servo

131

Tape

Loading

9.

Fewer

S pply

136

10.

Mechanism

11.

141

Tro bleshooting

Man al

12.

163

13.

Adj stment

Man al

176

14.

Description

of

Major

IC's

187

1.

General

2.

Major

Blocks

and

Operation

Function

of

the

SV-3500

.

Major

Blocks

and

Operation

2.

h

1.

General

1-1.

Function

of

the

SV-3500

(1)

(2)

(3)

'J

1

—

•

terminals

cables

permit

digital.

recorder

and

A

30

nW

cylinder

head

is

sed

for

signal

recording

and

playback.

Use

of

a

DC

motor

and

a

loading

and

mode

switching

stainless

steel

chassis,

:

Post-recording

f nction

The

post-recording

f nction

for

s bcode

data

permits

program

n mbers

to

be

rewritten

and

skip

ID's

to

be

written.

DD

(direct

drive)

capstan

motor

for

tape

f.

and

mo nting

of

the

mechanism

in

a

res lt

in

stable

main

feat res

are

listed

below.

The

SV-3500

is

a

f ll-fledged

DAT

(Digital.

A dio

Tape)

with

coaxial

and

optical,

digital

I/O

terminals,

for

inp t

o tp t

in

addition

to

the

analog

LINE

IN/OUT

terminals.

Use

of

level

F rthermore,

to

free

level,

displays.

SV-3500

is

compatible

with

broadcast

and

B

(Japan

only)

permitting

digital

m sic

signals

from

a

broadcast

26

digit

display,

from

digital

signal,

display

,

ass res

error

The

digital

signal

inp t

and

o tp t

terminals

for

fiber

optic

cables

and

coaxial

cables

permit

digital,

copying

of

tapes.

(To

another

DAT

recorder

with

digital

inp t

and

o tp t

compatibility)

.

F rthermore

,

the

satellite

modes

A

recording

of

the

satellite

t ner.

meters

with

a

large

the

direct

display

system,

digital,

data

decoder

to

digital

tape

transport.

The

4)

Basic

Operation

5)

Added

F nction

(1)

(2)

(4)

2

Increased

se

IC's

in

the

power

s pply

circ it

of

the

SV-3500

has

red ced

the

size

of

the

PC

board

area.

position

of

a

program

and

a tomatically

the

old

start

ID.

the

is

Start

ID:

Move

starting

Ren mber

:

Ren mbers

the

programes.

Skip

ID:

Recording

ndesired

skipped

d ring

playback,

fast

forwarded,

A to

(absol te

time)

:

Writes

the

absol te

time

onto

a

tape

which

has

been

recorded

on

a

recorder

not

capable

of

writing

the

absol te

time.

Also

compatible

with

32

KHz

digital

recording,

the

SV-3500

is

capable

of

digital,

recording

the

broadcast

satellite

modes

A

and

B.

(The

SV-3500

is

compatible

only

with

mode

B

at

48

KHz).

the

position

of

the

start

ID

which

is

entered

at

the

erases

The

post-recording

f nction

for

s bcode

data

has

been

added

to

permit

the

SV-3500

to

change

the

following

data.

The

m sic

scan

(introd ction

search)

f nction

plays

only

the

first

9

seconds

of

each

program.

The

"cleaning"

indicator

f nction

has

been

added

to

inform

the

ser

when

the

head

req ires

cleaning.

(Lights

when

the

error

rate

exceeds

1000).

In

this

g ide,

each

block

in

fig re

2-1

is

described.

a

skip

ID

at

the

beginning

and

end

of

an

part

of

a

recorded

tape

enables

that

part

to

be

(When

a

skip

ID

is

detected

tape

is

fast

forwarded,

and

when

the

ID

detected

the

tape

is

played

back).

2.

Major

Blocks

and

Their

Operation

1)

Cylinder

(head)

2)

RF

Circ it

(chapter

3)

I

3)

Signal.

Processing

Circ it

(chapter

4)

A dio

Circ it

(chapter

5)

Pane).

Control

Circ it

(chapter

6)

I

6)

System

Control

Circ it

(chapter

7)

Servo

Board

(chapter

8)

the

3

A

30

mm^f

cylinder

head

which

helically

scans

the

DAT

tape

is

sed.

The

tape

has

a

wrap

angle

of

90

degree

with

respect

to

the

cylinder

and

the

cylinder

is

fitted

with

two

heads,

A

and

B.

The

signal

distorted

waveform

recording

to

the

tape,

circ it

which

amplifies

and

waveshapes

the

signal

so

that

signal

can

be

processed

easily

at

the

data

slice

circ it

the

This

circ it,

the

heart

of

the

mechanism

operation

control,

receives

vario s

types

of

data

from

the

panel

control

circ it,

signal

processing

circ it

and

servo

circ it,

and

controls

the

overall

operation

of

the

system.

This

circ it

incl des

the

A/D

and

D/A

converters

and

mainly

handles

the

m sic

signal.

reprod ced

by

the

cylinder

has

a

considerably

(compared

to

the

digital

signal

)

when

The

RF

circ it

contains

a

waveshaping

the

in

This

circ it

prod ces

the

format

of

the

signal

recorded

on

the

tape

d ring

recording

and

interleaves

the

data

and

adds

error

correcting

codes.

D ring

playback,

reading

of

the

m sic

signal,

error

correction,

error

interpolation,

and

reading

of

the

s bcode

data

are

performed.

This

circ it

also

generates

the

clocks

sed

in

the

SV-3500.

This

circ it

perform

inp t

processing

of

the

control

keys,

control

the

FL

display

and

exchanges

control

data

with

the

system

control

circ it.

This

circ it

monitors

and

controls

mechanism.

the

operation

of

8)

Loading

Mechanism

(chapter

9)

and

9)

Power

s pply

Circ it

(chapter

10)

This

the

Mechanism

Block

(chapter

11)

10)

mechanism

is

same

as

SV-D1000

(Technics

1st

generation

Cylinder

J37

PLL

bloc

J37

H.P

J4

J 6

cn

JI

7

Figure

2-1

Organization

of

the

SV-3500

4

DEW

o-

Mechanism

(chapter

11)

This

DAT)

.

OPEN/CLOSE

RF

board

(

chapter

3

)

Panel

control

circ it

(chapter

6)

A dio

circ it

(chapter

5)

()

LINE

IN/OUT

()

DIGITAL

IN/OUT

()

OPTICAL

IN/OUT

Servo

board

(chapter

8)

System

control

circuit

(chapter

7)

Power

supply

board

(chapter

10)

J7

J6

J

JI

2

J 3

J 4

Loading

mechanism

(chapter

9)

circuit

supplies

the

AC

and

DC

power

required

by

various

circuits

in

the

SV-3500.

Signal

processing

circuit

(chapter

4)

This

mechanism

is

driven

by

a

single

DC

motor

and

loads

unloads

the

tape.

3.

RF

Section

3- .

Block

Diagram

Description

3-2.

Playback

Circuit

Operation

3-3.

Recording

Circuit

Operation

I

5

3-1.

Block

Diagra

Description

4th

AMP

EQ

LPF

—

----

RSRF

(playback

signal)

Head

B

Playback

Circ it

Block

HSW

(head

switch)

REC

AMP

Recording

Circ it

Block

SRRF

(recording

signal)

1)

Playback

Circ it

RF

signals

picked

p

by

head

A

and

head

B

then

a

2)

Recording

Circuit

6

Integra

tion

I

_

1

I

A/B

separat

ion

Wave

shaping

at

for

SRRP

■-•-(recording

signal)

playback

switching

low

A/B

Head

A

A/B

mixing

JT

I

removed

to

the

eye

I

to

a

processing

lst-3rd

AMP

ra!

fir'

•

i

>

w

W

[_777_

]

_

(3)

The

the

eq alization.

serial

signal

is

amplified

by

approximately

20

dB

4th

amplifier

and

sent

to

the

eq alizer

I

___

Integra

*

t

^

on

I

S2

During

playback'

SI

ON

S2

OFF

|

•

During

recording:

S2

ON

S

OFF

|lst-3rd

AMP

(2)

The

separated

signals

are

amplified

at

their

respective

amplifiers

and

sent

to

head

A

and

head

B.

The

recording

c rrent

switching

circ it

is

a

gain

switching

circ it

which

changes

the

level

of

the

PCM

and

ATF

components

of

the

RF

signals

for

recording.

pattern

of

rectang lar

circ it

as

signal

).

filter,

the

signal

is

sent

At

the

waveshaping

circ it,

’

is

waveshaped

and

then

sent

to

the

signal

RSRF

signal

(which

is

a

digital

data

Recording

I

--

c rrent

switching

I

lg_r

rec

amp

Fig re

3-1-1

RF

Block

Diagram

(1)

The

RF

signals

picked

p

by

head

A

and

head

B

are

sent

thro gh

the

rotary

transformers

to

their

respective

three

amplifiers

and

amplified

by

approximately

70

dB

and

each

signals

is

sent

to

the

integrators.

(1)

The

recording

signal.

(SRRF)

sent

from

the

signal,

processing

circ it

is

separated

at

the

A/B

separator,

by

HSW

signal,

control,

into

RF

signals

for

head

A

and

head

B.

(2)

At

the

integrators,

each

signal

is

s bjected

to

freq ency

compensation

and

the

res lt

is

sent

to

the

mixer.

Based

on

HSW

signal

control,

the

A/B

mixer

converts

the

signals

reprod ced

at

head

A

and

head

B

to

a

serial,

signal.

.

(4)

After

the

nwanted

8

MHz

and

above

components

are

at

the

low-pass

waveshaping

circ it.

the

eq alized

signal

wave

the

3-2.

Playback

Circuit

Operation

1)

Fran

the

Heads

to

the

4th

Amplifier

TP353

EQ

(IC35

30)

VCC1

2

*5V

TP352

R362

OC

Q352

Fran

the

recording

amplifier

(pin

18

of

IC-351)

Fran

the

recording

amplifier

(pin

19

of

IC-351)

Figure

3-2-1

Playback

Circuit

Diagram

(1)

(2)

(3)

7

When

from

IC-351

(AN7030S)

command

goes

a

turn

this

the

R/P

S/W

driver

A/B

S/W

driver

ZJ

Next,

351,

(At

Thus,

are

and

are

the

R381

cd

co-L-

-(A

Head

A

r=3ii^

Head

B

Cylinder

GND

APB

AREC

BPB

BREC

J28

GND

APB

AR

EC

BPB

BREC

2

T

5

"2.

3

5

A/B

mixer

—

-42ndJ>

—

A^

ip

A

L

3W4

4

th

AMP

04

CO

—

CO

XHx

—

T

”

T

“

co-j-ci

-r-M

<?|

O

I

0(4 ;

C354jt

Q357

J-

O0W39V38J

TP

^

5

'

mw

amp

Q

(J3o3

|

—

«

Ml

_

035

*

------

Q355/x>.

J27

•

]

3

|

RPSV

|

-

|ll|

SRRP|

-

|

8

|

HSW

|

C355O*

4^)0358

TV

ffi)

----

Q351

and

Q352,

which

are

connected

to

23

of

ic



on

and

this

gro nds

the

REC

side

of

the

heads,

time,

Q355

and

Q356

on

the

PB

side

are

off).

RF

signals

picked

p

at

the

heads

are

sent

to

Q353

and

Q354

(via

the

rotary

transformers

and

pins

2

and

4

of

connector

J28).

They

are

amplified

and

then

sent

to

pins

3

and

5

of

IC-531.

Q357

and

Q358

are

provided

to

prevent

C354

and

C355

from

discharging

d ring

recoeding.

11

of

connector

J27

goes

low

d e

to

a

the

signal,

processing

block,

26

of

IC-351

low.

Then,

a

high

o tp t

appears

at

23

of

IC-531

and

low

o tp t

appears

at

22.

5

X

6

The

RF

signals

inp t

at

pins

3

and

5

of

IC-351

amplified

at

the

2nd

and

3rd

amplifiers

within

the

IC

o tp t

from

pins

41

and

42.

The

o tp t

RF

signals

s bjected

to

low

freq ency

compensation

at

integrators,

consisting

of

C370

thro gh

C373

and

thro gh

R384,

and

inp t

to

pins

39

and

40

of

the

IC-351.

Uh

40

of

IC-351

for

head

B

24

of

IC-351

for

HSW

37

of

IC-351

for

RPSV

Fig re

3-2-2

8

39

of

IC-351

for

head

A

----

|j|

11

at

37

of

IC-351.

The

RPSV

signa],

from

37

C369

and

is

sent

to

3

of

connector

J27

where

sed

to

operate

the

servo

circ it

in

the

servo

block.

RF

signals

for

head

A

and

head

B

are

mixed

as

shows

fig re

3-2-2.

(4)

Based

on

HSW

signal,

control

at

8

of

connector

J27,

The

RF

signals

for

head

A

and

head

B

(which

are

inp t

at

pins

39

and

40)

are

mixed

by

the

A/B

mixer

within

the

IC.

The

mixed

signal

is

amplified

by

the

4th

amplifier

and

o tp t

passes

it

is

The

in

2)

From

the

4th

Amplifier

to

the

Eq alizer

O tp t

(EQOGT)

+5V

■

|

3

RPSV

|

4

TP354

i:C366

3

R374

V

0359

IC-35

AN7030S

Figure

3-2-3

and

sent

to

29

and

28

(

voltage

i/

9

CO

CO;

CO

r-~

CO

tr*

VR354

—

aza

—

At

R375

C369

---

IF

VR355

VR356

—

Ayv

—

J27

12

TP

a

30

of

IC-35

Z3

51,

signals,

are

IC-351,

respectively.

S-L

8T

u

T

R370

R37

Z35

SDL4047

5

RPRF

I

(a)

Operation

of

control

amplifier).

28,

29

and

30

of

IC-351

are

s bjected

to

eq alization

by

VR354

thro gh

VR356

(which

are

connected

to

the

VCA

drive

circ it)

as

shows

in

fig re

3-2-4.

|

R

3

73

.

|Delay

Line

2

R372

’

the

eq alizer

section

and

VCA

The

RF

envelope

signals

inp t

by

IC-351

are

thro gh

VR356

j

D351

(1)

The

RF

signal

o tp t

from

37

of

IC-351

is

sent

to

and

1

of

Z351

(delay

line).

which

are

delayed

by

100

nsec

and

200

nsec,

o tp t

at

3

and

4,

and

sent

to

29

and

28

of

CH.A

an

Recording

waveform

i

to

adjust

and

IC-351

(29)

b

eye

-2t-

IC-351

(28)

t=

100

nsec

Figure

3-2-4

3)

Fran

the

Low-Pass

Filter

(LPF)

to

the

Signal.

Processing.

Circuit

0v

77

J

36

0

IC2I3

X

o'

JI4

AN702 S

z

g

8.

9

OvT

Qv

'o'

I2v

5OV

40v

DET

0

Figure

3-2-5

—

10

—

L:

)

—

<S)

4

8

-

7T

-<»5>

<h7>

-----------

(MDMTR

+

IMOMTR

-

2

X

>

—

<2

02VH

X

-

—

(M0MTR+

)

-----

—

(

SRRF

—

<

SRPR

-----

(

RFENV

—

<

RSRF

—

<

EOT

----

(

MM000

----

(

MM002

-----

(

THS

-----

<

THt

-----

<

TH3

—

(

NPULOAO

—

<

SYNC

A

H2V

AGNO

RPSV

AGNO

RPRF

AGNO

SRRF

HSW

—

(

3OKUA0

-----

(

ATFWDN

—

(

SRPR

—

<

HTP

JI3

—

(MOMTR

-

>

—

'

-----

(

I3OKMA0

)

—

-----

(

G.GNO

>

—

<

HSW

>

—

IC2I3

L

MN74HC367S

INTERFACE

i'>

---------

|2)

------------

|3>

—

------

'

9

0vp.p

■v

5

vi<oy>

__________

K25VX

____________

Qv

___________

03

V

(2

5v><QV>

rv'ini

di.

j

—

©

—

©

C32I

AN702IS

ENVELOPE

:

the

which

27.

’

of

IC-351

pin(27)

b-(a+c)

eye

is

VR354

’

the

IC323

AN8005

REGULATOR

IIII

2V/5mi

Ji,

IC-351

(30)

a

"ft

/

____

f_

______

4

;

Jirr

f

6G66Ht

50v\

;

2

XX

£<!

$1

Sts

ft

PLAY

7

Mo

?v/5iM.di«

3

°

0

I'

®

ill

t

EC

IIII

Zv/Smiec

4lv

,

---------------

(h6

>A

---------

,

---------------

<

h

l

)

-----------

4

2VKOV? >

(

0V«4

3V»}

a

T

vk

O

wi

)

£av«o«

%av

'

''«ov>r

IC322

AN8OO5

REGULATOR

REC/P

iav

--------

njr;

-

33

33*1

(b)

Using

CH.A

as

an

example,

VR356

varies

the

level

of

a+c

the

leading

trailing

edges

of

pattern

waveform

o tp t

from

adj sts

the

balance

pattern

by

varying

the

level

ratio

of

a

and

c.

am

T

427

/

■2.97-477

VR355

varies

the

a+c

level

for

CH.B,

and

together

with

VR354,

adj sts

the

balance

of

the

eye

pattern

waveform.

IC323

JU9V

^3

________

IC-321

|13)

IC-321

1

14)

IC-321

(5)

IC-321

pin(ll)

Figure

3-2-7

Figure

3-2-6

buffer

I

—

-

output

is

generated

as

it

is

used

in

the

and

2ms

rt

1

(1)

The

RF

signa]

sent

from

5

of

J27

in

the

RF

inp t

by

the

Z321

LPF

where

nwanted

components

of

8

and

above

are

removed,

and

then

inp t

by

5

of

IC-321.

(4)

The

logic

circ it

consisting

of

IC-213

is

sed

to

the

timing

signals

and

recording

signals.

(3)

At

the

same

time,

the

RF

envelope

signal,

which

is

from

14

of

IC-321,

signal,

processing

circ it

to

search

for

the

beginning

end

of

tape.

Its

timing

chart

is

shows

in

fig re

3-2-7.

block

is

MHz

(2)

The

RF

signal

inp t

by

5

of

IC-321

is

waveshaped

by

a

comparator,

o tp t

from

13,

and

sent

to

the

signal

processing

circ it

thro gh

5

of

connector

J14.

At

this

time,

the

RF

signal

is

o t

p t

to

14

only

when

11

of

IC-321

is

high.

This

is

done

to

prevent

noise

from

being

o tp t

when

there

is

no

signal.

This

operation

is

shows

in

fig re

3-2-6.

3-3.

Recording

Circuit

Operation

4)

J3J

+9V

,035

R353

CM

VI

/in

uS

x

y

o

v->

f/

"r

Fig re

3-3-1

Recording

Circ it

Diagram

1)

Recording

Signal

Flow

the

signal

—

12

—

'll!

R369

*.

w

A

r

368

(2)

The

recording

signal

inp t

by

15

of

IC-351

is

sent

A/B

switch

(A

and

B

head

switch)

thro gh

the

R/P

which

is

inp t

by

8

of

connector

J27,

PLAY

AMP

in

A/B

S

W

to

HSW

5.

CO'

Ct'

i

—

|9|13OKMAD|

r-

|io|ATF

WDN|

J28

GND

APB

AREC

BPB

BREC

GND

APB

AREC

BPB

BREC

^3.

3

4

2

3

4

5

J27

----

I

8

I

HSW

I

----

|ll|SPRP

|

-----

I

7

|SRRF

|

I

|=

|

Tree

SW

Bloc

X

-

R/P

s

w

7

X°

Q353i

C351

47

—

I^

7

,

0354

------

C352

crT*

si

CO-r-

-HL

C3

58

cr

C3S9

fl

the

signal

control,

the

decision

to

send

the

inp t

recording

signal

to

head

A

or

head

B

is

made

at

the

A/B

switch.

The

signal,

is

amplified

at

the

REC

amplifier

and

o tp t

from

18

of

IC-351

for

head

A

and

from

19

for

head

B.

The

timing

is

shows

in

fig re

3-3-2.

iWl

2J

C360,,

-o-

”

036

9

X

0

)

“

co

i!i

(1)

The

recording

signal

(SRRF

signal)

from

the

signal,

processing

circ it

is

sent

to

.15

of

IC-351

thro gh

7

of

connector

J27.

IC-351

AN7030S

(the

Q351

and

Q352

2)

I

rec

Switching

Block

within

IC-351

and

ATF

This

PCM

—

-

IC-351

pini24i

IC-351

pin(i5)

------

5ms

-----

-

—

0.42ms

—

76.5

us

•7.5ms-

Figure

3-3-2

Figure

3-3-3

-

13

-

IC-351

pinlis)

—

Recording

signal

Of

is

IC-351

04)

ATF

WDN

IC-351

(19)

for

head

"B"

ATF

—

130K

—

IC-351

(18)

for

head

"A"

C360

and

C361.

at

this

time,

of

TV

11

I

—

11

I

(4)

Since

23

of

IC-351

is

low

at

this

time,

are

off.

are

C359,

mode

at

this

Th s,pin

26

<

opposite

of

the

playback

mode).

IC-351

pin(i3)

130K

MAD

This

circ it

varies

the

levels

of

the

PCM

signal,

fo nd

in

the

recording

signal.

(3)

The

recording

signals

o tp t

from

pins

18

and

19

of

IC-351

sent

to

pins

3

and

5

of

connector

J28

thro gh

C358,

Since

the

recorder

is

in

the

record

11

of

connector

J27

is

high.

IC-351

is

high

and

22

is

high

This

high

signal

t rns

on

Q355

and

Q356,

thro gh

which

the

recording

signal

c rrents

flow

after

passing

thro gh

the

rotary

transformers.

This

means

that

c rrent

flows

thro gh

heads

A

and

B.

(1)

The

levels

of

the

PCM

signal

and

ATF

signal,

in

the

recording

signal,

are

varied

with

VR351

thro gh

VR353

based

on

the

timings

of

the

130

KMAD

signal,

inp t

by

13

IC-351

and

the

ATFWDN

signal,

inp t

by

14.

shows

in

fig re

3-3-3.

Signal

Processing

Circuit

4- .

Recording

Data

Format

on

Tape

1)

Subcode

Area

2)

PCM

Area

3)

ATF

Area

4-2.

Signal

Processing

Circuit

Operation

4-3.

Reference

Ciock

Generation

1)

Playback

PH

Circ it

Operation

2)

DF

PLL

Circ it

Operation

3)

Master

Clock

PLL

Circ it

Operation

4)

DIN

PLL

4-4.

Subcode

RAM

4-5.

Level

Meter

Signal

4-6.

Switching

of

Signal

Flow

14

5)

Clocks

Generation

by

the

Signal

Processing

Circ it

4.

Signal

Processing

Circuit

4-1.

Recording

Data

Format

on

Tape

(1)

Ren mbering

al.].

(2)

Writing

the

SKIP

ID

(3)

A to

absol te

time

Permits

—

15

-

The

post-recording

f nction

rewites

only

the

s bcodes

d ring

the

playback

mode

nder

ATF

control..

absol te

time,

the

The

recording

format

of

s bcode

data

for

the

SV-3500

is

shows

in

fig re

4-1-1.

The

SV-3500

contains

a

post-recording

f nction

for

s bcode

data.

The

post-recording

f nction

permits

the

following

to

be

performed:

The

SKIP

f nction

ndesirable

sections

(parts

the

ser

does

not

wish

to

listen

to)

of

a

tape,

for

example

broadcast

recording.

While

the

tape

is

played

back,

the

post-recording

f nction

is

sed

to

write

the

SKIP

ID

to

any

part

that

the

ser

wo ld

like

to

SKIP.

Once

this

has

been

done,

the

tape

fast

forwards

d ring

s bseq ent

playback

operations

whenever

the

SKIP

ID

is

detected

and

playback

a tomatically

res mes

when

the

start

ID

is

detected

.

Edits

tape

containing

programs

which

have

already

been

n mbered

(e.g.

with

the

a to

program

n mbering

f nction).

Also

incl des

the

a to

ren mbering

f nction

which

a tomatically

ren mbers

the

entire

tape

for

programs

after

the

point

where

a

change

was

made.

tapes

(recorded

on

DAT

sets

which

do

not

record

the

absol te

time)

to

be

a tomatically

recorded

with

the

Once

the

absol te

time

is

recorded

onto

tape

with

this

f nction,

the

repeat

f nction

.

(e.g.

between

points

A

and

B)

can

be

sed.

7MHz)

bl,

Figure

4-1-1

in

PERIOD( s)

1/6

f

ch

1/6

f

ch

1/2

f

ch

TOTAL

90

196

7500

Table

4-1

-

16

—

Recording

density

f

ch

Calc lated

nder

the

condition

that

30

o

-

90

deg

wrap

angle,

2000

rpm

cylinder

is

sed.

Each

of

data

items

shows

above

contain

the

signals

shows

table

4-1.

'°bks.

61.0

KBPI

9.408MHz

MARGIN

PLL

(SUB)

SUB-1

POST

AMBLEjl/2

f

ch

IBG

____

ATF

____

IBG

____

PLL

(PCM)

PCM

____

IBG

____

ATF

____

IBG

____

PLL

(SUB)

SUB-2

POST

AMBLE]!/

2

f

ch

MARGIN

1/6

f

ch

1/2

f

ch

1/6

f

ch

1/2

f

ch

SIGNAL

1/2

f

ch

1/2

f

ch

ANGLE(deg)

5.051

__

0.918

3.673

0.459

1.378

2.296

1.378

0.918

58.776

1.378

2.296

1.378

0.918

3.673

0.459

5.051

420.9

76.5

306.1

38,3

114.8

191.3

114.8

76.5

4898.0

114.8

191.3

114.8

76,5

306.1

38.3

420.9

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)

(15)

(16)

N mber

of

block

11

2

8

1

3

5

3

2

128

3

5

3

2

8

1

11

ft

MARGIN(4,7MHz)

________

POST

AMBLEf

4,7MHz)

/~

ft

SUB-2

-----

/

z

1

/

PH-

(4,7MHz

,

For

subcode

/

®

IBG(1.6MHz)

/

I

!

,

DATF(788K,1.6M,130KH

z

)

l

~

>IBG(1.6Mite)

9)

PCM

!

23

-soi^

SCan

n

g

L

PLL

(4.

7MHz

)

...

For

PCM

®IBG(1.6FMz)

"

-----

/

®

ATF(788K,1.6M,130KH

z)

/

[

®

IBG

(1.6MHz)

'

/

I

®

POST

AMBLE(4,

/

I

III

I

®

PLL(

4.

7MHz)

,

For

subcode

®

MARGIN(4.7MHz

)

The

fig re

below

shows

the

recording

format

for

one

track

on

the

DAT

tape.

1)

S bcode

Area

wi

=

1

Bloc

Pac

area

T

X

Figure

4-1-2

7

8

F

-*

—

Bloc

Address

P

PP

PPP

P

Parity

P

77-

Sub-

Sub-2

Figure

4-1-3

—

7

—

£

W2

S

8bit

Sub

Code

ID

8

bit

Zq

Repeated

7

times

,

DATA

256bits

Head

scanning

direction

Data(s b

code+parity)

256bit

Block

Address

4bit

SYNC,W1,W2,Parity

32bits

s

■H

I

a

Same

as

Fig

4-1-2

W2

1

0

1

---

SYNC

---

S b

Code

ID

•Bloc

Address+Sub

Code

ID

r

—

Parity

P

Ibit

I

S b

Code

ID

3

bit

Fig re

4-1-2

shows

the

data

format

of

the

s bcode

area

which

contains

the

data

area

(256

bits)

called

the

"PACK"

area.

The

s bcode

data

is

located

in

this

pack

area.

In

one

track,

the

data

format

shows

below

is

repeated

8

times

in

S b-1

and

8

times

in

S b-2

for

a

total

of

16

times.

A

gro p

of

data

consisting

of

2

blocks

is

written

8

times

(per

track)

and

in

one

frame

(two

tracks)

is

written

16

times

to

complete

a

set

of

s bcode

data

(see

fig re

4-1-3).

For

each

rotation

of

the

head

cylinder,

one

gro p

of

data

is

written

16

times

(

2

blocks

x

8

times)

for

two

tracks.

2

3

9

A

B

C

D

E

4

5

6

Panasonic SV-3500 Quick start guide

Popular Tape Deck manuals by other brands