MEMORY MAP
The first page of the Memory Map (page 5) shows the break-
down of the large blocks of memory in the Color Computer.
One variable in this block is the video display which may be
located anywhere in the memory. BASIC normally locates the
video display at the Hexidecimal addresses 0400 -05FF.
The next two pages of the Map explain the addressing for the
PIA's. In general, the even numbered memory locations are the
I/O registers and the odd numbered memory locations are the
controll registers. Bit two of the control registers determines
what is addressed at the even numbered memory locations. If
this bit is set high (logic 1) the data I/O register is addressed.
If it is set low the data direction register is addressed. Norm-
ally the data direction register is addressed only during initial-
ization to allow configuration of the data inputs and outputs.
(By clearing bit 2and writing to the even numbered memory
location one address below, each bit of the PIA may be set as
an input or an output. A1in the data direction register sets
the bit as an output and asets the bit as an input.)
The addresses from FFC0-FFDF are the control registers for
the SAM address multiplexer chip. There are no data lines to
the SAM chip therefore two addresses are used to control each
register. In general, writing any data to an even numbered
memory location will clear the register and writing any data to
an odd numbered memory location will set the register. Ad-
dresses FFC0-FFC5 control the display mode. To select a cer-
tain display mode, both these registers and the PIA controlling
the VDG chip must be set to the proper mode. However,
it is also possible to set the SAM registers to one mode and the
PIA controlling the VDG to another mode, and obtain a
useful video mode. These cross modes are explained in more
detail in the Video Interface section.
Addresses FFC6-FFD3 control the display starting address. If
all of the registers are cleared, the display will begin at 0000.
Normally register F2 will be set causing the display to start at
0400. This feature of the SAM chip allows the display to be
paged through all of the RAM. Register P1 controls afeature
which is not used in the Color Computer. Therefore, it should
be cleared at all times.
Addresses FFD6-FFD9 control the clock speed of the CPU.
The Color Computer is designed to operate at 0.89 MHz.
Addresses FFDA-FFDD control the memory size set up of the
SAM chip. These addresses select 4K, 16K, or 32K of RAM in
the Color Computer. This memory size option should be
changed only by the reset routine in BASIC. Changes at other
times may erase the contents of RAM. Register TY, at ad-
dresses FFDE -FFDF, should be cleared at all times.
The final series of addresses in the Color Computer are the
interrupt and reset vectors. Whenever the CPU receives areset
or interrupt it will load the address at the indicated location
and begin execution at the new location. The dual set of
addresses are listed because the vectors are mapped into the
top of the BASIC ROM (BFF2-BFFF), i.e., if the CPU reads
FFFF it will actually read the contents of BFFF.
However, it is also possible to set the SAM registers to one
mode and the PIA controlling the VDG to another mode, and
obtain auseful video mode. These cross modes will be
discussed in more detail in the Video Interface section.
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