Radio shack Trs-80 User manual

1tad1e

lhaeli

•

erv1ce

®

TRS-

80

Poc

ket Computer Printer and Cassette Interface

Catalog Number: 26-3601/

26-3605

WWW

.

PC·llOO

.

INFO

CUSTOM

MANUFACTURED

FOR

RADIO

SHACK,

A

DIVIS

IONOFT

ANDY

CORPORAT

I

ON

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• • •

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at

http://www.PC-1500.info

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abo

ut

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at

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PC-

1500.in

fo

TABLE

OF

CONTENTS

POCKET

COM

PUT

ER

(26·

3601

)

I.

SPECIFICATIONS

.. ..

...

. .

......

...

..

. • . • .

.....

• . • •

..

......

•

2.

BLOCK

DIAGRAM

. . . . . . • . . . . . . . . . . . . • •• • . . . . . . . . • • . . . . . . . . • J

3.

LH581

l 1/0

PORT

. . . . . . . . . . . . . . . . . . . . . • • . . . . . . . . • • . . . . . . . . . 7

4.

CIRCUIT

Df'.SCRU'TION

. . . . . . . . . . . . . . . . . • . . • . . . . . . •• • . . . . . . . .

12

5. SE

RVI

CING

. ". . . . . . . . . . . . . . . . . . . . . . . . •• . . . . . . . . • •. . . . . . . . .

17

6.

KEY

&

POWER

S

UP

PLY

CIRCUIT

.

....

.

..

. • .

..

. .

..

. .

••

....

..

· . . 19

7.

KEY

P.

C.B

.

..

.....

.

...

.

..

...

.....

.

....

.

...

.

....

. · · • ·

..

·

..

· 20

8.

MAIN

P.

C.B

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . • • . . . . . . . . • • . . . . . . .

21

9.

LCD

SEGMENT

&

BACK

-

PLATE

SI

GNAL

. . . . . . • . . . . . . . . . . • . . . . . . .

22

10

.

PARTS

l.!ST . . . . . . . . . . . . . . .

..

. . . . . . . . . • . . • . . . . . . . . • •. . . . . . . 23

IJ.

EXPLODED

VIEW

. . . . . . . . . . .

..

• •• . . . . . . . . • • . • . . . . • . • • . • . . . . . 26

12

.

MAIN

CIRCUIT

DIAGRAM

. . . . . • . • • . . . . . . . . • • . . . . . . . . . • . • . . . . . 27

OPTIONAL

PRINTER &

CASSETTE

INTERF

ACE

(26.3605)

A)

ELECTRICAL

SECTION

I.

SPECIFICATIONS

. . . . . . . . . . . . . . . • . . . . . . . . . • • . . . . . . . . . • . . . . 28

2.

SYST

EM

BLOCK

DIAGRAM

. . . . • . • • . . . . . . . . • • . • . . . . . . . •• • . . . . .

29

3.

Cl

R

CUlT

OESCR

IPTIO

N . . . . . . . . . • • . . . . . . . . • •. . . . . . . . . • •• . . . . .

30

•4.

CI

R

CUIT

DIAGRAM

. .

..

.

..

.

..

•..

•. • .

...

..

••

.•..

· ·

..

• . • •. • · · · 33

S.

PART

AND

SIGNALS

POSITION

. - . . . . . . . . . . . . • . . . . . . . . . . • • . . . . . 34

6.

PARTS

LIST

. . . . . . . . . . . . . . . . . . . • . . . . . . . • . • • . . . . . . . . . • . . . . . 35

7.

EXPLODED

VIEW

. . . . . . . • •• • • . • •• • . . . . . . • • •• . . . . . . . . • •• • . . . 38

B)

MECHANICAL

SEC

TION

I.

SPECIFIC1\TIONS

...

..

....

- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.

MECHANISM

AND

OPERATION

. . . . . . • . . . . . . . •• . . . . . . . . . • • . • . . . 43

3. DIS,\SSEMllLY

AND

RE

ASS

E

MBLY

. . . • . . . . . . • •• • . . . . . . . . • • • • . . . 46

4.

REPAIR

ANO

MAINTENANCE

. . . . . . . • . . . . . . . . • • . . . . . . . . . . • . . . . 54

S.

OILI

NG

STANDARD

•.

, ,

.•

, . , ,

•.

. , ,

..•.

, , , • , , , . , , , , , . , . . , . . . , 64

6.

ADHENSION

STANDARD

. . . . . . . . . . . • . . . . . . . . • • . . . . . . . . . •. . . . .

65

7.

C

IRC

UIT

DIAGRAM

AND

WIRING

. . . . . . . . . . . • • . . . . . . . . • • . . . . . . .

66

8.

MECHANICAL

PARTS

UST . . . . . . . . . . . . . . . . • • . . . . . . . . • . . • . . . . . 67

9.

EXPLODED

VIEW

. . . . . . . . . . . . . . • • . . . . . . . . • • . . . . . . . . . • . . . . . . . 68

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Sharp PC

-1

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POCKET COMPUTER

(26·3601)

Cap

ac

ity:

Operacing

sequence:

Programmingh

nguagc:

Cen

c

raJ

p

r

oc

e

~i

ng

unit:

Memory

configuration:

Power consumption:

Physic

al

dimensions:

Weight:

1.

SPECIFICATIONS

10 digits (mantessa) +2 digits (

exp<mcnt)

Di

rect fonnulaentJ)'

(f

urnished wit

'.

1 priority determiningfunction)

BASIC

CMOS

S·bit microprocessor

ROM: J6KB

RAM:

3.SKB

Systenl atea:

Input b

uff

er

area:

Stack area:

0.

13W

0

.9

KB

SO

bytes

1

96

bytes

195

(W

) x 8

6(0)

x 25

.S(H

)

mm

(7~

'

x

3%"

x 1")

375g, including batter

ies

(13.2 oz)

Accessories: Soft

case

, t

wo

templates, four batteries (type

AA),

instruction manual

and

name

label.

2. BLOCK DIAGRAM

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-1

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All and more about Sharp PC-1500

at

http:f/www.PC-1500.info

2-1

. RAM MAP

USER ME

MORY

2KB

USER M

EMORY

STANDARD

2-2. L

SI

signa

l description

1. LH5801 (8-blt CMOS MPU)

1) Outl

in

e

USER

MEMORY

OPTION

IOKB

PV

EXPAND

ROMO

16

K8

SYSTEM

PROGRAM

16KB

EXPAND

ROM

I 1

6KB

* : Inhibit

to

use by redundancy

0000

l'Fff

so

SI

S2

S3

S4

S5

S6

S7

YO

YI

Y2

Ya

The

LHS801

Is

the 8-bit microprocessor

of

the

CMOS stalic type, featuring very low

p0wer

dissipation

1111d

taiie

data

processing capability.

The

M

PU

inc<>rporat01

functions Suth aa

the

LCD

backplate

signal

generator, input

poll,

external

latch clock and timer, and allows a variety

of

SY•tems

with ralativety

few

chips.

2)

Ft11U

r

es

of MPU (M

icro

Processing Unit)

• 8-bit pa,,.llel operations

• I28KB direct accessing

• Implementation

of

6·

byte general purpose register besides the occumulator while allows

the

u

se

of

three data pointers.

•

9·b

lt

tim

er

fun

ctio

n

• Tluec kinds

of

interrupts

Non·maskable Interrupt

Maskllblc Interrupt

Tlrner

interrup

t

• Instruction set

of

80

kinds

•

OMA

and multiprocessorcapab

il

ities

•

MJ>U

wait function

(memory

accessconllol)

• Implementation

of

8-l>il input

p0n

and

clock

P~

for

c~1cmal

latch

• Mem

ory

backupfunction

•

LCD

back plate

con

trol

• Clock 2.6M

Ht

(crystalcontrol)

Internal machine cycle ...... I.3MHz

Min.lnu1n

ins

tru

ction cxcute

time

...... l.

3µS

-2-

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and

more

about

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PC-1500

at

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-

1500.info

2-3.

MPU

Bl

ock

diagram

Control signa'

Back

plate

(8

bit)

•

"8

u-

• 0

'd

s

c

c 0

.2

u

t;:

:::>

·~

=~

.=

Beek

plate

driver

Address

conuol -

~

Input

port

"

18

b

it>

;

"

lrnorn1I reol1tt1

.=

2

lnttrn

el

bus

c

0

u

Date

bus

(8

bh)

~

..

/\

L u

t t i

F1

Yee

GND

Table below sho

ws

the internal register.;

of

the

MP

U

that

consiu

of

S·bit x

14

RAM

storages.

"'

PL

Su

SL

!Ill

Wt

/\

E

Uu

Ut

Vii_

Yt

Xn

Xt

......

Program

counrer

...... Stackpointer

......W

~sis

ter

••••••

A regist

er

, E register

...... U regist

er

...... Y

re&iJ

ter

...... X register

} Exclusive registers

}

G<_,

,

..

~

••""

MPU

registers

c-0

ns.

ist

of

tw

o

groups

of

r

egisters;

exclu

si

ve

regist

er

group

ilnd

general

purpose

re-g.is1er

group

.

Exclusive registcrs

co

nsist

of

program

counter

(PH, PL) (l6

bilsl,

stock pointer (SH, SL) (16 bits] , and W register (Wtl, WL)

(1

6bils].

General purpos.e registers consist

of

eight 8·hit registers; U register

(UH

, UL), X regist

er

(XH, XL),

and

Y register (YH, YL)

ca

n

be used

in

p

air

lo comprise 16·bit registers.

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at

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2-4.

description

(1) XLO, XL1

Crystal oscillator externalconnection pins

(XLO

: In, XLJ: Out)

(2)

ADO

-AD15

16 bits address bus (AOO: least significant address bit, ADIS: most significut address bit).

Tums

to

high impedance

by

the

BRQ

signal.

(3)

D0-07

Bidirectional data bus

tJSed

to write and read data of/from

the

external memory

(DO

: least significant bit,

D7:

most

significant bit).

(4)

MEO,

MEl

Memory enable signals for direct accessing

to

an external memory (the maximum I

28KB

(64KB

x

2)).

(5)

R/W

Read/write signal to perform reading operation when R(W=l and write operation when

R(W=O

.

(6) RESET

.<d

0 s

ADI

MEO

_.:,..._,/

MEI

0 1

IN

Oata

re&d

cyc

le

OUT

D:ita

wfi1e

cy

cle

The

MPU

returns

to

its initial state with a high inputlevel

to

this pin.

(7)

BRO

Bus request. A high level causes

th

e

MPU

to

respond

wi

th

the

high level BAK signal after exeuted pending command.

(8)

BAK

Bus .acknowledge appears in response with a high

BRQ

indicating

that

address bus, data bus, R/W,

MEO

and ME I are

in

high

impedance.

(9) OPF

Operation code fetch appears when the

MPU

fetches an.operation (instruct

ion

) code. OPF

is

outputted only during the

fetch

of

an

instruction

code

and is n

ot

outputted when address data,

irnrn<Xli

atc data,

or

the:

second byte

of

a two step

in

s

tructi

on

is

fetched.

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notsale this PDF

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-"'

os

ADO-ADI 5 X

x:

-----"

~'-----

MEO

OPF

---..J

Last

1;ycle

-4-

Opefation

fetch

cy~

J

c

All

and

more

about

Sharp

PC-1500

at

http

:/

/www

.

PC-

1500.info

(

10

1

INO

-IN7

Input po

rt

.

Th

e M

PU

takes the signol

on

IN

O-

IN

7 input

por

t in

to

the internal accumulat

or

as 8·bit dal3.

(111 PU,

PV,

DIS

On

ch

ip llip

Oops

output from

LS

I pins.

PU

:

Set

to

high wilh the SPU instruction and

set

to

low with the RPU instruction.

PV:

Set

to

hish with the SPV instruction and

set

to

low with the

RPV

instruction.

DIS:

Set

to

high with

the

SDP instruction and set

to

low with the RDP instruction.

(121

P,P

Strobe

ou

tput is

outputted

nonnally during

the

exccution of the ATP inst

ru

ction, used for the extem

ol

latch

of

the

A

rc

gL

<;;

ter

content

s.

(1

31

<PQ

S

Clock is

in

the

same phase as the basic clock inside the c

hip

and it

is

the basic clock for an entire system.

lt

becomes the basic clock

of

I

.3Mltt

frequency when a

2.6~11tt

crystal is connected between

XLO

and

XLI.

(141 WAIT

(1

51

(1

61

(171

WAJT

output

that

Informs the

MPU

that addressed memory

or

1

{0

device is not ready.

TI1e

MPU

is in

the

wait statewhile

this si

gn

al

is

on

.

HO-H7

I.CD

backplate signal

VA,

VB

, VM,

VDI

S

LCD

drive source.

HI

N

LCD

backplate signal. Counter input

that

generates

HO-H7.

Normally connoeted

to

HA.

(181 HA

MPU

divider

outp

ut.

(

19

1 BFO,

BF

I

M

PU

internal register llF OipOop ou

tput

(llFO) and in

put

(BFI) can be re.ct by the instruction from

th

e

MP

Uand

set

by

the BFI input. Normally used for

the

memory backupsystem.

(201 N

MI

Non-maskable i.nterrupt. A high

NMI

signal denotes

an

interrupt request,

to

wltich

the

MP

U responds unconditionally and

the control m

oves

to start the

int

e

rrup

t processing

rout

ine

aft

er

t

he

contents of

th

e

nternory

3.ddress

FFFC

is

n1

ovcd

in

to

the high

O'

rder byte

of

the

p

ro

gram c

oun

ter und

the

contents

of

tho memo

ry

addre

ss

FFFD

into

th

e low order

byte

of

the

pr

og

ram

counter.

(211 Ml

Maskable interrupt. A high

on

this signal makes interrupt request when interruptenable

is

set. The M

PU

responds uncondi·

lion.Uy

to

this request. Cpntrol moves

to

start

the

interrupt processing routine after the contents

of

the

memory address

FFF8

is moved into

the

high

order

byte

of

the

program

counter

, the contents

of

the

memory address

FFF9

are moved Into

the

low

or

der byte

of

the program counter.

(221 OD

Outp

ut

disable. When the OD signal is active the data bus i

:S

in the

output

mode.

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L')~CO:.C<J-Q

------en

ooOt--<ou)"="'('IO~-o

Q Q Q Q Q Q Q Q z Q Q Q Q Q Q Q Q

<<<<<<<

<<.:><<<<<<<<

57

56 55 54 53 52

51

50 49 48 47 46 45

44

43

42 41

40 39

R/W

58

38

07

P

f'/

59 37

06

PV

60

36

05

PIJ

61

35

04

f'f

OS

62

34

OS

XLO

63

33

02

XL! 64

82

01

WAIT

65

31

DO

IN7

66

80

MEI

INS

67

LHS801

29

MEO

1N5

68

28

OD

IN4

69

27

HO

IN3

10

26

Hi

IN2 71 25

112

IN l

72

24

H3

!NO

73

23

H4

74 22

HS

75

0

21

H6

76

20

H7

g a 4 5 6 7 3 9

10

111213

14

l~

IG

17

1819

f--

"

"'

a -" 0

"'

~

u

;:,:

0 <

c:l

.... ....

l;r.

<

<I>

</)

<

""

"

""

Q.

< u

>;:;:--:i::

-

"'

Ol

0:

> Ol 0

"'

> > > > z

......

::c

0

"'

Do

notsale this PDF

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and

more

about

Sharp

PC-1500

at

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:/

/www

.

PC-1500.info

3.

LH5811

11

0

PORT

(1)

Outline

The

LH

SS

l I 1/0 port

is

th

e s

ingle

chip

LSI

of

CMOS

s1a1ic

circuit thal

ca

n

be

connecl

ed

with a

general

iPUrpos

e 8·bit Cl'U.

It

ha

s lhe

fo

llowing

fun

clions:

(I)

Two pairs

of

S·bit bidlreclional pons

(2)

One

pair

of

8-bit bidirectional ports

(3) Two li

nes

of

interrupt request inputs. one

of

lhem

is

the

input

from

pon.

(4)

One

line

of

interrupt request oulpul.

(5) C

PU

wait control

(6) Ser

ial

control

(2)

Funct

i

on

s

(I)

Port

s.

PAO-

PA

7 and

PBO

-

Pl

l7,can

be

programmed

fo

r 1

/0

dir

ec

t

ions

by

ea

ch bit.

The

CPU

can

acce

ss

PAO-

PA7

and

PBO-

PB7

as

though o

ne

Joca

lion of

memory

.

(2)

PCO

-

PC7

is

the port

of

output type.The C

PU

can access it

as

th

ough one location

of

me

mory.

Also,

lhe latch clock

P9

to the

PC

pon

can

be

supplied directly

from

1n

ex1emal

source.

(3)

LHS81

J incorporates two interrupt request inpuls,

JRQ

and P67,

when

apply inlerrupt requ

es

l

of

the

CPU

at lhe

rising

edge

of

the inpul

whe

n the corresponding bit

of

the internol

mask

regist

er

is

"I".

Signal

PB7

represents the 8th

bit

of

the poll

PB

and

ii

needs

lo

be

In

the input mode

when

the interrupt inpul

is

applied.

(4)

The

I.

H58J

J h

as

a

CPU

wail conlrol circuit

which

11

s

es

two output

Hnes

of

memoiy enab

le

signals

for

a memory Iha!

has

slower

acc

ess

t

ime.

In

a

dditi

on. two

inpu

t

line

s for

th

e wait conditions

are

used

.

Six

differe

.

nt

of

access

times

can

bechosen byprogr:unming.

(5) The following funclions

>re

provided

for

serial conlrol.

A. Serialdata

transmi$$ion

Se

rial

da

ta trans

mi

ss

ion

is

used

~11he

formal

ofs

tarl bit/8

-bil

data/2 slop

bil

s.

Trillls

mission

clock

is

programm

ab

le

by

changing

internal and

external

clocks,

as

well

as changing

the

clock rate;

I

/I,

1/2, 1

/l

28, 1/256, 1/512, 1/1024, 1/2048and 1/4096

of

the basicclock.

B. Serial data reception

When

a stan

bi

l

is

re.cei

\•ed

in

th

e

idle

state, 8 bits of

data

is

receive

d.

and

st

ored

in the

int

erna

l

regis

ter

a.

nd

th

e

in1e

rrupt

requ

est

fl

t1

R

is

set

on

.

Receplion

cl

oc

k l.s

se

nt

from

the exlernal clnck 011d

must

be

synchronizedwith the

se

rial

d313

Input.

C.

LCD

driver

con1rol

The

LCD

driver Is

COMCCted

with three signal lines

of

the lransmissionclock, a

serial

data bus, and a synchronous

signal line

10

carry o

u1

da

ta transfer

for

chip

selec1,

addressing,and

do

la

read

/write.

For

the

trans

ml~sion

c

lock

in

thi

s

cas

e,

the clock

rate

can

be

pr

ograr

nmed

in

th

e

sa

me

manner

as In

the

seri

al

datu

transmission

cl

oc

k.

(Transmi

ss

ionclock to the

LCD

driver

is

IMll

z.)

D. Pul

se

waveform

The pulse

waveform

can

besenl out in continuation.

Eiglit

sons

of

frequencies are programmable; 1/1, 1/2, 1/12

8,

1/256, l/5I2, 1/1024, and 1/4096

of

the b

asic

clock.

E.

Transmission

to

audio

cassett

e

tape

reco

rder

Themodulated

signa

l can be senl

from

the

SDO

ou1put in the

forma

t

of

s1ar1

bit/8·bll data/2 stop

bit

s.

Modulation

clock

.

s,

FX

and

FY,

ca

n

be

set

sepuatcly

to

an

yof

cl<>c

krate; I/64, I/

128

, I

/256

, I

/S

12,

a

nd

1/

1024

of

the basic clock. ·

Do

notsale this PDF

!!!

_,_

0

::J

0

.....

(J)

Ql

CD

.....

;;;r

ur

-u

0

,,

lo

I

IN

T

IRO

...

CLO

1.

C

soo

C

l~

I SOI

'A

IT

D!oeEI

r-

---

-z-

-----

-· -

----

-

T--

r--

·-

--

---

--- --

---

~---

-

--

---,

I

Vet

L.

I

V

SSI

r+

vsst

~

U

::I

:l

4-

I

Odver [

DATA

BUS

'4-

·

~

___.

J_J

-i. :

&

ctoe

k

J-

co~t~ol

_J

...

WAIT

I.

;

cont

t

OI

r---'

Serl

ti

S•rl1I

con

trol 1

~~;

,~

ot

I

A.

r •rtnJmluion

re«ivtr

1-t--;

J con1'rol

'°ntrof

J----.t

1r

.r.

.~

J n :

~::

i

~ter

} [ 1F

P

e:~'te

}

~oistor

} [

~evister

r L } U l I

'~

.

~

} i

,

I-- I--

71---+---l

•

1-

----'

,f

I.

!

~

. }

r.

f--

I-

1

f-

1---

Ch;p

r;--!

11

I

~°?~~~er

~

OP.,?-

} ~

Of>B

}

conu~

s.

r-evisttr

119

1

,ttr

:

}

~AO~

I

OUT

PUT

DAA L

OUT

PUT DOB

l__

[ DOB control

L..._

I

control

reg

ister

_r

coniro1

reg

ister r rt01ner I

I

L-

-

-"--

--

------

~

._}_

______

____

{t

__

._

__

L_<..

__

___

_ J

l'A

0-7

JJ00

•7

PC0 - 7 P"

00-7

VSSI

•

\ISSt=G

XJ>

VCC•

45

~

0.&V

1/0

PORT

contro

ll

er

svrte.m

block

dlagrem

)>

WI

Q)

:J

WO

a.

OM

EO

3

0

~

<I>

Q)

CT

0

M

MO

c:

-

(/)

IV

\\

' ::r

Q)

RSO

-a

RS I

-0

RS2

()

RS8

'

~

cso

01

CSI

0

m 0

Q)

~

::r

::::

"O

r

-0

()

'

~

(Jl

0

:;

·

0

A

ll

and

more

abo

ut

Sharp

PC-1500

at

http:/lwww.

PC

-

1500.in

fo

1/0

port

(LH5811)

Signal In/out Connection Functional description

No. Name

I

PAI

In/out Key Port A input/output. Key strobe.

~

7 PA7 In/out Key Port A input/output,Key strobe.

8

GND

In

Power

OV

9

PBO

I

n/out

Option Port B input/output

JO

PBI I

n/out

OptiO

ll

Port B input/output

11

PB2 In CMTIN Port ll input/output.Cassette tape data input..

12

PJ~3

In

GNO

Domestic}export

spe

.cification select

(Domestic)

VCC

(Export)

13

P84

In GND

Us

e.r

area

dctcnninati

on

14

P\l:5

In

µP0!990C

Clock input from TP tenninal

of

the timer

JC

IS Pll:6 In µPOl990C Data input from the DA

TA

OUT

te

m1inal

of

•he

timer IC

16

PIP

In

Key BREAK key inp

ut

(interrupt input)

17

P¢

In

GND

PC

port latch clock input

18

PC'O

Out µPD 1990C Data output to

the

DA

TA

IN

tem1inal to

the

timer IC

19

PC

I

Out

µPDl990C Sirobcoutput to

the

STB tenninal fo the timer

IC

20 PC2

Out

µP01990C

Clock

outp

ut

to

the

LK

tenn

i.n

al

of

the

tirner

IC

21

PC3

Out

µPD1990C

Tin

i

er

IC

control

signal

outp

ut

22 PC4

Out

µPDl990C Timer IC controlsignal

output

23

PCS

Out

µP

D1

990C Timer

IC

cont

ro

l

signal

output

24 PC6

Out

Buzzer

2S

PC7

26

cso

In

CPU Chip select input connected

to

AD12

27

CS!

In

CPU Chip select inputconnected 10 AD13

28

CS2

In

Decoder IC Chip select input connected

to

Y3

of

the chip select decoder

IC

Do

not

sale

this

PDF

!!!

-9

-

All and more about Sharp PC-1500

at

http:/lwww.PC-1500.info

1/0

port

(LH5811)

Signal

Infout Connection Funclional description

No. Name

29

RSO

In

CPU

Internal register and operationstlcct signal

l l ?

~

l

32

RS3 In

CPU

Internal register and 0peration select signal

33

R/W

In

CPU

Read/write input

34 MEI In

CPU

Memo

ry enable

35 M

EO

In

CPU

Memory enable and 1

/0

port controllerenable

36

WO

In

Option

Wait

condition

input

37 WI In Option

Wah

condi

ti

on

inpu

t

38

GND

In Power

ov

39

v

cc

In

Power +SY

40

DMEI

Out Decoder

ROM

enable

41

DMEO

Out

ROM,

option ROMenable

42

WAIT

Out

CP

U

Wait

signal

to

theC

PU

43

INT

Out

CPU

Interrupt request to the

CPU

44

RESET

In

RF.SET

circuit

ln

_

itial

reset

signal

45

IR

Q In Option Jnt

crrupl

request

inpu

t

46

¢OS In

CPU

Basic

clock input

47

CLI

CLO

Not used.

Serial

data receptjon clock input

48

SDI (VCC) Not used. Serial data reception input

49

LC

NC

Not used.

LC

Ddri.er synchronizing

signal

50

CLO

In

CLI

Serial data transmission/receptionclock

51

SDO

In

CMT

Serial

transmission

&reception

data.

Use

for

thecassette

tape data output.

52

DO

lnjout

CPU

Data bus

?

~

?

59

D7

lnjout

CPU

Data bus

60

PAO

Out

K

oy

P

ort

Ainpu

t/

output.

Use

d as

th

e key strobe.

Do

notsale this PDF !!! -

10-

All

and

more

about

Sharp

PC-1500

at

http:l/www.

PC-

1500.info

R

ead/

wr

ite

ti

mi

ngs

for

1/0

po

rt

A0

- 1$

::x

____

___

_

_,

c

MREQ

°'t

_

_,

.,

..

---

-

-----

--

lli'

AlT

*

--

~

u

o-

1-

--

--c==

=)-

-

(a) D

ata

read fr

om

1/0

po

rt

A0

-1

5

:JC

__

_

____

_

~x:::

RJ

•-

--~

,

.__

__

_

~

r--

WAI~

00

- 1

--

c=

===

=

==>

-

(b) Da

ta

write to 1

/0

port

Do

notsale this PDF

!!!

N

OT!>:

Clock ¢ is furnished to the

i\()S

input

of

the 1

/0

por

t.

MREQ

•

is an

invers

ion of MERQ

of

Z·

80

and

fur

n

i1

hed to the M

EO

of

the 1/0 port.

WA

IT

•

is

an

in

version

of

WAIT

of

the 1

/0

po

rt

and

furnished to

the

W

AJT

input

of

Z

·SO.

- 11-

All and more about Sharp PC-1500

at

http

:/

/www.PC-1500.info

1. Chip SelectCircuit

c

r

u

V o

,.

~

OMEO

T

D

MEO

ADS

4.

CIRCUIT

DESCRIPTION

·rC4011139fo. T

C40Hl38f

Vss

vs

s

vcc

V<;c

;

::

) :

RA.M3

C"l'C5Sl7

AF')

1u

Mox)Jlc

Uni

t

St

S3

S6

1

i.>

I/

{)

l°

Qr

t

Th Di!'i)lay

chip

L. 3

~

----

-----•

To

RA.\11, 2

<T

C5514

P)

~-------

------

0--

•

To

1/0

PORT(l.Jl58J

I)

~-

•To

ROM

(SC6J3

J28E')

L--------------------

+To

Module

Unit

'-------------------+

To

tttod

ule Unit

T

C•

OH

1

ss

Int

ern.a

l logic:

Truth

Table

v;

In

pu

t

...

~·A.11

1.

1>

:ili

tt:

C>

Output

vr

°'

·

-·

·' " c :!!_

..

.,

Vi

..

.

,.

"

'·

..

,,

$ T ., " " " " H H " H

~

s1a

,

r.

<;r

• .

·.

" ·'· ·=·

·:·

v " " " " " " " "

<:

·

~·

" "

<-

.,

. " " " " H " H "

"'

" L L L L L L • " " " " " "

c

y;

" L '· " L L " L " " " " " "

" L L L " L " " ' " H " " "

{™

Yr

VI

AllLt:

ttj;

Cl w

" 1. L " " '· " " " L " " " "

" ' L '· '· " " " " -;;- ' " " "

" L L " L " " " " " " L " "

"

..

'· '· " " " " " " " " L "

" L L " " " " " " " " " " L

y.;:

-

12

-

Do

notsale this PDF

!!!

A

ll

and

more

about

Sharp

PC-1500

at

http:/lwww.PC

-

1500.in

fo

TC40H139 Truth Ta

ble

n

YO

Input

Out

put

EtW!U:

SELECT

G A B

YO

Yl

Ya

Y8

Yi

H * * H H H H

L L I. L H H H

A

Y2

L H L H

I.

H

ill

V3

c L L H H H L H

L H H H H H L

*=

I

rr

ele

Vll

nt

• Selection

of

I

YO

- I

Y3

by

the

decoder

IC

(TC40Hl39H) isdone when

the

gate signal (IG) input

BFO

is

low.

YO

With low state

of

AD

14 and ADI5, the

YO

outpu

t becomes low

to

select the syst

em

ROM

area

of

the module unit.

(IYli)

(0000 -

3FFF

address setup)

Yi

With ltigh

st

ate

of

ADl4

and low state

of

ADI5,

the

YI

output

becomes low to select the gate (G2A)

of

the

IC

(IYI)

(TC40HJ38F).

(4000-7

FFF

add

re

ss

setup)

Y2

With low sta

te

of

ADl4 and high state

of

ADIS, the Y2

output

becomes low

to

select the expansion

ROM

•rea of

(1

Y2)

the

module

un

it.

(8000-

BFFFaddress setup)

Y3

W

it

h high state

of

A

Dl4

and ADIS,

the

Y3

output

becomes low

to

select

the

system program ROM (SC-0131281')

(I

Y3) a

nd

th

e

1/0

port (LHS8

11

).

(COOO

-

FFFF

address setup)

• Selection

of

SO

-S7 by the decoder

IC

(TC40

Hl3

8F)

is done when t

he

gate signal input

MEO

(GI)

is high,

YI

(GiA)low,

and

G2B

.is low (wltich is nom1ally low).

SO

Wi

th

all

of

AD

II,

ADl2

and ADJ3 in low sta

te

,

SO

goes

to th

e low state and selects

the

RA

M3

(TC5517AF).

(YO)

(4

000-

47

FF

address setup)

SJ With h

igh

state

of

ADI I and

Jow

sta

te

of

ADI2 and AD13,

SI

goes to

the

low state

to

select tlte option user

RAM

(YI) area. (

4800-4FFF

address setup)

S2 W

ith

low sta

te

of

ADI I and high state

of

AD12

and

low state

of

ADJ3, S2 goes to the low state

to

select the option

(Yi)

RAM

;11ea.

(5000-57FF address setup)

S3 With high sta

te

of

ADJ!

and

AD

l2

and low state

of

ADl3,

S3 goes

to

the

low state

to

select

the

option user

RAM

(Y3) area.

(5800-

SFFFaddresssetup)

S6 Wi

th

low state

of

ADI I and ltigh state

of

ADl2

an

d AD13, S6 goes to

the

low state

to

receive

th

e interrupt input

(Y6) from

•n

option in

to

the

1/0 port. (7000 - 77

FF

~

dd

ress

se

tup

)

57 With all

of

ADI

I;

ADl2,

and ADl3 in ltigh state, S7

goesto

the lowstate to select

the

system

111emory

RAM! and

(Y7) 2 (TCSSJ4P). (7800 -

7FFF

addres setup) RAMI and

RAM2

;11e

4·bit

RAMs

, independently used to assume low

order

and high order bits

to

comprise one byte

with

a pair

of

4 bits each.

• Sele

ct

ion

of

2

Y2

and 2Y3 by

the

de<:oder

IC

(fC40Hi39)

is

done when

th

e gate

of

2G

becomes active

with

the

selection

of

the TC40H1

38F

output, $6(Y6).

2

Y2

With low state

of

AD8

and hl

gh

state

of

DMEO

,

th

e

ffi

output

goes to

the

low state

so

tha

t

the

NANO gate

output

(V2)

V2

is turned ltigh

to

select the display chip I and 3 . (7

60

0-

76FF

addresssetup)

2

Y3

Wit

h ltish state

of

AD8 and

DMEO

, t

he

2Y3

ou

tput

goes to

th

e low state so that the NA

NO

g•t•e

out

V3 is turned

(V3) high to select the display chip 2 and 4. (7700 -

7FFF

address setup)

• Display cltip (SC882G) is a 4·bit

RAM

, comprised

of

one byte

of

da

ta

wi

th 4 low order bits and 4 ltigh order bits

of

data,

so tlt3t even the cltip select signals are used in pair

of

cltip I with cltip 3

•nd

ch

ip 2 with chip 4.

Do

not

sale

this

PDF

!!!

-13-

Al

l and more about Sharp PC-1500 at http://w

ww

.PC-1500.info

2! Buzzer circuit

SDO C

MT

OUT

10

i

-0

rc6 i 9

p

O PB2

1:-

1

,-

1

-

~-t<}

-

..

R

T

C

MT

IN

Yee

The control signal CMT OUT is sent

ou

t from

the

pin S

OO

of the 1/0 port which so

un

ds the buzzerincombination with

the

lowm

1e

or

either

the

programmed output from

the

1/0 port

or

C

MT

IN

se

nt

from the cassette tapedeck.

3)

RAM

R/W

signal circuit

R/W

RAM

I

R/

W

CPU

ADtO

4)

ON key

doub

le action preventive circuit

Yee

DAP

202

This circuit prevents writing

if

Al}

IO

Is

in high state during

the write mode (when

R{W

is

'

°i:r

iThis

is

to

preve

nt

wrong

operation when a specific key.

or

m

is

pushed with-

out perfonning "

NEW

0 E!llTER" after battery replacement.

This circuit consists

of

the Schmitt circu

it

that prevents the

possibility

of

setting

the

input flag

or

the

Ui58

I I 1/0

p0rt

which depends on how

th

e ON key

i.s

pushed.

BF

I

-

-N'l'-.....__~

s'°i

)'

4

'--

._

_

_,,

I

/0

POR

T

TC50H

OOI

I

~

36PF-89PF

Do notsale this PDF !!!

PB7

-14

-

A

ll

and

more

abo

ut

Sharp

PC-

1

500

at

http:/lwww.PC

-

1500.in

fo

5)T

im

er

/co

u

nt

er circuit

PC.5 C2

PC4

'

0

PC3

...

0

PCI

"'

-l

Cl "

co

"O

0

"'

ST

B "'

0

~

cs

;,..

(")

"'

()Q

f'CoO

PC2

DATA

HI

~

PS6

CNO

PB

S

Yoo

XTAL

OE

TP

DATA

OUT

Cl.K

Vee

1---~

a

32.768kH1.

y

1. Outline

As shown in

the

le

ft

,

the

µPD I990AC

is

used for the time keeping

JC

to

count

hour/minute/second/ml)nlh/day.

2.

Main

fu

n

ctio

n

of

µP

D1

990A

C

Time data

is

in the

BCD

form

and

is

judged by means

of

comparison. How-

ever,

day

of

week

is

n

ol

used

with

this

chip and hour

is

represented by 24-hour

system.

r

-

--

----

~-+-+-~~

~~~~~~

--'

,

Ve

e :

: + I

'-

-

...

- - --·

110

CPU

Reset

IL

S&

I

IMS&

!

OI

N

2 5 2 B

~

Seconds Minut

es

Houn

Dav

Wee

k

Mo

nth

• I • • I 4 I 4 4

Bits Bits Bits 8iu

Blu

Blc:

s

• I •

Sits

Sib

• I •

Bits Bits

Pi

n Signal In/out

Descrip

tion

No.

N:une

I

C2

Jn

'Mode select signal C2=0

2 Cl ln Mode select signal

Cl

co

Mode Data In

/o

ut

mode

3

co

In Mode select signal 0 0 0 Regi!ler

ho

ld

0 I I Register shift

I 0 2 Time set

I I 3 Time read

4

STB

In Strobe. Command

is

latched

by

the strobeSTB.

Do

not

sale

this

PDF

!!!

- 1

5-

All and more about Sharp PC-1500

at

http://www.PC-1500.info

5

cs

In

Ch;p

se

le.;t: d

isa

ble

CLK

and

STB

input and

OAT

AOUT output by the

CS

input.

All

input/output are inv

alid

unless

CS

is

hjgh.

STB l

'\

Lnte

rn;il

~TB

(comman<l

latch clock)

J

cs

CLK ] '

J Internal

.CLK

(40-bit serial clock)

OE

1

"\

J Inte

rnal

OE

(gate

in

put

of

OAT

OUT)

6

OATALN

ln

Oat

a input

signa

l (40-bit serial data)

7

GNO

In

OV

8

CLK

In

40

-bit

shift

regi$ter

clock

(Data

in

put

/output

is

carried

out in

synchron

ization

withC

LK

.)

9

DATA

Out Data output

signal

(40·bit

ser

i

al

data)

O

UT

10

TP

Out

Timer

p

uls

e output:

to

CO

, Cl,

C2

du

ring

command

ass

ignmen

t.

II

OUT

In

Output enable: input tocontrol the output

of

DATA

OU

T.

EN

ABLE

12

XTAL

In

Basic

clock, 32.768kHz

13

XTAL

In

Same

th

e

above

14

Vl>D

In

Source

po

wer

input, connected to

VGG

(4

.7V).

6)

Power supply circuit

T

he

power supply

is

incorporated in a

single

resin

molded

IC

that consists

of

the stabilizer circui

t,

temperat

ur

e compensation

circuit.

and

bleeder

circu

it.

v

"'"'

.

int-

(6>

'Po

'

L

lX2

I4

-vr

tSS98

VGG

HI-MIC

2

SB

710

13

2Sll779

¥

ID

8

: $

'r.R

-!-

AOAPT

Jae

k

-::-u~t-S

-'

~ 2SCI

623

~

Irr

t2 9

llf.O

\'R

l

7~

:

~1

3

-

X4

-

II

2

-:-

tO

6 1

~

V

R

2

~

r-

I

1

"T

...

,,,

5

2SJ8

4 •t

= ± (;ND

Adjusting method

I.

Apply 7

.0

± 0.

2V

DC.

at

p-Oint

· @ .

2. Turn YR! to

read

at

VCC

4.7 ±

0.02

V

DC

from

GND

.

3. Turn VR2 to read at

Vl>JSP

3.7 ± O.otV

DC

from

GNl>.

Supply

vo!lagc

: I.

SV

x 4

7V

O.OSV

VCC:

4.7V

VCC

:

4.7V

±0.02V

VDI

S

P:

3.7V t O.

OIV

(In the

case

of25°C)

Do

notsale this PDF

!!!

-16-4.

Adj

ust

ing condition

is

25°C.

A

ll

and

more

abo

ut

Sharp

PC-

1

500

at

http:/lwww.PC

-

1500.in

fo

5.

SERVICING

1) Measures against irregular condition

In a rare

cas~,

all keys

on

the keyboard might.become inoperative, including the I

B~~KI

key, when a strongexternal noise

interference

IS

met

or

when

a

strong

unpact

is

given

to the

maclune

body.

Wh

r

suclJa

condition is encountered, keep the ALL RESET key pushed for a period

of

about 15seconds while depressing

the

~

l(

key.

llRliAK

Oepressi

ng

I

ON

Ikey.

.........

'

All

reset

Use

the

tip

of

a ball point pen

to

pus.h

the

ALL

RESET

SW.

Do not

use

the

ti

p

of

somethinpuch

as

a

pencil

of

which the tip might break. Also, do not use

anything with a sharp edge such as a needle.

Wait for

th

e prompt l"NEW

O?:

CHECK"

to

appear on

the

di<play,

then

push I

CL

I

NEW

0 \ENTER!.

If

the

prompt

"NEWO•: CHECK" does not appear,

try

the

above entryagain.

DO

not

use

the ALL RESET switch except for

the

above operati

on,

or destruction

of

the

progtam, data,

an

d reserve contents

Will

OCCUI',

2) How

to

replace

FPC

(Flexible Printed Cable)

To

replace

the

FPC

that

connect the Key

PCB

with

the

Operation

PCB

, the following procedure should be used.

Soldering

Do

not

sale

this

PDF

!!!

-17-

Since the Operation

PCB

is connected with

the

FPC

by means

of

th

e crimp metal,

the

Key

PCB

is dis·

connec

te

d from

the

Operat

io

n

PCB

after removing

the

crimp metal.

Radio Shack TRS-80 User manual

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