Samsung M471B1G73AH0 Instructions for use

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M471B1G73AH0
Rev. 1.0, Jul. 2010
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datasheet
204pin Unbuffered SODIMM
based on 4Gb A-die
78FBGA with Lead-Free & Halogen-Free
(RoHS compliant)

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Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
Revision History
Revision No. History Draft Date Remark Editor
1.0 - First Release Jul. 2010 - S.H.Kim

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Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
Table Of Contents
204pin Unbuffered SODIMM based on 4Gb A-die
1. DDR3 Unbuffered SODIMM Ordering Information........................................................................................................ 4
2. Key Features................................................................................................................................................................. 4
3. Address Configuration .................................................................................................................................................. 4
4. x64 DIMM Pin Configurations (Front side/Back Side)................................................................................................... 5
5. Pin Description ............................................................................................................................................................. 6
6. Input/Output Functional Description.............................................................................................................................. 7
7. Function Block Diagram:............................................................................................................................................... 8
7.1 8GB, 1Gx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ....................................................................... 8
8. Absolute Maximum Ratings .......................................................................................................................................... 9
8.1 Absolute Maximum DC Ratings............................................................................................................................... 9
8.2 DRAM Component Operating Temperature Range ................................................................................................ 9
9. AC & DC Operating Conditions..................................................................................................................................... 9
9.1 Recommended DC Operating Conditions (SSTL-15).............................................................................................. 9
10. AC & DC Input Measurement Levels .......................................................................................................................... 10
10.1 AC & DC Logic Input Levels for Single-ended Signals.......................................................................................... 10
10.2 VREF Tolerances.................................................................................................................................................... 11
10.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 12
10.3.1. Differential Signals Definition ......................................................................................................................... 12
10.3.2. Differential Swing Requirement for Clock (CK-CK) and Strobe (DQS-DQS) ................................................ 12
10.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 13
10.3.4. Differential Input Cross Point Voltage ............................................................................................................ 14
10.4 Slew Rate Definition for Single Ended Input Signals ............................................................................................. 14
10.5 Slew rate definition for Differential Input Signals ................................................................................................... 14
11. AC & DC Output Measurement Levels ....................................................................................................................... 15
11.1 Single Ended AC and DC Output Levels............................................................................................................... 15
11.2 Differential AC and DC Output Levels ................................................................................................................... 15
11.3 Single-ended Output Slew Rate ............................................................................................................................ 15
11.4 Differential Output Slew Rate ................................................................................................................................ 16
12. DIMM IDD specification definition ............................................................................................................................... 17
13. IDD SPEC Table ......................................................................................................................................................... 19
14. Input/Output Capacitance ........................................................................................................................................... 20
14.1 2Rx8 2GB SODIMM .............................................................................................................................................. 20
15. Electrical Characteristics and AC timing ..................................................................................................................... 21
15.1 Refresh Parameters by Device Density................................................................................................................. 21
15.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 21
15.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 21
15.3.1. Speed Bin Table Notes .................................................................................................................................. 25
16. Timing Parameters by Speed Grade .......................................................................................................................... 26
16.1 Jitter Notes ............................................................................................................................................................ 29
16.2 Timing Parameter Notes........................................................................................................................................ 30
17. Physical Dimensions :................................................................................................................................................. 31
17.1 512Mx8 based 1Gx64 Module (2 Ranks) - M471B1G73AH0................................................................................ 31

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Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
1. DDR3 Unbuffered SODIMM Ordering Information
NOTE :
1. "##" - F8/H9
2. F8 - 1066Mbps 7-7-7 & H9 - 1333Mbps 9-9-9
- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)
2. Key Features
• JEDEC standard 1.5V ± 0.075V Power Supply
•V
DDQ = 1.5V ± 0.075V
• 400 MHz fCK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin
• 8 independent internal bank
• Programmable CAS Latency: 5,6,7,8,9
• Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
• Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066) and 7(DDR3-1333)
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
• Bi-directional Differential Data Strobe
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C
• Asynchronous Reset
3. Address Configuration
Part Number2Density Organization Component Composition Number of
Rank Height
M471B1G73AH0-CF8/H9 8GB 1Gx64 512Mx8(K4B4G0846A-HC##)*16 2 30mm
Speed DDR3-800 DDR3-1066 DDR3-1333 Unit
6-6-6 7-7-7 9-9-9
tCK(min) 2.5 1.875 1.5 ns
CAS Latency 679tCK
tRCD(min) 15 13.125 13.5 ns
tRP(min) 15 13.125 13.5 ns
tRAS(min) 37.5 37.5 36 ns
tRC(min) 52.5 50.625 49.5 ns
Organization Row Address Column Address Bank Address Auto Precharge
512Mx8(4Gb) based Module A0-A15 A0-A9 BA0-BA2 A10/AP

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Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
4. x64 DIMM Pin Configurations (Front side/Back Side)
NOTE :
1. NC = No Connect, NU = Not Used, RFU = Reserved Future Use
2. TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules.
3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back
1VREFDQ 2VSS 71 VSS 72 VSS 139 VSS 140 DQ38
3VSS 4 DQ4 KEY 141 DQ34 142 DQ39
5 DQ0 6 DQ5 73 CKE0 74 CKE1 143 DQ35 144 VSS
7DQ18 VSS 75 VDD 76 VDD 145 VSS 146 DQ44
9VSS 10 DQS077 NC 78 A153147 DQ40 148 DQ45
11 DM0 12DQS079 BA2 80 A143149 DQ41 150 VSS
13 VSS 14 VSS 81 VDD 82 VDD 151 VSS 152 DQS5
15 DQ2 16 DQ6 83 A12/BC 84 A11 153 DM5 154 DQS5
17 DQ3 18 DQ7 85 A9 86 A7 155 VSS 156 VSS
19 VSS 20 VSS 87 VDD 88 VDD 157 DQ42 158 DQ46
21 DQ8 22 DQ12 89 A8 90 A6 159 DQ43 160 DQ47
23 DQ9 24 DQ13 91 A5 92 A4 161 VSS 162 VSS
25 VSS 26 VSS 93 VDD 94 VDD 163 DQ48 164 DQ52
27 DQS1 28 DM1 95 A3 96 A2 165 DQ49 166 DQ53
29 DQS1 30 RESET 97 A1 98 A0 167 VSS 168 VSS
31 VSS 32 VSS 99 VDD 100 VDD 169 DQS6170 DM6
33 DQ10 34 DQ14 101 CK0 102 CK1 171 DQS6 172 VSS
35 DQ11 36 DQ15 103 CK0104CK1 173 VSS 174 DQ54
37 VSS 38 VSS 105 VDD 106 VDD 175 DQ50 176 DQ55
39 DQ16 40 DQ20 107 A10/AP 108 BA1 177 DQ51 178 VSS
41 DQ17 42 DQ21 109 BA0 110 RAS 179 VSS 180 DQ60
43 VSS 44 VSS 111 VDD 112 VDD 181 DQ56 182 DQ61
45 DQS246 DM2113 WE 114 S0 183 DQ57 184 VSS
47 DQS2 48 VSS 115 CAS 116 ODT0 185 VSS 186 DQS7
49 VSS 50 DQ22 117 VDD 118 VDD 187 DM7 188 DQS7
51 DQ18 52 DQ23 119 A133120ODT1189 VSS 190 VSS
53 DQ19 54 VSS 121 S1 122 NC 191 DQ58 192 DQ62
55 VSS 56 DQ28 123 VDD 124 VDD 193 DQ59 194 DQ63
57 DQ24 58 DQ29 125 TEST 126 VREFCA 195 VSS 196 VSS
59 DQ25 60 VSS 127 VSS 128 VSS 197 SA0 198 NC
61 VSS 62 DQS3129 DQ32 130 DQ36 199 VDDSPD 200 SDA
63 DM3 64 DQS3 131 DQ33 132 DQ37 201 SA1 202 SCL
65 VSS 66 VSS 133 VSS 134 VSS 203 VTT 204 VTT
67 DQ26 68 DQ30 135 DQS4136 DM4
69 DQ27 70 DQ31 137 DQS4 138 VSS

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Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
5. Pin Description
NOTE:
* The VDD and VDDQ pins are tied common to a single power-plane on these designs.
Pin Name Description Number Pin Name Description Number
CK0, CK1 Clock Inputs, positive line 2 DQ0-DQ63 Data Input/Output 64
CK0, CK1 Clock Inputs, negative line 2 DM0-DM7 Data Masks/ Data strobes,
Termination data strobes 8
CKE0, CKE1 Clock Enables 2 DQS0-DQS7 Data strobes 8
RAS Row Address Strobe 1 DQS0-DQS7 Data strobes complement 8
CAS Column Address Strobe 1 RESET Reset Pin 1
WE Write Enable 1 TEST Logic Analyzer specific test pin (No connect
on SODIMM) 1
S0, S1 Chip Selects 2 VDD Core and I/O Power 18
A0-A9, A11,
A13-A15 Address Inputs 14 VSS Ground 52
A10/AP Address Input/Autoprecharge 1 VREFDQ
VREFCA
Input/Output Reference 2
A12/BC Address Input/Burst chop 1 VDDSPD SPD and Temp sensor Power 1
BA0-BA2 SDRAM Bank Addresses 3 VTT Termination Voltage 2
ODT0, ODT1 On-die termination control 2 NC Reserved for future use 3
SCL Serial Presence Detect (SPD) Clock Input 1 Total 204
SDA SPD Data Input/Output 1
SA0-SA1 SPD Address 2

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Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
6. Input/Output Functional Description
Symbol Type Function
CK0-CK1
CK0-CK1 Input
The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and
falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read opera-
tions is synchronized to the input clock.
CKE0-CKE1 Input Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks,
CKE low initiates the Power Down mode or the Self Refresh mode.
S0-S1 Input
Enables the associated DDR3 SDRAM command decoder when low and disables the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is
selected by S0; Rank 1 is selected by S1.
RAS, CAS, WE Input When sampled at the cross point of the rising edge of CK and falling edge of CK, signals CAS, RAS, and WE define
the operation to be executed by the SDRAM.
BA0-BA2 Input Selects which DDR3 SDRAM internal bank of eight is activated.
ODT0-ODT1 Input Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR3 SDRAM mode register.
A0-A9,
A10/AP,
A11
A12/BC
A13-A15
Input
During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of
CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the
cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke
autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-
BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle,
AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pre-
charged regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to pre-
charge.A12(BC) is sampled during READ and WRITE commands to determine if burst chop (on-the fly) will be
performed (HIGH, no burst chop; LOW, burst chopped)
DQ0-DQ63 I/O Data Input/Output pins.
DM0-DM7 Input The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input
data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect.
DQS0-DQS7
DQS0-DQS7I/O
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is
sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR3
SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to
the crosspoint of respective DQS and DQS.
VDD,VDDSPD,
VSS
Supply Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
VREFDQ,
VREFCA
Supply Reference voltage for SSTL15 inputs.
SDA I/O This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and Temp sensor. A resistor must be
connected from the SDA bus line to VDDSPD on the system planar to act as a pull up.
SCL Input This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
SA0-SA1 Input Address pins used to select the Serial Presence Detect and Temp sensor base address.
TEST I/O The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules
RESET Input RESET In Active Low This signal resets the DDR3 SDRAM

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Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
7. Function Block Diagram:
7.1 8GB, 1Gx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
V7
V8
V5
S1 RAS CAS WE CK1 CK1 CKE1 ODT1 A[0:N] /BA[0:N] S0 CK0 CK0 CKE0 ODT0
DQS3
DQS3
DM3
DQS
DQS
D11
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
ZQ
DQ[0:7]
DM
240Ω
± 1%
DQ[24:31]
D3
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
ZQ
240Ω
± 1%
Vtt
VDD
Vtt
Rank0
Rank1
NOTE :
1. DQ wiring may differ from that shown however ,DQ, DM, DQS and DQS relationships are maintained as shown
VSS
VDD
D0 - D15
VREFCA
VDDSPD SPD
CK0
VREFDQ D0 - D15
D0 - D15
D0 - D15, SPD
Vtt
CK1
CK0
CK1
RESET
Vtt
D8 - D15
D0 - D7
D0 - D7
D8 - D15
D0 - D7
V6
V2
V3
D6D12D3D9
Vtt
Address and Controllines
DQS
DQS
DQ[0:7]
DM
DQS1
DQS1
DM1
DQS
DQS
D1
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
ZQ
DQ[0:7]
DM
240Ω
± 1%
DQ[8:15]
D9
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
ZQ
240Ω
± 1%
DQS
DQS
DQ[0:7]
DM
DQS0
DQS0
DM0
DQS
DQS
D0
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
ZQ
DQ[0:7]
DM
240Ω
± 1%
DQ[0:7]
D8
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
ZQ
240Ω
± 1%
DQS
DQS
DQ[0:7]
DM
DQS2
DQS2
DM2
DQS
DQS
D2
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
ZQ
DQ[0:7]
DM
240Ω
± 1%
DQ[16:23]
D10
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
ZQ
240Ω
± 1%
DQS
DQS
DQ[0:7]
DM
DQS
DQS
D4
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
ZQ
DQ[0:7]
DM
240Ω
± 1%
D12
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
ZQ
240Ω
± 1%
DQS
DQS
DQ[0:7]
DM
DQS
DQS
D14
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
ZQ
DQ[0:7]
DM
240Ω
± 1%
D6
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
ZQ
240Ω
± 1%
DQS
DQS
DQ[0:7]
DM
DQS
DQS
D15
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
ZQ
DQ[0:7]
DM
240Ω
± 1%
D7
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
ZQ
240Ω
± 1%
DQS
DQS
DQ[0:7]
DM
DQS
DQS
D13
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
ZQ
DQ[0:7]
DM
240Ω
± 1%
D5
CS RAS CAS WE CK CK CKE ODT A[N:0]/BA[N:0]
ZQ
240Ω
± 1%
DQS
DQS
DQ[0:7]
DM
DQS4
DQS4
DM4
DQ[32:39]
DQS6
DQS6
DM6
DQ[48:55]
DQS7
DQS7
DM7
DQ[56:63]
DQS5
DQS5
DM5
DQ[40:47]
VDD
D7D5D10D8
V1
V4
V9
V7
V6
V9 V8
V4
V3
D15D13D2D0
D14D4D11D1
V1
V2
V5
V1
Vtt
A0
A1
A2
SA0
SA1
SCL
SDA
WP
SCL
(SPD)

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Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
8. Absolute Maximum Ratings
8.1 Absolute Maximum DC Ratings
NOTE :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be
equal to or less than 300mV.
8.2 DRAM Component Operating Temperature Range
NOTE :
1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document
JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main-
tained between 0-85°C under all operating conditions
3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the
following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. It is also possible to specify a component with 1X refresh (tREFI
to 7.8us) in the Extended Temperature Range.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature
Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.
9. AC & DC Operating Conditions
9.1 Recommended DC Operating Conditions (SSTL-15)
NOTE:
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
Symbol Parameter Rating Units NOTE
VDD Voltage on VDD pin relative to VSS -0.4 V ~ 1.975 V V 1,3
VDDQ Voltage on VDDQ pin relative to VSS -0.4 V ~ 1.975 V V 1,3
VIN, VOUT Voltage on any pin relative to VSS -0.4 V ~ 1.975 V V 1
TSTG Storage Temperature -55 to +100 °C 1, 2
Symbol Parameter rating Unit NOTE
TOPER Operating Temperature Range 0 to 95 °C 1, 2, 3
Symbol Parameter Rating Units NOTE
Min. Typ. Max.
VDD Supply Voltage 1.425 1.5 1.575 V 1,2
VDDQ Supply Voltage for Output 1.425 1.5 1.575 V 1,2

- 10 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
10. AC & DC Input Measurement Levels
10.1 AC & DC Logic Input Levels for Single-ended Signals
[ Table 1 ] Single-ended AC & DC input levels for Command and Address
NOTE :
1. For input only pins except RESET, VREF = VREFCA(DC)
2. See ’Overshoot/Undershoot Specification’ on page 18.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175) and VIH.CA(AC150); VIH.CA(AC175) value is used when VREF + 175mV is referenced and VIH.CA(AC150) value is
used when VREF + 150mV is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175) and VIL.CA(AC150); VIL.CA(AC175) value is used when VREF - 175mV is referenced and VIL.CA(AC150) value is used
when VREF - 150mV is referenced.
[ Table 2 ] Single-ended AC & DC input levels for DQ and DM
NOTE :
1. For input only pins except RESET, VREF = VREFDQ(DC)
2. See ’Overshoot/Undershoot Specification’ on page 18.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150) ; VIH.DQ(AC175) value is used when VREF + 175mV is referenced, VIH.DQ(AC150) value is used
when VREF + 150mV is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150) ; VIL.DQ(AC175) value is used when VREF - 175mV is referenced, VIL.DQ(AC150) value is used when
VREF - 150mV is referenced.
Symbol Parameter DDR3-800/1066/1333/1600 Unit NOTE
Min. Max.
VIH.CA(DC100) DC input logic high VREF + 100 VDD mV 1,5
VIL.CA(DC100) DC input logic low VSS VREF - 100 mV 1,6
VIH.CA(AC175) AC input logic high VREF + 175 - mV 1,2,7
VIL.CA(AC175) AC input logic low - VREF - 175 mV 1,2,8
VIH.CA(AC150) AC input logic high VREF+150 - mV 1,2,7
VIL.CA(AC150) AC input logic low - VREF-150 mV 1,2,8
VREFCA(DC) Reference Voltage for ADD,
CMD inputs 0.49*VDD 0.51*VDD V3,4
Symbol Parameter DDR3-800/1066 DDR3-1333/1600 Unit NOTE
Min. Max. Min. Max.
VIH.DQ(DC100) DC input logic high VREF + 100 VDD VREF + 100 VDD mV 1,5
VIL.DQ(DC100) DC input logic low VSS VREF - 100 VSS VREF - 100 mV 1,6
VIH.DQ(AC175) AC input logic high VREF + 175 - - - mV 1,2,7
VIL.DQ(AC175) AC input logic low - VREF - 175 --mV1,2,8
VIH.DQ(AC150) AC input logic high VREF + 150 NOTE 2 VREF + 150 NOTE 2 mV 1,2,7
VIL.DQ(AC150) AC input logic low NOTE 2 VREF - 150 NOTE 2 VREF - 150 mV 1,2,8
VREFDQ(DC) Reference Voltage for DQ,
DM inputs 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD V3,4