Samsung KS57C2308 User manual

KS57C2308/P2308/C2316/P2316 PRODUCT OVERVIEW
1-1
1PRODUCT OVERVIEW
OVERVIEW
The KS57C2308/C2316 single-chip CMOS microcontroller has been designed for high performance using
Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
With features such as LCD direct drive capability, 8-bit timer/counter, and serial I/O, the KS57C2308/C2316 offer
an excellent design solution for a wide variety of applications that require LCD functions.
Up to 40 pins of the 80-pin QFP package can be dedicated to I/O. Six vectored interrupts provide fast response
to internal and external events. In addition, the KS57C2308/C2316's advanced CMOS technology provides for
low power consumption and a wide operating voltage range.
OTP
The KS57C2308/C2316 microcontroller is also available in OTP (One Time Programmable) version,
KS57P2308/P2316. KS57P2308/P2316 microcontroller has an on-chip 8/16-Kbyte one-time-programmable
EPROM instead of masked ROM. The KS57P2308/P2316 is comparable to KS57C2308/C2316, both in function
and in pin configuration.

PRODUCT OVERVIEW KS57C2308/P2308/C2316/P2316
1-2
FEATURES
Memory
–512 ×4-bit RAM
–8 K ×8-bit ROM (KS57C2308/P2308)
–16 K ×8-bit ROM (KS57C2316/P2316)
I/O Pins
–Input only: 8 pins
–I/O: 24 pins
–Output: 8 pins sharing with segment driver
outputs
LCD Controller/Driver
–Maximum 16-digit LCD direct drive capability
–32 segment, 4 common pins
–Display modes: Static, 1/2 duty (1/2 bias),
1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)
8-Bit Basic Timer
–Programmable interval timer
–Watchdog timer
8-Bit Timer/Counter 0
–Programmable 8-bit timer
–External event counter
–Arbitrary clock frequency output
–Serial I/O interface clock generator
Watch Timer
–Real-time and interval time measurement
–Four frequency outputs to BUZ pin
–Clock source generation for LCD
8-Bit Serial I/O Interface
–8-bit transmit/receive mode
–8-bit receive only mode
–LSB-first or MSB-first transmission selectable
–Internal or external clock source
Bit Sequential Carrier
–Support 16-bit serial data transfer in arbitrary
format
Interrupts
–Three internal vectored interrupts
–Three external vectored interrupts
–Two quasi-interrupts
Memory-Mapped I/O Structure
–Data memory bank 15
Two Power-Down Modes
–Idle mode (only CPU clock stops)
–Stop mode (main or sub system oscillation stops)
Oscillation Sources
–Crystal, ceramic, or RC for main system clock
–Crystal or external oscillator for subsystem clock
–Main system clock frequency: 4.19 MHz (typical)
–Subsystem clock frequency: 32.768 kHz
–CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
–0.95, 1.91, 15.3 µs at 4.19 MHz (main)
–122 µs at 32.768 kHz (subsystem)
Operating Temperature
–– 40 °Cto 85 °C
Operating Voltage Range
–1.8 Vto 5.5 V
Package Type
– 80-pin QFP

KS57C2308/P2308/C2316/P2316 PRODUCT OVERVIEW
1-3
BLOCK DIAGRAM
Interrupt
Control
Block
Instruction
Register
Program
Counter
Program
Status Word
Stack
Pointer
Arithmetic and Logic Unit
Instruction Decoder
Clock
RESET XIN
XTIN
Internal
Interrupts
INT0, INT1,INT2
P3.0/LCDCK
P3.1/LCDSY
P3.2
P3.3
I/O Port 3
512 x 4-Bit
Data
Memory
8/16-Kbyte
Program
Memory
LCD Drive/
Controller
BIAS
VLC0-VLC2
LCDCK/P3.0
LCDSY/P3.1
COM0-COM3
SEG0-SEG23
P8.0-P8.7/
SEG24-SEG31
P2.3/BUZ
XOUT
XTOUT
P6.0-P6.3/
KS0-KS3 I/O Port 6
P7.0-P7.3/
KS4-KS7 I/O Port 7
P4.0-P4.3 I/O Port 3
P5.0-P5.3 I/O Port 4
8-Bit Timer/
Counter 0
P1.3/TCL0
P2.0/TCLO0
P8.0-P8.7/
SEG24-SEG31 I/O Port 8
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/TCL0
Input Port 1
P2.0/TCLO0
P2.1
P2.2/CLO
P2.3/BUZ
I/O Port 2
Basic
Timer
4-Bit
Accumulator
FLAGS
P0.0/INT4
P0.1/SCK
P0.2/SO
P0.3/SI
I/O Port 0
Serial I/O
Port
P0.2
/SO P0.3 /SI
P0.1
/SCK
Watch-Dog
Timer Watch Timer
Figure 1-1.KS57C2308/C2316 Simplified Block Diagram

PRODUCT OVERVIEW KS57C2308/P2308/C2316/P2316
1-4
PIN ASSIGNMENTS
SEG19
SEG20
SEG21
SEG22
SEG23
P8.0/SEG24
P8.1/SEG25
P8.2/SEG26
P8.3/SEG27
P8.4/SEG28
P8.5/SEG29
P8.6/SEG30
P8.7/SEG31
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
KS57C2308
KS57C2316
(TOP VIEW)
SEG2
SEG1
SEG0
COM0
COM1
COM2
COM3
BIAS
VLC0
VLC1
VLC2
VDD
VSS
XOUT
XIN
TEST
XTIN
XTOUT
RESET
P0.0/INT4
P0.1/SCK
P0.2/SO
P0.3/SI
P1.0/INT0
P1.1/INT1 P1.2/INT2
P1.3/TCL0
P2.0/TCLO0
P2.1
P2.2/CLO
P2.3/BUZ
P3.0/LCDCK
P3.1/SCDSY
P3.2 P3.3 P4.0 P4.1 P4.2 P4.3 P5.0
SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18
Figure 1-2.KS57C2308/C2316 80-QFP Pin Assignment Diagram

KS57C2308/P2308/C2316/P2316 PRODUCT OVERVIEW
1-5
PIN DESCRIPTIONS
Table 1-1. KS57C2308/C2316 Pin Descriptions
Pin Name Pin
Type Description Number Share Pin Reset Value Circuit Type
P0.0
P0.1
P0.2
P0.3
I
I/O
I/O
I
4-bit input port.
1-bit and 4-bit read and test are possible.
4-bit pull-up resistors are software assignable.
20
21
22
23
INT4
SCK
SO
SI
Input A-1
D *
D *
A-1
P1.0
P1.1
P1.2
P1.3
I4-bit input port.
1-bit and 4-bit read and test are possible.
4-bit pull-up resistors are software assignable.
24
25
26
27
INT0
INT1
INT2
TCL0
Input A-1
P2.0
P2.1
P2.2
P2.3
I/O 4-bit I/O port.
1-bit and 4-bit read/write and test are possible.
4-bit pull-up resistors are software assignable.
28
29
30
31
TCLO0
–
CLO
BUZ
Input D
P3.0
P3.1
P3.2
P3.3
I/O 4-bit I/O port.
1-bit and 4-bit read/write and test are possible.
Each individual pin can be specified as input
or output. 4-bit pull-up resistors are software
assignable.
32
33
34
35
LCDCK
LCDSY Input D
P4.0–
P4.3
P5.0–
P5.3
I/O 4-bit I/O ports. N-channel open-drain output up
to 5 V. 1-, 4-, and 8-bit read/write and test are
possible. Ports 4 and 5 can be paired to
support 8-bit data transfer. 4-bit pull-up
resistors are software assignable.
36–43 – Input E
P6.0–
P6.3
P7.0–
P7.3
I/O 4-bit I/O ports. Port 6 pins are individually
software configurable as input or output. 1-bit
and 4-bit read/write and test are possible. 4-bit
pull-up resistors are software assignable. Ports
6 and 7 can be paired to enable 8-bit data
transfer.
44–51 KS0–KS3
KS4–KS7 Input D *
P8.0–
P8.7 OOutput port for 1-bit data (for use as CMOS driver only) 59–52 SEG24– SEG31 Output H-16
SEG0–
SEG23 OLCD segment signal output 3–1, 80–60 –Output H-15
SEG24–
SEG31 OLCD segment signal output 59–52 P8.0–P8.7 Output H-16
COM0–
COM3 OLCD common signal output 4–7 – Output H-15
VLC0–VLC2 –LCD power supply. Voltage dividing resistors
are assignable by mask option 9–11 SCLK SDAT – –
BIAS –LCD power control 8 – – –
LCDCK I/O LCD clock output for display expansion 32 P3.0 Input D

PRODUCT OVERVIEW KS57C2308/P2308/C2316/P2316
1-6
Table 1-1. KS57C2308/C2316 Pin Descriptions (Continued)
Pin Name Pin
Type Description Number Share Pin Reset Value Circuit Type
LCDSY I/O LCD synchronization clock output for LCD
display expansion 33 P3.1 Input D
TCL0 I/O External clock input for timer/counter 0 27 P1.3 Input A-1
TCLO0 I/O Timer/counter 0 clock output 28 P2.0 Input D
SI ISerial interface data input 23 P0.3 Input A-1
SO I/O Serial interface data output 22 P0.2 Input D *
SCK I/O Serial I/O interface clock signal 21 P0.1 Input D *
INT0
INT1 IExternal interrupts. The triggering edge for INT0 and INT1 is selectable. Only INT0 is
synchronized with the system clock.
24
25 P1.0 P1.1 Input A-1
INT2 IQuasi-interrupt with detection of rising edge
signals. 26 P1.2 Input A-1
INT4 IExternal interrupt input with detection of rising
or falling edge 20 P0.0 Input A-1
KS0–KS7 I/O Quasi-interrupt inputs with falling edge
detection. 44–51 P6.0–P7.3 Input D *
CLO I/O CPU clock output 30 P2.2 Input D
BUZ I/O 2, 4, 8 or 16 kHz frequency output for buzzer
sound with 4.19 MHz main system clock or
32.768 kHz subsystem clock.
31 P2.3 Input D
XIN,
XOUT –Crystal, ceramic or RC oscillator pins for main
system clock. (For external clock input, use
XIN and input XIN‘s reverse phase to XOUT)
15,14 – – –
XTIN,
XTOUT –Crystal oscillator pins for subsystem clock.
(For external clock input, use XTIN and input
XTIN's reverse phase to XTOUT)
17,18 – – –
VDD –Main power supply 12 – – –
VSS –Ground 13 – – –
RESET –Reset signal 19 – Input B
TEST –Test signal input (must be connected to VSS)16 – – –
NOTES:
1. Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
2. D *Type has a schmitt trigger circuit at input.

KS57C2308/P2308/C2316/P2316 PRODUCT OVERVIEW
1-7
PIN CIRCUIT DIAGRAMS
VDD
P-CHANNEL
IN
N-CHNNEL
Figure 1-3.Pin Circuit Type A
SCHMITT TRIGGER
VDD
IN
P-CHANNEL
PULL-UP
RESISTOR
RESISTOR
ENABLE
Figure 1-4.Pin Circuit Type A-1 (P1, P0.0, P0.3)
VDD
P-CHANNEL
DATA
OUTPUT
DISABLE
N-CHANNEL
OUT
Figure 1-5.Pin Circuit Type C
P-CHANNEL
PULL-UP
RESISTOR
RESISTOR
ENABLE
DATA
OUTPUT
DISABLE
CIRCUIT TYPE A
I/O
VDD
CIRCUIT
TYPE C
Figure 1-6.Pin Circuit Type D
(P0.1, P0.2, P2, P3, P6, P7)

PRODUCT OVERVIEW KS57C2308/P2308/C2316/P2316
1-8
DATA
OUTPUT
ENABLE
VDD
P-CH
RESISTOR
ENABLE
N-CH
PULL-UP
RESISTOR
I/O
CIRCUIT TYPE A
VDD
PNE
Figure 1-7.Pin Circuit Type E (P4, P5)
VLC0
VLC1
LCD SEGMENT/
COMMON DATA
VLC2
OUT
Figure 1-8.Pin Circuit Type H-15 (SEG/COM)
VLC0
VLC1
LCD SEGMENT/
& PORT 8 DATA
VLC2
VDD
OUT
Figure 1-9.Pin Circuit Type H-16 (P8)
IN
SCHMITT TRIGGER
VDD
Figure 1-10.Pin Circuit Type B (RESET)

KS57C2308/P2308/C2316/P2316 ADDRESS SPACES
2-1
2ADDRESS SPACES
PROGRAM MEMORY (ROM)
OVERVIEW
ROM maps for KS57C2 308/C2316 devices are mask programmable at the factory. KS57C2308 has 8K ×8-bit
program memory and KS57C2316 has 16K ×8-bit program memory, aside from the differences in the ROM size
the two products are identical in other features. In its standard configuration, the device's 8,192 ×8-bit (16,384 ×
8-bit)program memory has four areas that are directly addressable by the program counter (PC):
—12-byte area for vector addresses
—96-byte instruction reference area
—20-byte general-purpose area
—8064-byte general-purpose area (KS57C2308)
—16256-byte general-purpose area (KS57C2316)
General-Purpose Program Memory
Two program memory areas are allocated for general-purpose use: One area is 20 bytes in size and the other is
8,064-bytes (16,256-bytes).
Vector Addresses
A 12-byte vector address area is used to store the vector addresses required to execute system resets and
interrupts. Start addresses for interrupt service routines are stored in this area, along with the values of the
enable memory bank (EMB) and enable register bank (ERB) flags that are used to set their initial value for the
corresponding service routines. The 16-byte area can be used alternately as general-purpose ROM.
REF Instructions
Locations 0020H–007FH are used as a reference area (look-up table) for 1-byte REF instructions. The REF
instruction reduces the byte size of instruction operands. REF can reference one 2-byte instruction, two 1-byte
instructions, and one 3-byte instruction which are stored in the look-up table. Unused look-up table addresses can
be used as general-purpose ROM.
Table 2-1. Program Memory Address Ranges
ROM Area Function Address Ranges Area Size (in Bytes)
Vector address area 0000H–000BH12
General-purpose program memory 000CH–001FH 20
REF instruction look-up table area 0020H–007FH 96
General-purpose program memory 0080H–1FFFH (KS57C2308)
0080H–3FFFH (KS57C2316) 8064 (KS57C2308) 16256 (KS57C2316)

ADDRESS SPACES KS57C2308/P2308/C2316/P2316
2-2
GENERAL-PURPOSE MEMORY AREAS
The 20-byte area at ROM locations 000CH–001FH and the 8,064-byte (16,256-byte)area at ROM locations
0080H–1FFFH (0080H–3FFFH) are used as general-purpose program memory. Unused locations in the vector
address area and REF instruction look-up table areas can be used as general-purpose program memory.
However, care must be taken not to overwrite live data when writing programs that use special-purpose areas of
the ROM.
VECTOR ADDRESS AREA
The 12-byte vector address area of the ROM is used to store the vector addresses for executing system resets
and interrupts. The starting addresses of interrupt service routines are stored in this area, along with the enable
memory bank (EMB) and enable register bank (ERB) flag values that are needed to initialize the service routines.
12-byte vector addresses are organized as follows:
NOTE: PC13 is used for KS57C2316/P2316 microcontroller.
To set up the vector address area for specific programs, use the instruction VENTn. The programming tips on the
next page explain how to do this.
VECTOR ADDRESS AREA
(12 Bytes)
GENERAL-PURPOSE AREA
(20 Bytes)
INSTRUCTION
REFERENCE
AREA
GENERAL-PURPOSE AREA
(8,064 Bytes/
16,256 Bytes)
1FFFH
3FFFH
0080H
007FH
0020H
001FH
000CH
000BH
0000H
Figure 2-1. ROM Address Structure
76543210
RESET
INTB/INT4
INT0
INT1
INTT0
0000H
0002H
0004H
0006H
0008H
000AH
INTS
Figure 2-2.Vector Address Structure
EMB ERB PC13 (note) PC12 PC11 PC10 PC9 PC8
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

KS57C2308/P2308/C2316/P2316 ADDRESS SPACES
2-3
++ PROGRAMMING TIP — Defining Vectored Interrupts
The following examples show you several ways you can define the vectored interrupt and instruction reference
areas in program memory:
1. When all vector interrupts are used:
ORG 0000H
VENT0 1,0,RESET ;EMB ←1, ERB ←0; Jump to RESET address by RESET
VENT1 0,0,INTB ;EMB ←0, ERB ←0; Jump to INTB address by INTB
VENT2 0,0,INT0 ;EMB ←0, ERB ←0; Jump to INT0 address by INT0
VENT3 0,0,INT1 ;EMB ←0, ERB ←0; Jump to INT1 address by INT1
VENT4 0,0,INTS ;EMB ←0, ERB ←0; Jump to INTS address by INTS
VENT5 0,0,INTT0 ;EMB ←0, ERB ←0; Jump to INTT0 address by INTT0
2. When a specific vectored interrupt such as INT0, and INTT0 is not used, the unused vector interrupt
locations must be skipped with the assembly instruction ORG so that jumps will address the correct locations:
ORG 0000H
VENT0 1,0,RESET ;EMB ←1, ERB ←0; Jump to RESET address by RESET
VENT1 0,0,INTB ;EMB ←0, ERB ←0; Jump to INTB address by INTB
ORG 0006H ;INT0 interrupt not used
VENT3 0,0,INT1 ;EMB ←0, ERB ←0; Jump to INT1 address by INT1
VENT4 0,0,INTS ;EMB ←0, ERB ←0; Jump to INTS address by INTS
ORG 000CH ;INTT0 interrupt not used
ORG 0010H
3. If an INT0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not
written by a ORG instruction in Example 2, a CPU malfunction will occur:
ORG 0000H
VENT0 1,0,RESET ;EMB ←1, ERB ←0; Jump to RESET address by RESET
VENT1 0,0,INTB ;EMB ←0, ERB ←0; Jump to INTB address by INTB
VENT3 0,0,INT1 ;EMB ←0, ERB ←0; Jump to INT1address by INT0
VENT4 0,0,INTS ;EMB ←0, ERB ←0; Jump to INTSaddress by INT1
VENT5 0,0,INTT0 ;EMB ←0, ERB ←0; Jump to INTT0 address by INTS
ORG 0010H
General-purpose ROM area
In this example, when an INTS interrupt is generated, the corresponding vector area is not VENT4 INTS, but
VENT5 INTT0. This causes an INTS interrupt to jump incorrectly to the INTT0 address and causes a CPU
malfunction to occur.

ADDRESS SPACES KS57C2308/P2308/C2316/P2316
2-4
INSTRUCTION REFERENCE AREA
Using 1-byte REF instructions, you can easily reference instructions with larger byte sizes that are stored in
addresses 0020H–007FH of program memory. This 96-byte area is called the REF instruction reference area, or
look-up table. Locations in the REF look-up table may contain two 1-byte instructions, one 2-byte instruction, or
one 3-byte instruction such as a JP (jump) or CALL. The starting address of the instruction you are referencing
must always be an even number. To reference a JP or CALL instruction, it must be written to the reference area
in a two-byte format: for JP, this format is TJP; for CALL, it is TCALL.
By using REF instructions you can execute instructions larger than one byte, In summary, there are three ways
you can use the REF instruction:
—Using the 1-byte REF instruction to execute one 2-byte or two 1-byte instructions,
—Branching to any location by referencing a branch instruction stored in the look-up table,
—Calling subroutines at any location by referencing a call instruction stored in the look-up table.
++ PROGRAMMING TIP — Using the REF Look-Up Table
Here is one example of how to use the REF instruction look-up table:
ORG 0020H
JMAIN TJP MAIN ;0, MAIN
KEYCK BTSF KEYFG ;1, KEYFG CHECK
WATCH TCALL CLOCK ;2, CALL CLOCK
INCHL LD @HL,A ;3, (HL) ←A
INCS HL
•
•
•
ABC LD EA,#00H ;47, EA ←#00H
ORG 0080H
MAIN NOP
NOP
•
•
•
REF KEYCK ;BTSF KEYFG (1-byte instruction)
REF JMAIN ;KEYFG =1, jump to MAIN (1-byte instruction)
REF WATCH ;KEYFG =0, CALL CLOCK (1-byte instruction)
REF INCHL ;LD @HL,A
;INCS HL
REF ABC ;LD EA,#00H (1-byte instruction)
•
•
•

KS57C2308/P2308/C2316/P2316 ADDRESS SPACES
2-5
DATA MEMORY (RAM)
OVERVIEW
In its standard configuration, the 512 x 4-bit data memory has four areas:
—32 ×4-bit working register area in bank 0
—224 ×4-bit general-purpose area in bank 0 which is also used as the stack area
—224 ×4-bit general-purpose area in bank 1
—32 ×4-bit area for LCD data in bank 1
—128 ×4-bit area in bank 15 for memory-mapped I/O addresses
To make it easier to reference, the data memory area has three memory banks — bank 0, bank 1 and bank 15.
The select memory bank instruction (SMB) is used to select the bank you want to select as working data memory.
Data stored in RAM locations are 1-, 4-, and 8-bit addressable. One exception is the LCD data register area,
which is 1-bit and 4-bit addressable only.
Initialization values for the data memory area are not defined by hardware and must therefore be initialized by
program software following power RESET. However, when RESET signal is generated in power-down mode, the
most of data memory contents are held.
GENERAL-PURPOSE
REGISTERS AND
STACK AREA
(224 x 4 Bits)
WORKING REGISTERS
(32 x 4 Bits)
LCD DATA REGISTERS
(32 x 4 Bits)
MEMORY-MAPPED I/O
AEERESS REGISTERS
(128 x 4 Bits)
000H
01FH
020H
0FFH
100H
FFFH
1FFH
F80H ~~
BANK 0
BANK 1
BANK 15
GENERAL-PURPOSE
REGISTERS
(224 x 4 Bits)
1DFH
1E0H
Figure 2-3.Data Memory (RAM) Map

ADDRESS SPACES KS57C2308/P2308/C2316/P2316
2-6
Memory Banks 0, 1, and 15
Bank 0 (000H–0FFH) The lowest 32 nibbles of bank 0 (000H–01FH) are used as working registers;
the next 224 nibbles (020H–0FFH) can be used both as stack area and as
general-purpose data memory. Use the stack area for implementing subroutine
calls and returns, and for interrupt processing.
Bank 1 (100H–1FFH) The lowest 224 nibbles of bank1 (100H–1DFH) are for general–purpose use;
Use the remaining of 32 nibbles (1E0H–1FFH) as display registers or as
general purpose memory.
Bank 15 (F80H–FFFH) The microcontroller uses bank 15 for memory-mapped peripheral I/O. Fixed
RAM locations for each peripheral hardware address are mapped into this
area.
Data Memory Addressing Modes
The enable memory bank (EMB) flag controls the addressing mode for data memory banks 0, 1 or 15. When the
EMB flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or
indirect addressing is used. With direct addressing, you can access locations 000H–07FH of bank 0 and bank 15.
With indirect addressing, only bank 0 (000H–0FFH) can be accessed. When the EMB flag is set to logic one, all
three data memory banks can be accessed according to the current SMB value.
For 8-bit addressing, two 4-bit registers are addressed as a register pair. Also, when using 8-bit instructions to
address RAM locations, remember to use the even-numbered register address as the instruction operand.
Working Registers
The RAM working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2,
and 3). Each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable.
Register A is used as a 4-bit accumulator and register pair EA as an 8-bit extended accumulator. The carry flag
bit can also be used as a 1-bit accumulator. Register pairs WX, WL, and HL are used as address pointers for
indirect addressing. To limit the possibility of data corruption due to incorrect register addressing, it is advisable
to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines.
LCD Data Register Area
Bit values for LCD segment data are stored in data memory bank 1. Register locations in this area that are not
used to store LCD data can be assigned to general-purpose use.

KS57C2308/P2308/C2316/P2316 ADDRESS SPACES
2-7
Table 2-2. Data Memory Organization and Addressing
Addresses Register Areas Bank EMB Value SMB Value
000H–01FH Working registers 00, 1 0
020H–0FFH Stack and general-purpose registers
100H–1DFH General-purpose registers 1 1 1
1E0H–1FFH LCD Data registers
F80H–FFFH I/O-mapped hardware registers 15 0, 1 15
++ PROGRAMMING TIP — Clearing Data Memory Banks 0 and 1
Clear banks 0 and 1 of the data memory area:
RAMCLR SMB 1;RAM (100H–1FFH) clear
LD HL,#00H
LD A,#0H
RMCL1 LD @HL,A
INCS HL
JR RMCL1
SMB 0;RAM (010H–0FFH) clear
LD HL,#10H
RMCL0 LD @HL,A
INCS HL
JR RMCL0

ADDRESS SPACES KS57C2308/P2308/C2316/P2316
2-8
WORKING REGISTERS
Working registers, mapped to RAM address 000H-01FH in data memory bank 0, are used to temporarily store
intermediate results during program execution, as well as pointer values used for indirect addressing. Unused
registers may be used as general-purpose memory. Working register data can be manipulated as 1-bit units, 4-bit
units or, using paired registers, as 8-bit units.
000H
001H
002H
003H
004H
005H
006H
007H
00FH
010H
017H
018H
01FH
008H
A
E
L
H
X
W
Z
Y
A ...Y REGISTER
BANK 1
REGISTER
BANK 2
REGISTER
BANK 3
A ...Y
A ...Y
WORKING
REGISTER
BANK 0
DATA
MEMORY
BANK 0
Figure 2-4.Working Register Map

KS57C2308/P2308/C2316/P2316 ADDRESS SPACES
2-9
Working Register Banks
For addressing purposes, the working register area is divided into four register banks — bank 0, bank 1, bank 2,
and bank 3. Any one of these banks can be selected as the working register bank by the register bank selection
instruction (SRB n) and by setting the status of the register bank enable flag (ERB).
Generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service
routines. Following this convention helps to prevent possible data corruption during program execution due to
contention in register bank addressing.
Table 2-3. Working Register Organization and Addressing
ERB Setting SRB Settings Selected Register Bank
3210
000––Always set to bank 0
0 0 Bank 0
10001 Bank 1
1 0 Bank 2
1 1 Bank 3
Paired Working Registers
Each of the register banks is subdivided into eight 4-bit registers. These registers, named Y, Z, W, X, H, L, E and
A, can either be manipulated individually using 4-bit instructions, or together as register pairs for 8-bit data
manipulation.
The names of the 8-bit register pairs in each register bank are EA, HL, WX, YZ and WL. Registers A, L, X and Z
always become the lower nibble when registers are addressed as 8-bit pairs. This makes a total of eight 4-bit
registers or four 8-bit double registers in each of the four working register banks.
YZ
WX
HL
E A
(MSB) (LSB) (MSB) (LSB)
Figure 2-5. Register Pair Configuration

ADDRESS SPACES KS57C2308/P2308/C2316/P2316
2-10
Special-Purpose Working Registers
Register A is used as a 4-bit accumulator and double register EA as an 8-bit accumulator. The carry flag can also
be used as a 1-bit accumulator.
8-bit double registers WX, WL and HL are used as data pointers for indirect addressing. When the HL register
serves as a data pointer, the instructions LDI, LDD, XCHI, and XCHD can make very efficient use of working
registers as program loop counters by letting you transfer a value to the L register and increment or decrement it
using a single instruction.
C
A
EA
1-BIT
ACCUMULATOR
4-BIT
ACCUMULATOR
8-BIT
ACCUMULATOR
Figure 2-6.1-Bit, 4-Bit, and 8-Bit Accumulator
Recommendation for Multiple Interrupt Processing
If more than four interrupts are being processed at one time, you can avoid possible loss of working register data
by using the PUSH RR instruction to save register contents to the stack before the service routines are executed
in the same register bank. When the routines have executed successfully, you can restore the register contents
from the stack to working memory using the POP instruction.

KS57C2308/P2308/C2316/P2316 ADDRESS SPACES
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++ PROGRAMMING TIP — Selecting the Working Register Area
The following examples show the correct programming method for selecting working register area:
1. When ERB ="0":
VENT2 1,0,INT0 ;EMB ←1, ERB ←0, Jump to INT0 address
INT0 PUSH SB ;PUSH current SMB, SRB
SRB 2;Instruction does not execute because ERB ="0"
PUSH HL ;PUSH HL register contents to stack
PUSH WX ;PUSH WX register contents to stack
PUSH YZ ;PUSH YZ register contents to stack
PUSH EA ;PUSH EA register contents to stack
SMB 0
LD EA,#00H
LD 80H,EA
LD HL,#40H
INCS HL
LD WX,EA
LD YZ,EA
POP EA ;POP EA register contents from stack
POP YZ ;POP YZ register contents from stack
POP WX ;POP WX register contents from stack
POP HL ;POP HL register contents from stack
POP SB ;POP current SMB, SRB
IRET
The POP instructions execute alternately with the PUSH instructions. If an SMB n instruction is used in an
interrupt service routine, a PUSH and POP SB instruction must be used to store and restore the current SMB and
SRB values, as shown in Example 2 below.
2. When ERB ="1":
VENT2 1,1,INT0 ;EMB ←1, ERB ←1, Jump to INT0 address
INT0 PUSH SB ;Store current SMB, SRB
SRB 2;Select register bank 2 because of ERB ="1"
SMB 0
LD EA,#00H
LD 80H,EA
LD HL,#40H
INCS HL
LD WX,EA
LD YZ,EA
POP SB ;Restore SMB, SRB
IRET

ADDRESS SPACES KS57C2308/P2308/C2316/P2316
2-12
STACK OPERATIONS
STACK POINTER (SP)
The stack pointer (SP) is an 8-bit register that stores the address used to access the stack, an area of data
memory set aside for temporary storage of data and addresses. The SP can be read or written by 8-bit control
instructions. When addressing the SP, bit 0 must always remain cleared to logic zero.
F80H SP3 SP2 SP1 "0"
F81H SP7 SP6 SP5 SP4
There are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack
(pop). A push decrements the SP and a pop increments it so that the SP always points to the top address of the
last data to be written to the stack.
The program counter contents and program status word are stored in the stack area prior to the execution of a
CALL or a PUSH instruction, or during interrupt service routines. Stack operation is a LIFO (Last In-First Out)
type. The stack area is located in general-purpose data memory bank 0.
During an interrupt or a subroutine, the PC value and the PSW are saved to the stack area. When the routine has
completed, the stack pointer is referenced to restore the PC and PSW, and the next instruction is executed.
The SP can address stack registers in bank 0 (addresses 000H-0FFH) regardless of the current value of the
enable memory bank (EMB) flag and the select memory bank (SMB) flag. Although general-purpose register
areas can be used for stack operations, be careful to avoid data loss due to simultaneous use of the same
register(s).
Since the RESET value of the stack pointer is not defined in firmware, we recommend that you initialize the stack
pointer by program code to location 00H. This sets the first register of the stack area to 0FFH.
NOTE
A subroutine call occupies six nibbles in the stack; an interrupt requires six. When subroutine nesting or
interrupt routines are used continuously, the stack area should be set in accordance with the maximum
number of subroutine levels. To do this, estimate the number of nibbles that will be used for the
subroutines or interrupts and set the stack area correspondingly.
++ PROGRAMMING TIP — Initializing the Stack Pointer
To initialize the stack pointer (SP):
1. When EMB ="1":
SMB 15 ;Select memory bank 15
LD EA,#00H ;Bit 0 of SP is always cleared to "0"
LD SP,EA ;Stack area initial address (0FFH) ←(SP) – 1
2. When EMB ="0":
LD EA,#00H
LD SP,EA ;Memory addressing area (00H–7FH, F80H–FFFH)