Shugart SA 400 minifloppy User manual

SA400 W
minifloppyTM ~
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~®shUgart Associates

SA400 rt&J
minifloppyTM ~
Disl<ette Storage Drive ~D
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© Copyright 1977 Shugart Associates

PREFACE
This service manual contains all the information
required to service the SA 400 MiniFloppy drive
in
the field. The service manual is divided into 3
sections:
Section I Theory of Operations
Section 2 Maintenance Manual
Section 3 Illustrated Parts Catalog
Each section contains its own Table of Contents.
For information on the SA 400 drive specifica-
tions, interfacing, track formats, and applications
notes refer to Shugart Associates OEM manual
PIN 54102.

Section 1

Table c)f Contents
1.0 Theory
of Operations 1
1.1
General Operations 1
1.2
Head Positioning . 1
1.3 Diskette Spindle
Drive.
2
1.4 Head/Write
Head .2
1.5 Hecording Format 2
1.6
Bit Cell 3
1.7
Byte.
3
1.8 Tracks.
4
1.9 Track Format 4
1.10 Sector Recording Format 4
1.11
Soft Sector Recording Format. 4
2.0 Drive
Motor Control 6
3.0 Drive Selection 7
3.1
Head
Load. 7
3.2
Singlle Drive System. 7
3.3 Mu Itiple Drive System.
7
4.0 Index Detector 8
5.0 Track Zero Indication .9
6.0 Track Accessing 10
6.1
Stepper Motor.
10
6.2 Stepper Control 10
6.3 Step
Out.
10
6.4 Step In Mode 10
7.0 Read/Write Operations
13
8.0 Read/Write
Head .
16
9.0 Write Circuit Operation
17
10.0
Read Circuit Operation 18
11.0 Write Protect
19
12.0 Interface .20
12.1 J1/P1Connector .20
12.2 D.C. Power 20
12.3 I
nput/Output Lines.
20

List of Illustrations
1.
Functional Diagram. 2
2.
Data Pattern 2
3.
Bit Cell 3
4.
Byte.
3
5.
Data Bytes 3
6. Hard Sector Format 4
7.
Soft Sector Format .5
8.
Motor Control Functional Diagram.
6
9. Drive Select Functional
Diagram.
7
10. Index Detector Logic 8
11. Index Timing Diagram. 8
12. Track 00 Indication Diagram 9
13. Track 00
Timing Diagram 9
14. Step
Out Logic 10
15. Stepper Control Functional Diagram
11
16. Step Timing Diagram 12
17. Step In Logic
12
1B. Bit Cell 14
19.
Basic Read/Write Head
14
20. Recorded
Bit
14
21. Reading A
Bit .15
22. IF and 2F Recording Flux and
Pu Ise Relationship 15
2:L Read/Write
Head.
16
24. Write Circuit Functional Diagram
17
25.
Read Circuit Functional Diagram 18
2B.
Write Protect Functional Diagram 19
27. D.C. Power 20
28. SA400 Interface Connections .
21
29. Interface Signal Driver/Receiver
21

1.0 THEORY OF OPERATIONS
1.1 GENERAL OPERATIONS
The SA 400 Minifloppy Drive consists of read/
write and
control electronics, drive mechanism,
motor control, read/write head, track positioning
mechanism,
and the removable Diskette. These
components perform the following functions:
•
Interpret and generate control signals.
•Move read/write head
to the desired track.
•Read and write data
•Maintain correct diskette speed.
The relationship and interface signals for the inter-
nal functions
of the SA 400 are shown in Figure 1.
The Head Positioning Actuator Cam positions the
read/write head to the desired track on the Disk-
ette. The Head Load Actuator loads the Diskette
against
the read/write head and data may then be
recorded or read from
the Diskette.
The drive has
two (2) PCB's, one is for the drive
motor control and the other is the drive PCB. The
electronics packaged on the drive PCB contains:
1.
Index Detector Circuits
2.
Head Position Actuator Driver
3. Head Load Actuator Driver
4. Read/Write Amplifier and Transition
Detector
5.
Step Control Logic
6. Track Zero Sensing Circuits
7. Write
Protect
The drive motor control PCB contains the following
electronics:
1. Motor on & off circuitry
2.
Motor speed control
1.2 HEAD POSITIONING
An electrical stepping motor drives the Head Position
Actuator Cam which positions the read/write head.
The stepping
motor rotates the actuator cam clock-
wise or counter-clockwise. The using system incre-
ments the stepping
motor to the desired track. Each
step consists
of 2steps to the stepper motor for each
step pulse supplied
on the interface.

___ READ DATA
DRIVE SELECT
WRITE DATA
WRITE GATE
... WRITE PROTECT
DRIVE SELECT
STEP
DIRECTION SELECT. --..1
DRIVE SELECT (3 LINES)
..... TRACK 00
..... INDEX/SECTOR
_MOTOR ON __ . --..I
READ
LOGIC
WRITE
LOGIC
CONTROL
LOGIC
WRITE PROTECT (COM)
WRITE PR T C ~C
~"" _~::I~gROTECT
I ~ r---------------.
I ~~~
....... --+--j...:.:.R=..EA:.:::..D~HE~AD I ,.----_"....:~~:--_--.J
I
WRITE HEAD
ACTIVITY LIGHT
HEAD LOAD SOLENOID
TRACK 00 (COM)
TRACK 00 (N/OI
MOTOR ON
TACHOMETER
STEPPER </JA
STEPPER tPB
STEPPER <PC
STEPPER ¢O
INDEX/sECTOR LED
INDEX/SECTOR DETECTOR
FIGURE 1. FUNCTIONAL DIAGRAM
1.3 DISKETTE SPINDLE DRIVE
The Diskette D.C. drive motor rotates the spindle
at 300 rpm through abelt-drive system. 50 or 60
Hz operation is accommodated without any
changes. AClamping Hub moves in conjunc-
tion with the Hub frame that precisely clamps the
Di.skette to the spindle hub. The motor
is started
by making the interface signal
"motor on" true
and
is stopped by making this signal false.
1.1\ READIWRITE HEAD
The read/write head is aceramic head and is in
direct contact with the Diskette. The head sur·
face has been designed to obtain maximum signal
transfer to and from the magnetic surface
of the
Diskette with minimum Head/Diskette wear.
The SA
400 ceramic head is asingle element read/
write head with straddle erase elements to provide
erased areas between data tracks. Thus, normal
tolerance between media and drives will
not de-
grade the signal to noise ratio and insures Diskette
interchangeability.
The read/write head
is mounted on acarriage
which
is located on the Head Position Actuator
Cam and
is driven thm acam follower. The Disk-
2
ette is held in aplane perpendicular to the read/
write head
by one platen located on the base cast·
ing. The Diskette
is loaded against the head with
afelt load pad actuated by the head load solenoid.
1.5 RiECORDING FORMAT
The format of the data recorded on the Diskette is
totally afunction of the host system. Data is re-
corded on the Diskette using frequency modula·
tion
as t.he recording mode, i.e., each data bit re-
corded on the diskette has an associated clock bit
recorded with it, this is referred to as FM. Data
written
on and read back from the diskette takes
the form
as shown in Figure 2. The binary data
pattern shown represents a101. Two recording
frequencies are used.
IF which is 0 bit and 2F
which is a 1 bit. The IF frequency is 62.5 KHz
and
2F is 125.0 KHz.
I
DATA BITS
FIGURE 2. DATA PATTERN

1.6 BIT CELL
As shown in Figure 3, the clock bits and data bits
(if present) are interleaved. By definition, aBit
Cell
is the period between the leading edge of one
clock bit and the leading edge
of the next dock
bit. Abit cell time is 8/1 sec from clock to clock.
CLOCK BITS
_--L_
(
[)ATABr~
(If: PRESENT) ,
FIGURE 3. BIT CELL
1.7 BYTE
AByte, when referring to serial data (being written
onto or read from the disc drive), is defined as
eight (8) consecutive bit cells. The most significant
bit cell
is defined as bit cell 0and the least signifi-
cant
bit cell is defined as bit cell 7. When reference
is made to aspecific data bit (i.e., data bit 3), it is
with respect to the corresponding bit cell (bit cell 3).
During awrite operation,
bit cell 0 of each byte is
transferred to the disc drive first with bit cell 7be-
ing transferred last. Correspondingly, the most
significant
byte of data is transferred to the disc
first and the least significant
byte is transferred
last.
When data
is being read back from the drive, bit
cell 0
of each byte will be transferred first with
bit cell 7last.
As with reading, the most signifi-
cant byte will be transferred first from the drive
to the user. Figure 4illustrates the relationship
of the bits within abyte and Figure 5illustrates
the relationship
of the bytes for read and write
data.
~CELL8~~CELL;I:'TCELL: R:,TCELL: BlTCELL]
MSB I BIT CELL 1ILSB
BYTE--------------·~I
BINARY REPRESENTATION OF:
BIT CELL 0
DATA BITS
CLOCK BITS
HEXADECIMAL
REPRESENTATION
OF:
DATA BITS
CLOCK BITS
FIGURE 4. BYTE
b:ITiJ
YTE BYTE
LhLJ
01234567
,_-...lL....-_ ........ _......L __ .L-_-L_---' __ ........_........ _---JL.-._...L-_......I
1
BIT CELL 0OF BYTE 0 IS
FIRST DATA TO BE SENT
TO THE
DRIVE WHEN
WRITING AND FROM THE
DRIVE WHEN READING
FIGURE 5. DATA BYTES
3
1
BIT CELL 7OF BYTE 17 IS
LAST DATA TO BE SENT TO
THE
DRIVE WHEN WRITING
AND FROM THE DRIVE
WHEN READING

1.8 TRACKS
The SA 400 Minifloppy drive is capable of re-
cording up
to 35 tracks of data. The tracks are
numbered 0-34. Each track
is made available to
the read/write head
by accessing the head with
astepper motor and carriage assembly. Track
00
is the outer most track with track 34 being the
intermost track. Track accessing will be covered
in Section 3.
Basic Track Characteristics:
'1.10 HARD SECTOR RECORDING FORMAT
In this Format, the using system may record up to 10 or
]6 sectors (records) per track. Each track
is started
by aphysical index pulse and each sector
is started
by aphysical sector pulse. This type
of recording
is called hard sectoring. Figure 6shows some typ-
ical Sector Recording Formats. The using system
must do the sector separation. For additional in-
formation on sector separation and formatting re-
quirements. Refer to the SA
400 OEM Manual.
Tracks may be formatted in numerous ways and
is
dependent on the using system. The SA 400 can
use hard sector recording with
SAl05 and SAl07
media or soft-sectoring using SAl04 media.
No. bits/track
Bit per inch (inside)
Tracks per inch
Access time
1.9 TRACK FORMAT
25,000 bits
2,581 BPI
48 TPI
40 msec
'loll SOFT SECTOR RECORDING FORMAT
In this Format, the using system may record one
long record or several smaller records. Each track
is started by aphysical index pulse and then each
record is preceded
by aunique recorded identifier.
This type
of recording is called soft sectoring. Fig-
ure 7shows the soft sector format for
18 sectors
and 128 bytes. Refer to the SA
400 OEM Manual
for further formatting information.
HIEX BYTE
#OF BYTES
16 SECTORS
10 SECTORS
8SECTORS
5SECTORS
4SECTORS
2SECTORS
1SECTORS
SA 400 HARD SECTOR FORMAT
SECTOR SEPARATION DONE BY THE USING SYSTEM
FM RECOMMENDED FORMAT
PHY~CALSEC~R~'~~~~~~~~~~~ __ ~~ __ ~~~~~~~~~~~~~~
1-1I: .. --G-1-- ...... I .. .-I-D-... .. r----- OATAFIELD ------., .... 1 .. CRC ~M
IHEX HEX ~ CD HEX II
I00 FB FF
I16 1 2 tI
I128 48 I
I256 35 I
I256 115 I
I512
91 I
512 250
I1024 519 I
I2048 1058 I
UPDATE WRITE ~~~~~~~~~~~~~~.~~~.~~~~~~~~~~~~~~~
[2J -USER DATA
~J -GENERATED BY CRC GENERATOR (IBM OR EQUIV)
FIGURE 6. HARD SECTOR FORMAT
4

PHYSICAL INDEX .......
~ DATA FIELD
_>RECORD
18
GAP4
PRE-INDEX
103 BYTES
HEX "FF"
GAP 1
INDEX GAP
20
BYTES
ID
RECORD
" 1
GAP 2
10
GAP
10
BYTES
DATA FIELD
RECORD
" 1
GAP3
DATA GAP
18 BYTES
ID
RECORD
#2
GAP2
DATA FIELD
RECORD
#2
GAP3
ID
RECORD
#3
GAP 2
DATA FIELD
RECORD
#3
10
RECORD
18
GAP2
DATA FIELD
RECORD
18
GAP4 ~
/ /J ~,,~
--------------... ,.---.....,r-------------"""'T---~,...---""
GAP BYTES
HEX
"FF-
SYNC
BYTES
HEX
"00
ID
ADDRESS
MARK
TRACK
ADDRESS SECTOR
ADDRESS CRC CRC
BYTE BYTE
1 2
DATA OR
DELETED DATA
ADDRESS MARK
128 BYTES OF
USER DATA
CRC
BYTE 1CRC
BYTE 2
I... 16 BYTES-----+4 BYTES-.j
GAP BYTES
HEx' FF SYNC BYTES
HEX "00
WRITE GATE
OFF
HEX
"FF-
GAP BYTES
HEX -'FF"
SYNC BYTES
HEX "00"
~6BYTES~4BYTES~
WRITE GATE .",
TURN ON FOR UPDATE ----./
OF NEXT DATA FIELD
!+18YTE+ 16 BYTES -+--48YTES---.t
'- WRITE TURN-OFF
~ FOR UPDATE OF
PREVIOUS DATA FIELD
FIGURE 7. SOFT SECTOR FORMAT (18 SECTORS PER TRACK)

2.0 DRIVE MOTOR CONTROL
• Start/Stop
•Speed Control
•Over
Current Protection
•Speed Adjust
The
motor used in the SA 400 is a DC drive motor
and has aseparate motor on and off interface line.
After activating the
motor on line, a 1 second delay
must be
introduced to allow proper motor speed
before reading or writing.
When
motor on is activated to PIN 16 on the drive
PCB this will
start the motor by causing current to
flow
thm the motor windings. Figure 8shows the
functional diagram
of the motor speed control cir-
cuit.
The motor speed control utilizes an integral
brushless tachometer. The
output voltage signal
from this
tachometer is compared to avoltage/
frequency reference level. The
output from the
voltage/frequency comparator will control the
necessary current to maintain a constant motor
speed of 300 RPM. Motor speed adjustment
changes the V ref thm a Potentiometer.
+TACH IN
MOTOR +MOTOR
OUT
-MOTOR OUT
-MOTOR ON ----------.--------'
FIGURE 8. MOTOR CONTROL FUNCTIONAL DIAGRAM
6

3.0 DRIVE SELECTION
3.1 HEAD LOAD
When the shunt block position HL'is shorted the
head will load, by energizing the head load solen-
oid, when drive select is brought to an active low.
Reference Figure 9.
If the shunt block i.s positioned so HL is open
and MH is shorted the head will load with--
Motor On signal, irregardless of the state of
drive select. Reference Figure 9.
3.2 SINGLE DRIVE SYSTEM
With MX jumper shorted the input to the or gate
for
output enable is at alow level. This causes the
signal output enable to always be true when the
drive is powered on. Activating any drive select
line will light
the activity lite and enable reading
and writing if the motor is running and the head
is loaded. Refer to Figure 9for the logic required.
3.3 MULTIPLE DRIVE SYSTEM
There are 3drive select lines. In multiple drive sys-
tems leave the jumper uncut in the shunt block for
the drive number you wish to select. MX must
be cut for the input & output to be daisey chained.
With MX cut drive select must be true in order to
activate output enable which in turn gates the out-
put lines lites the activity lite and conditions the
input lines. Reading and writing can now be per-
formed if the motor is running and the head is
loaded. Figure 9is the drive select functional
diagram.
OUPUT LINES
ACTIVITY LITE
READ
INPUT LINES
DS13
DS2 DRIVE
SELECT
DS3 ---
[II
MOTOR ON 0MH
---4 • ..----0 10----------.
I[J--------- .....
HL
+5
---'V\/'y--..-----
READ PULSE
READ
ENABLE
TRK 00 SWITCH
INDEX PULSE
OUTPUT ENABLE
WRITE PROT SWITCH
PHASE A
TO
STEP COUNTER
MX
OPEN FOR MULTIPLE
DRIVE SYSTEM.
STEP
~-
20
LEAVE SHORTED THE
STRAP IN THE SHUNT
BLOCK FOR THE
DRIVE
YOU WISH TO SELECT.
WRITE GATE
~
24
MH SHORTED THE HEAD
WI LL LOAD WITH -MOTOR ON.
HL SHORTED THE HEAD WI LL
LOAD WITH -DRIVE SELECT.
FIGURE 9. DRIIVE SELECT FUNCTIONAL DIAGRAM
7

CD +-OUTPUT ENABLE
4.0 INDEX DETECTOR
Each time an index or sector hole is moved past the
index photo detector, apulse
is formed. This pulse
is present on the interface as index/sector pin 8.
Without aDiskette in the drive the
output line will
be low so the using system must look for atransi-
tion
to be avalid signal. The detector output is fed
into aschmidt trigger with alevel trigger latch back
to maintain pulse stability, while shaping the pulse.
With
output enable true this pulse will be on the
interface
as anegative going pulse. Refer to figures
10 and
11 for logic required and timings. Shown is
the output from asoft sector Diskette.
+5
0-
INDEX SECTOR
L..---.----------I ~
FIGURE 10. INDEX DETECTOR LOGIC
+\
__ /
_I I_
II
--~NDEX DETECTOR
1 ..... ','~J ----L _
I.. 200±7.2m.sec I
SOFT SECTOR --j
FIGURE 11. INDEX TIMING DIAGRAM
8

5.0 TRACK ZEBO IINDICATION
Track 00 signal (pin 26) is provided to the using
system
to indicate when the read/write head is
positioned
on track zero. Figures 12 & 13 show
the logic
and timing for the track zero indi.cation.
The
track zero micro switch is actuated by the car-
riage
between track one and track zero. When the
carriage is stepped to track 00 stepper phase A is
Anded with the output from the track 00 switch.
The
output from this And gate conditions another
And gate and its other leg is output enable which
is true when the drive is selected in amultiple drive
system
or on power on in asingle drive system.
These conditions will cause a
TRK 00 indication to
the interface. Reference Figure
12 for the logic
required.
+OUTPUT ENABLE -------------,
-q~A----...,
0--
F
~---I DEBOUNCE
H
~---ICKT
..--~~- - TKOO
TP8
FIGURE 12. TRACK 00 INDICATION DIAGRAM
__ r
__ -----11 ____
__ --.r-L------..
_JI __
__ ---'L-
-----------_._------------ .....
1> B
1> C
1> D
1> A
------------.-----------------J~------ ...
TRACK 00
SWITCH (TP8)
ON TRACK
OUTPUT ENABLE __ J
STEP PULSE
DIRECTION
TKOO INTERFACE
SIGNAL PIN26
(TKOO SIGNAL)
____________ ..... OUTPUT ENABLE. TKOO SWITCH
•PHASE
A.
FIGURE 13. TRACK 00 TIMING DIAGRAM
9

6.0 TRACK ACCESSI NG
•Stepper Motor (4 Phase)
Ato be energized in the stepper. "Figure
15 and
16 shows the stepper control logic and timing."
•Stepper Control Logic
•Reverse Seek
•Forward Seek
•Track Zero Indication
Seeking the read/write head from one track to
an-
other is accomplished by selecting the desired direc-
tion utilizing the Direction Select Interface line,
loading the read/write head, and then pulsing the
Step line. Multiple track accessing
is accomplished
by repeated pulsing
of the Step line with write gate
inactive until the desired track has been reached.
Each pulse on the Step line will cause the read/
write head to move one track either in or
out de-
pending
on the Direction Select line.
6.1 STEPPER MOTOR
The 4phase stepper motor turns the head actuator
cam in 2step increments per track. Two incre-
ments will move the head one track
via aball bear-
ing follower which
is attached to the carriage as-
sembly. This follower rides in aspiral groove in
the face of the actuator cam.
The stepper motor has 4phases. Phase Aand phase
Care the active positions which are energized when
the head
is on track. The phases Band Dare trans-
ient states.
Two one shots to the stepper counter
logic provides the 2nd step pulse approximately
11
milliseconds after the step line goes negative pro-
viding the drive
is selected and read enable is true.
6.2 STEPPER CONTROL
During Power on Reset time the stepper control
shift register
is reset to zero. This will cause phase
With drive select and read enable true, this provides
the conditions which allows the step pulse to clock
the clock
input to the stepper control shift register.
As the stepper control shifts from one phase to an-
other the outputs are fed back to the 2nd pulse gen-
erator sis. When astep pulse causes the stepper
counter
to go from its on track phase via the clock
:input the two step sis
is fired. In approximately
11 milliseconds a 2nd clock to the shift register is
provided, this causes the stepper motor to step from
its transient phase Bor Dto the
next on track phase
Aor C. This
is the method that causes the stepper
to step 2times for each step pulse on the interface.
The circuit will also interlock any possibility
of
writing on the transient phases Band D.
The stepper control
is a 4 bit parallel access shift
register with Jand Kinputs.
It is used in the shift
mode when stepping
out and in the load mode
when stepping in. Only the A
Band C outputs are
used. The
4th output is D' and is true when the
other outputs are zero.
6.3 STEPOUT
Figure 14 shows the logic for how the bit for step-
ping
is shifted when direction is high and the shift
register is in ashift mode or step out.
6.4 STEP IN MODE
When direction is low the drive is in astep in mode.
The shift register
is in aload mode. Its outputs are
being used to load the inputs. Figure
17 shows the
logic
on this and how the outputs are shifted. Ref-
erence figure 16 for timing. Again only A B &C
outputs are used, the
4th output is D'.
D'
INPUT TO SECOND
PULSE
GENERATOR
P
...
0
R
0A
,..,
0100
'"
0100B
,....
0
'"
0 0 0 10C
,...,
'-'
00 0 0 1D
--
STATES
A
B
C
D
D.LffiriIi]
eLK nn n n
PULSE ---J UUU L
STEPPER ~
PHASE ~
FIGURE 14. STEP OUT LOGIC
10

+5V
AQA
.... -- ....
D--¥- </>0
D-",,*"- </>A
D-"""*- </>8
I'\--¥-- </>C
.---+--- ...... -+----HL~
01------....,
8Q
-OIFIECTION
-*·-----10
C
+REAO ENABLE
-STEP
)(
.....-----41 8
FiGURE 15. STEPPER CONTROL FUNCTION DIAGRAM
11

POR
STEP nn.
CLK
L,~
DIRECTION
</> A
~J
</> BI
~~
I
</> Cn
~T
11
</> Dn
r~
I
FIGURE 16. STEP TIMING Dlt\GRAM
INPUT TO SECOND
PULSE
GENERATOR
=r-
A
B
C
D
_.-
LA
00010
-00100B
01000C
'--
H
~O
0001
D
--
=-----.-.-- .. --------- .. ---1
D'~
ClK
PULSE JUU1..fL
STEPPER ~
PHASE ~
FIGURE 17. STEP IN LOGIC
12

13
7.0 READ-WRITE OPERATIONS
•SA 400 Minifloppy uses double frequency NRZI
recording method.
•The read/write head, in general,
is aring with a
gap and acoil wound at some point on the ring.
•During awrite operation, a
bit is recorded when
the flux direction in the ring
is reversed by
rapidly reversing the current in the coil.
•During aread operation, a
bit is read when the
flux direction in the ring
is reversed as aresult
of aflux reversal on the diskette surface.
7.1 The SA 400 drive uses the double-
frequency
(2F) longitudinal non return to zero
(NRZI) method
of recording. Double frequency
is the term given to the recording system that in-
serts aclock bit at the beginning
of each bit cell
time thereby doubling the frequency
of recorded
bits. This clock bit,
as well as the data bit, are
provided by the using system. See Figure 18.
7.2 The read/write head is aring with agap and
acoil wound some
point on the ring. When cur-
rent flows through the coil, the flux induced in
the ring fringes at the gap.
As the diskette record-
ing surface passes
by the gap, the fringe flux mag-
netizes the surface in alongitudinal direction.
See Figure 19.
7.3 The drive writes 2frequencies IF 62.5 KHz
and
2F 125 KHz. During awrite operation, a bit
is recorded when the flux direction in the ring is
reversed by rapidly reversing the current in the
coil. The fringe flux
is reversed in the gap and
hence the portion
of the flux flowing through the
oxide recording surface
is reversed. If the flux reo
versal is instantaneous in comparison to the mo-
tion
of the diskette, it can be seen that the portion
of the diskette surface that just passed under the
gap
is magnetized in one direction while the por-
tion under the gap
is magnetized in the opposite
direction. This flux reversal represents abit. See
Figure 20.
7.4 During aread operation, abit is read when
the flux direction in the ring
is reversed as aresult
of aflux reversal on the diskette surface. The gap
first passes over an area
that is magnetized in one
direction, and aconstant flux flows through the
ring and coil. The coil registers no
output voltage
at this point. When arecorded bit passes under
the gap, the flux flowing through
the ring and coil
will make a1800reversal. This means
that the flux
reversal in the coil will cause avoltage
output pulse.
See Figure
21 .

CDCDCcCD C CD
BINARY
REPRESENTATION
-
BIT CELL 0
BIT CELL 1 BIT CELL 2B
1 1 0
f------~ ..
~-
--
--
-
IT CELL 3 BIT CELL 4
BIT CELL 5
BIT CELL 6
BIT CELL 7
01010
A
\1..- ...,---- __ ,_--J/\1..- -.- __ -----J
1
I
C
HEX
I~EPRESENTATION
FIGURE 18. BIT CELL
CURRENT
...
FRINGE
FLUX
OXIDE
CRECORDING
SURFACE
1
MYLAR ®
BASE
DISKETTE MOTION
FIGURE 19. BASIC READ/WRITE HEAD
-
CURRENT
~
RECOFIDED BIT
.. DISKETTE MOTION
FIGURE 20. RECORDED BIT
14