Toshiba TXZ Plus Series User manual

TXZ+ Family
TMPM4N Group(1)
Input/Output Ports
2021-01-18
Rev. 1.0
1 / 82
© 2020-2021
Toshiba Electronic Devices & Storage Corporation
2021-01
32-bit RISC Microcontroller
TXZ+ Family
TMPM4N Group(1)
Reference Manual
Input/Output Ports
(PORT-M4N(1))
Revision 1.0

TXZ+ Family
TMPM4N Group(1)
Input/Output Ports
2021-01-18
Rev. 1.0
2 / 82
Contents
Preface ................................................................................................................................................................. 5
Related document.....................................................................................................................................................5
Conventions ..............................................................................................................................................................6
Terms and Abbreviations ..........................................................................................................................................8
1. Outlines ......................................................................................................................................................... 9
2. Function ...................................................................................................................................................... 11
2.1. Clock supply.....................................................................................................................................................11
3. Signal connection list .................................................................................................................................. 12
4. Registers ..................................................................................................................................................... 33
4.1. List of Register .................................................................................................................................................34
4.2. List of Port Functions and Settings ..................................................................................................................37
4.2.1. Setting of using the alternated pin ..............................................................................................................................37
4.2.2. PORT A ......................................................................................................................................................................38
4.2.3. PORT B ......................................................................................................................................................................40
4.2.4. PORT C......................................................................................................................................................................41
4.2.5. PORT D......................................................................................................................................................................42
4.2.6. PORT E ......................................................................................................................................................................44
4.2.7. PORT F ......................................................................................................................................................................46
4.2.8. PORT G......................................................................................................................................................................47
4.2.9. PORT H......................................................................................................................................................................49
4.2.10. PORT J.....................................................................................................................................................................50
4.2.11. PORT K ....................................................................................................................................................................51
4.2.12. PORT L ....................................................................................................................................................................53
4.2.13. PORT M ...................................................................................................................................................................55
4.2.14. PORT N....................................................................................................................................................................57
4.2.15. PORT P ....................................................................................................................................................................58
4.2.16. PORT R....................................................................................................................................................................60
4.2.17. PORT T ....................................................................................................................................................................61
4.2.18. PORT U....................................................................................................................................................................62
4.2.19. PORT V ....................................................................................................................................................................64
4.2.20. PORT W ...................................................................................................................................................................66
4.2.21. PORT Y ....................................................................................................................................................................67
5. Block Diagrams of Ports ............................................................................................................................. 68
5.1. Type FTU1 .......................................................................................................................................................69
5.2. Type FTU2 .......................................................................................................................................................70
5.3. Type FTU2b .....................................................................................................................................................71
5.4. Type FTU3 .......................................................................................................................................................72
5.5. Type FTU4 .......................................................................................................................................................73
5.6. Type FTU5 .......................................................................................................................................................74
5.7. Type FTU6 .......................................................................................................................................................75

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TMPM4N Group(1)
Input/Output Ports
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Rev. 1.0
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5.8. Type FTU10 .....................................................................................................................................................76
5.9. Type FTU13 .....................................................................................................................................................77
5.10. Type FTU14 ...................................................................................................................................................78
5.11. Type FTU15 ...................................................................................................................................................79
6. Precaution ................................................................................................................................................... 80
6.1. Pin status during the reset period ....................................................................................................................80
6.2. Unused pins .....................................................................................................................................................80
6.3. Important points of using debug interface pins used as general-purpose ports..............................................80
7. Revision History .......................................................................................................................................... 81
RESTRICTIONS ON PRODUCT USE............................................................................................................... 82
List of Figures
Figure 5.1 Port Type FTU1 ...................................................................................................................... 69
Figure 5.2 Port Type FTU2 ...................................................................................................................... 70
Figure 5.3 Port Type FTU2b .................................................................................................................... 71
Figure 5.4 Port Type FTU3 ...................................................................................................................... 72
Figure 5.5 Port Type FTU4 ...................................................................................................................... 73
Figure 5.6 Port Type FTU5 ...................................................................................................................... 74
Figure 5.7 Port Type FTU6 ...................................................................................................................... 75
Figure 5.8 Port Type FTU10 .................................................................................................................... 76
Figure 5.9 Port Type FTU13 .................................................................................................................... 77
Figure 5.10 Port Type FTU14 .................................................................................................................. 78
Figure 5.11 Port Type FTU15 .................................................................................................................. 79

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TMPM4N Group(1)
Input/Output Ports
2021-01-18
Rev. 1.0
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List of Tables
Table 1.1 Features ..................................................................................................................................... 9
Table 3.1 Signal connection list (1/21)..................................................................................................... 12
Table 3.2 Signal connection list (2/21)..................................................................................................... 13
Table 3.3 Signal connection list (3/21)..................................................................................................... 14
Table 3.4 Signal connection list (4/21)..................................................................................................... 15
Table 3.5 Signal connection list (5/21)..................................................................................................... 16
Table 3.6 Signal connection list (6/21)..................................................................................................... 17
Table 3.7 Signal connection list (7/21)..................................................................................................... 18
Table 3.8 Signal connection list (8/21)..................................................................................................... 19
Table 3.9 Signal connection list (9/21)..................................................................................................... 20
Table 3.10 Signal connection list (10/21)................................................................................................. 21
Table 3.11 Signal connection list (11/21)................................................................................................. 22
Table 3.12 Signal connection list (12/21)................................................................................................. 23
Table 3.13 Signal connection list (13/21)................................................................................................. 24
Table 3.14 Signal connection list (14/21)................................................................................................. 25
Table 3.15 Signal connection list (15/21)................................................................................................. 26
Table 3.16 Signal connection list (16/21)................................................................................................. 27
Table 3.17 Signal connection list (17/21)................................................................................................. 28
Table 3.18 Signal connection list (18/21)................................................................................................. 29
Table 3.19 Signal connection list (19/21)................................................................................................. 30
Table 3.20 Signal connection list (20/21)................................................................................................. 31
Table 3.21 Signal connection list (21/21)................................................................................................. 32
Table 4.1 Ports base address .................................................................................................................. 34
Table 4.2 Register List ............................................................................................................................. 35
Table 4.3 Port A registers setting............................................................................................................. 38
Table 4.4 Port B registers setting............................................................................................................. 40
Table 4.5 Port C registers setting............................................................................................................. 41
Table 4.6 Port D registers setting............................................................................................................. 42
Table 4.7 Port E registers setting............................................................................................................. 44
Table 4.8 Port F registers setting............................................................................................................. 46
Table 4.9 Port G registers setting ............................................................................................................ 47
Table 4.10 Port H registers setting .......................................................................................................... 49
Table 4.11 Port J registers setting ........................................................................................................... 50
Table 4.12 Port K registers setting........................................................................................................... 51
Table 4.13 Port L registers setting ........................................................................................................... 53
Table 4.14 Port M registers setting .......................................................................................................... 55
Table 4.15 Port N registers setting .......................................................................................................... 57
Table 4.16 Port P registers setting........................................................................................................... 58
Table 4.17 Port R registers setting .......................................................................................................... 60
Table 4.18 Port T registers setting........................................................................................................... 61
Table 4.19 Port U registers setting .......................................................................................................... 62
Table 4.20 Port V registers setting........................................................................................................... 64
Table 4.21 Port W registers setting.......................................................................................................... 66
Table 4.22 Port Y registers setting........................................................................................................... 67
Table 7.1 Revision History ....................................................................................................................... 81

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TMPM4N Group(1)
Input/Output Ports
2021-01-18
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Preface
Related document
Document name
Product Information
Clock Control and Operation Mode
Exception
Flash Memory
8-bit Digital to Analog Convertor
I2C Interface
I2C Interface Version A
I2S Interface
Serial Peripheral Interface
Synchronous Serial interface
CAN Controller
Universal Serial Bus
Ethernet Mac
Multi-function DMA Controller
High Speed DMA Controller
12-bit Analog to Digital Convertor
32-bit Timer Event Counter
Asynchronous Serial Communication Circuit
Full Asynchronous Serial Communication Circuit
Serial Memory Interface
Real Time Clock
Remote Control Signal preprocessor
Consumer Electronics Control
Advanced Programmable Motor Control Circuit
Debug Interface
Boundary-scan
External Bus Interface
Non Break Debug Interface

TXZ+ Family
TMPM4N Group(1)
Input/Output Ports
2021-01-18
Rev. 1.0
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Conventions
●Numeric formats follow the rules as shown below:
Hexadecimal: 0xABC
Decimal: 123 or 0d123 – Only when it needs to be explicitly shown that they are decimal numbers.
Binary: 0b111 – It is possible to omit the "0b" when the number of bit can be distinctly understood from a
sentence.
●"_N" is added to the end of signal names to indicate low active signals.
●It is called "assert" that a signal moves to its active level, "deassert" to its inactive level.
●When two or more signal names are referred, they are described like as [m: n].
Example: S[3: 0] shows four signal names S3, S2, S1 and S0 together.
●The characters surrounded by [ ] defines the register.
Example: [ABCD]
●"n" substitutes suffix number of two or more same kind of registers, fields, and bit names.
Example: [XYZ1], [XYZ2], [XYZ3] [XYZn]
●"x" substitutes suffix number or character of units and channels in the Register List.
In case of unit, "x" means A, B, and C ...
Example: [ADACR0], [ADBCR0], [ADCCR0] [ADxCR0]
In case of channel, "x" means 0, 1, and 2 ...
Example: [T32A0RUNA], [T32A1RUNA], [T32A2RUNA] [T32AxRUNA]
●The bit range of a register is written like as [m: n].
Example: Bit[3: 0] expresses the range of bit 3 to 0.
●The configuration value of a register is expressed by either the hexadecimal number or the binary number.
Example: [ABCD]<EFG> =0x01 (hexadecimal), [XYZn]<VW> =1 (binary)
●Word and Byte represent the following bit length.
Byte: 8 bits
Half word: 16 bits
Word: 32 bits
Double word: 64 bits
●Properties of each bit in a register are expressed as follows:
R: Read only
W: Write only
R/W: Read and Write are possible
●Unless otherwise specified, register access supports only word access.
●The register defined as reserved must not be rewritten. Moreover, do not use the read value.
●The value read from the bit having default value of "—" is unknown.
●When a register containing both of writable bits and read-only bits is written, read-only bits should be written
with their default value, in the cases that default is "—", follow the definition of each register.
●Reserved bits of the Write-only register should be written with their default value.
In the cases that default is "—", follow the definition of each register.
●Do not use read-modified-write processing to the register of a definition which is different by writing and
read out.

TXZ+ Family
TMPM4N Group(1)
Input/Output Ports
2021-01-18
Rev. 1.0
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All other company names, product names, and service names mentioned herein may be trademarks of their
respective companies.

TXZ+ Family
TMPM4N Group(1)
Input/Output Ports
2021-01-18
Rev. 1.0
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Terms and Abbreviations
Some of abbreviations used in this document are as follows:
CAN Controller Area Network
CEC Consumer Electronics Control
DMA Direct Memory Access
I2C Inter-Integrated Circuit
I2S Inter-IC Sound
JTAG Joint Test Action Group
NBDIF Non Break Debug Interface
PORF Power On Reset Circuit for FLASH and debug
SW Serial Wire

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TMPM4N Group(1)
Input/Output Ports
2021-01-18
Rev. 1.0
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1. Outlines
It is described about the register and setting of port. A list of the functions is indicated below.
Table 1.1 Features
Function
Classification
Function Description
Port - Programmable pull-up /Programmable pull-down /Open-drain output
are possible.
Peripheral
Function pins
Interrupt control External Interrupt pin
Interrupt pin has a noise filter (Filter width 30 ns Typ.).
32-bit Timer Event Counter Input capture input pin. Timer output pin.
Serial Peripheral Interface Chip select input 1 pin, Chip select output 4 pins, Data input pin, Data
output pin, Clock input/output pin
Synchronous Serial Interface Data input pin, Data output pin, Frame synchronous input/output pins,
Clock input/output pins
Asynchronous Serial
Communication Circuit
Data input pin, Data output pin, Handshake function pins.
Full Asynchronous Serial
Communication Circuit
Data input pin, Data output pin, Handshake function pins, IrDA1.0
data input/output pin
I2C Interface Data input/output pin, Clock input/output pin
I2C Interface version A Data input/output pin, Clock input/output pin
I2S Interface Data input pin, Data output pin, LR clock input/output pin, Bit clock
input/output pin, Master clock input/output pin
Serial Memory Interface Chip select input/output pin, Data input/output pin, Clock input/output
pin
CAN Controller Data input pin, Data output pin
Universal Serial Bus
SOF output, ID detection pin, VBUS control pin, DP signal pin, DM
signal pin, VBUS detection pin
Ethernet MAC
PPS output 2 pins, MDC output pin, MDIO input pin, CRS input pin,
COL input pin, TXCLK input pin, TXD output 4 pins, TXEN output pin,
RXCLK input pin, RXD input 4 pins, RXDV input pin, RXER input pin
Multi-Function DMA Controller MDMA Request input pin
High Speed DMA Controller HDMA Request input pin
Interval Sensor Detection Data input pin, Data output pin
Consumer Electronics Control Data input/output pin,
External Bus Interface
Address bus output pin, Data bus input/output pin, Read strobe output
pin, Write strobe output pin, Chip Select output pin, Byte Enable
output pin, Address Latch Enable output pin, Wait input pin, Clock
output pin
Advanced Programmable Motor
Control Circuit
X/Y/Z phase output pins, U/V/W phase output pins, EMG detection
input pin, OVV detection input pin.
Remote Control Signal
preprocessor
Data input pin
12-bit Analog to Digital Convertor Analog input pin, AD Trigger input pin
8-bit Digital to Analog Convertor DAC output pin
Real Time Clock 1 Hz clock output pin, Alarm output pin
Trigger Input TRGINx pin

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TMPM4N Group(1)
Input/Output Ports
2021-01-18
Rev. 1.0
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Function
Classification
Function Description
Debug pins
JTAG Test select input pin, Serial clock input pin, Serial data output pin,
Serial data input pin, Test reset pin
SW
Serial wire data input/output pin, Serial wire clock input pin, Serial wire
viewer output pin
Trace Trace clock output pin, Trace data output 4pins.
NBDIF NBD synchronous input pin, NBD clock input pin, NBD data
input/output 4pins.
Control pins
High speed resonator High speed resonator connection pin, External High speed clock input
Low speed resonator Low speed resonator connection pin, External Low Speed clock input
BOOT mode control BOOT mode control pin

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TMPM4N Group(1)
Input/Output Ports
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2. Function
2.1. Clock supply
When PORT is used, the corresponding clock enable bits should be set to "1" (Clock supply) in fsys supply stop
register A ([CGFSYSENA] and [CGFSYSMENA]), fsys supply stop register B ([CGFSYSENB] and
[CGFSYSMENB]), fsys supply stop register C ([CGFSYSMENC]), and fc supply stop register ([CGFCEN]).
The corresponding registers and the bit locations depend on a product. Some products do not have all registers.
For the details, refer to reference manual "Clock Control and Operation Mode".

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TMPM4N Group(1)
Input/Output Ports
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3. Signal connection list
The function pins are sorted by the signal name of the block diagram which is described in each reference manual
in this table. Register setting of the peripheral function is explained in the order of port, so please use for a reverse
lookup of port name.
The numerical value shows the pin number.
Table 3.1 Signal connection list (1/21)
Related Reference Manual
Function pin
name
Port
name
M4NR
(LQFP176)
M4NQ
(LQFP144)
M4NN
(LQFP100)
M4NR
(BGA177)
M4NQ
(BGA145)
Asynchronous Serial
Communication Circuit
UT0RXD
PE2
60
52
39
T5
P5
PH4 89 73 51 R16 N14
PH5 88 72 50 T15 P13
UT0TXDA
PE3 61 53 40 T6 N6
PH5 88 72 50 T15 P13
PH4
89
73
51
R16
N14
UT0CTS_N
PE1
59
51
38
R5
N5
PH7 86 70 48 R14 N12
PH6 87 71 49 R15 P12
UT0RTS_N
PE0 58 50 37 R4 N4
PH6 87 71 49 R15 P12
PH7 86 70 48 R14 N12
UT1RXD
PH0 93 77 55 N16 L11
PH1 92 76 54 N15 M13
PV4 81 65 - R12 N10
UT1TXDA
PH1 92 76 54 N15 M13
PH0 93 77 55 N16 L11
PV5 80 64 - T12 P9
UT1CTS_N
PH3 90 74 52 P15 N13
PH2 91 75 53 P16 M14
PV6 79 63 - T11 N9
UT1RTS_N
PH2 91 75 53 P16 M14
PH3 90 74 52 P15 N13
PV7 78 62 - R11 L9
UT2RXD
PG0
129
105
72
D15
D13
PG1
130
106
73
C16
C14
UT2TXDA PG1 130 106 73 C16 C14
PG0 129 105 72 D15 D13
UT2CTS_N PG3 132 108 75 B16 B14
PG2 131 107 74 C15 C13
UT2RTS_N PG2 131 107 74 C15 C13
PG3 132 108 75 B16 B14

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TMPM4N Group(1)
Input/Output Ports
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Table 3.2 Signal connection list (2/21)
Related Reference Manual
Function pin
name
Port
name
M4NR
(LQFP176)
M4NQ
(LQFP144)
M4NN
(LQFP100)
M4NR
(BGA177)
M4NQ
(BGA145)
Asynchronous Serial
Communication Circuit
UT3RXD
PU6 40 - - M4 -
PV0 115 97 - F12 F10
PV1 114 96 - G13 F11
UT3TXDA
PU7 41 - - M2 -
PV1 114 96 - G13 F11
PV0 115 97 - F12 F10
UT3CTS_N
PU5
39
-
-
L4
-
PV3 112 94 - H13 G10
PV2 113 95 - G12 G11
UT3RTS_N
PU4 38 - - L5 -
PV2 113 95 - G12 G11
PV3 112 94 - H13 G10
UT4RXD PM0 124 102 - E16 D14
PM1 123 101 - F15 E13
UT4TXDA
PM1 123 101 - F15 E13
PM0 124 102 - E16 D14
PU0 35 31 - L2 J2
UT4CTS_N
PM3 121 99 - E13 F13
PM2 122 100 - F16 E14
PU2 36 32 - K5 K4
UT4RTS_N
PM2 122 100 - F16 E14
PM3 121 99 - E13 F13
PU3 37 33 - K4 K2
UT5RXD PJ0 168 - - B5 -
PJ1 167 - - B6 -
UT5TXDA PJ1 167 - - B6 -
PJ0
168
-
-
B5
-
UT5CTS_N PJ3 165 - - D7 -
PJ2 166 - - D6 -
UT5RTS_N PJ2 166 - - D6 -
PJ3 165 - - D7 -

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TMPM4N Group(1)
Input/Output Ports
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Table 3.3 Signal connection list (3/21)
Related Reference Manual
Function pin
name
Port
name
M4NR
(LQFP176)
M4NQ
(LQFP144)
M4NN
(LQFP100)
M4NR
(BGA177)
M4NQ
(BGA145)
Full Asynchronous Serial
Communication Circuit
FUT0RXD PG5 96 80 58 M13 K11
PJ5 68 - - R9 -
FUT0TXD PG4 97 81 59 L12 K13
PJ4 69 - - T9 -
FUT0CTS_N PG7 94 78 56 M15 L13
FUT0RTS_N PG6 95 79 57 M16 L14
FUT0IROUT
PG4
97
81
59
L12
K13
FUT0IRIN PG5 96 80 58 M13 K11
FUT1RXD PJ7 66 - - N9 -
PM6 83 67 - R13 N11
FUT1TXD PJ6 67 - - R8 -
PM7 82 66 - T13 P10
FUT1CTS_N PM4 85 69 - N12 L10
FUT1RTS_N PM5 84 68 - T14 P11
FUT1IROUT PM7 82 66 - T13 P10
FUT1IRIN PM6 83 67 - R13 N11
I2C Interface (I2C, EI2C)
I2C0SDA
EI2C0SDA
PG2 131 107 74 C15 C13
I2C0SCL
EI2C0SCL
PG3 132 108 75 B16 B14
I2C1SDA
EI2C1SDA
PF2 174 142 98 B4 B5
I2C1SCL
EI2C1SCL
PF3 175 143 99 A3 B4
I2C2SDA
EI2C2SDA
PG4 97 81 59 L12 K13
PV5 80 64 - T12 P9
I2C2SCL
EI2C2SCL
PG5
96
80
58
M13
K11
PV4 81 65 - R12 N10
I2C3SDA
EI2C3SDA
PJ6 67 - - R8 -
PM0 124 102 - E16 D14
I2C3SCL
EI2C3SCL
PJ7
66
-
-
N9
-
PM1
123
101
-
F15
E13
I2C4SDA
EI2C4SDA
PJ3 165 - - D7 -
PM6 83 67 - R13 N11
I2C4SCL
EI2C4SCL
PJ2 166 - - D6 -
PM7 82 66 - T13 P10

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TMPM4N Group(1)
Input/Output Ports
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Table 3.4 Signal connection list (4/21)
Related Reference Manual
Function pin
name
Port
name
M4NR
(LQFP176)
M4NQ
(LQFP144)
M4NN
(LQFP100)
M4NR
(BGA177)
M4NQ
(BGA145)
Interval Sensor Detection
Circuit
ISDAIN0 PE4 62 54 41 R6 P6
ISDAIN1 PE5 63 55 42 R7 P7
ISDAIN2 PE6 64 56 43 T7 N7
ISDAIN3 PE7 65 57 44 T8 N8
ISDAOUT PK0 111 93 71 H12 H10
ISDBIN0 PV0 115 97 - F12 F10
ISDBIN1
PV1
114
96
-
G13
F11
ISDBIN2 PV2 113 95 - G12 G11
ISDBIN3 PV3 112 94 - H13 G10
ISDBOUT PK1 110 92 - J12 H11
ISDCIN0 PW4 120 - - G15 -
ISDCIN1 PW5 119 - - G16 -
ISDCIN2 PW6 118 - - H15 -
ISDCIN3 PW7 117 - - H16 -
ISDCOUT PY4 22 - - J4 -
Serial Peripheral Interface
TSPI0CSIN PA0 21 17 15 J5 J5
TSPI0CS0 PA0 21 17 15 J5 J5
TSPI0CS1 PA4 17 13 11 G5 G5
TSPI0CS2 PA5 16 12 10 F4 F4
TSPI0CS3 PA6 15 11 9 E1 F5
TSPI0RXD PA2 19 15 13 H5 H5
TSPI0TXD PA3 18 14 12 G4 G4
TSPI0SCK PA1 20 16 14 H4 H4
TSPI1CSIN PL0 103 85 63 L13 J11
TSPI1CS0 PL0 103 85 63 L13 J11
TSPI1CS1 PK4 107 89 67 J15 G14
TSPI1CS2
PK5
106
88
66
K15
H13
TSPI1CS3 PK6 105 87 65 J16 H14
TSPI1RXD PL2 101 83 61 L15 J13
TSPI1TXD PL3 100 82 60 L16 K14
TSPI1SCK PL1 102 84 62 K16 J14
TSPI2CSIN PA7 14 10 - E2 E4
PF7 3 3 2 B1 B2
TSPI2CS0 PF7 3 3 2 B1 B2
PA7 14 10 - E2 E4
TSPI2CS1 PA3 18 14 12 G4 G4
TSPI2RXD PA5 16 12 10 F4 F4
TSPI2TXD PA4 17 13 11 G5 G5
TSPI2SCK PA6 15 11 9 E1 F5

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TMPM4N Group(1)
Input/Output Ports
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Table 3.5 Signal connection list (5/21)
Related Reference Manual
Function pin
name
Port
name
M4NR
(LQFP176)
M4NQ
(LQFP144)
M4NN
(LQFP100)
M4NR
(BGA177)
M4NQ
(BGA145)
Serial Peripheral Interface
TSPI3CSIN PK7 104 86 64 K12 J10
PK1 110 92 70 J12 H11
TSPI3CS0 PK1 110 92 70 J12 H11
PK7 104 86 64 K12 J10
TSPI3CS1 PL3 100 82 60 L16 K14
TSPI3RXD PK5 106 88 66 K15 H13
TSPI3TXD
PK4
107
89
67
J15
G14
TSPI3SCK PK6 105 87 65 J16 H14
TSPI4CSIN PD0 48 40 29 N5 L4
TSPI4CS0 PD0 48 40 29 N5 L4
TSPI4RXD PD2 50 42 31 N6 K6
TSPI4TXD PD3 51 43 32 M7 L6
TSPI4SCK PD1 49 41 30 M6 L5
TSPI5CSIN PV7 78 62 - R11 L9
TSPI5CS0 PV7 78 62 - R11 L9
TSPI5RXD PV4 81 65 - R12 N10
TSPI5TXD PV5 80 64 - T12 P9
TSPI5SCK PV6 79 63 - T11 N9
TSPI6CSIN PM3 121 99 - E13 F13
TSPI6CS0 PM3 121 99 - E13 F13
TSPI6RXD PM1 123 101 - F15 E13
TSPI6TXD PM0 124 102 - E16 D14
TSPI6SCK PM2 122 100 - F16 E14
TSPI7CSIN PM4 85 69 - N12 L10
TSPI7CS0 PM4 85 69 - N12 L10
TSPI7RXD PM6 83 67 - R13 N11
TSPI7TXD
PM7
82
66
-
T13
P10
TSPI7SCK PM5 84 68 - T14 P11
TSPI8CSIN PW0 77 - - M11 -
TSPI8CS0 PW0 77 - - M11 -
TSPI8RXD PW2 75 - - M10 -
TSPI8TXD PW3 74 - - N10 -
TSPI8SCK PW1 76 - - N11 -

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TMPM4N Group(1)
Input/Output Ports
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Table 3.6 Signal connection list (6/21)
Related Reference Manual
Function pin
name
Port
name
M4NR
(LQFP176)
M4NQ
(LQFP144)
M4NN
(LQFP100)
M4NR
(BGA177)
M4NQ
(BGA145)
Synchronous Serial interface
TSSI0TCK PD2 50 42 31 N6 K6
TSSI0TFS PD3 51 43 32 M7 L6
TSSI0TXD PD4 52 44 33 N7 L7
TSSI0RCK PD7 55 47 36 M9 L8
TSSI0RFS PD6 54 46 35 N8 K8
TSSI0RXD PD5 53 45 34 M8 K7
TSSI1TCK
PU2
36
-
-
K5
-
TSSI1TFS PU3 37 - - K4 -
TSSI1TXD PU4 38 - - L5 -
TSSI1RCK PU7 41 - - M2 -
TSSI1RFS PU6 40 - - M4 -
TSSI1RXD PU5 39 - - L4 -
Serial Memory Interface
SMI0CS1_N PK0 111 93 71 H12 H10
SMI0D0 PK2 109 91 69 J13 F14
SMI0D1 PK3 108 90 68 K13 G13
SMI0D2 PK4 107 89 67 J15 G14
SMI0D3 PK5 106 88 66 K15 H13
SMI0D4 PL0 103 85 63 L13 J11
SMI0D5 PL1 102 84 62 K16 J14
SMI0D6 PL2 101 83 61 L15 J13
SMI0D7 PL3 100 82 60 L16 K14
SMI0CLK PK6 105 87 65 J16 H14
SMI0CS0_N PK7 104 86 64 K12 J10

TXZ+ Family
TMPM4N Group(1)
Input/Output Ports
2021-01-18
Rev. 1.0
18 / 82
Table 3.7 Signal connection list (7/21)
Related Reference Manual
Function pin
name
Port
name
M4NR
(LQFP176)
M4NQ
(LQFP144)
M4NN
(LQFP100)
M4NR
(BGA177)
M4NQ
(BGA145)
I2S Interface
I2S0MCLK PB0 13 9 8 D1 C1
I2S0LRCK PD4 52 44 33 N7 L7
I2S0BCK PD5 53 45 34 M8 K7
I2S0DO PD7 55 47 36 M9 L8
I2S0DI PD6 54 46 35 N8 K8
I2S1MCLK PG6 95 79 57 M16 L14
I2S1LRCK
PE7
65
57
44
T8
N8
I2S1BCK PE6 64 56 43 T7 N7
I2S1DO PE4 62 54 41 R6 P6
I2S1DI PE5 63 55 42 R7 P7

TXZ+ Family
TMPM4N Group(1)
Input/Output Ports
2021-01-18
Rev. 1.0
19 / 82
Table 3.8 Signal connection list (8/21)
Related Reference Manual
Function pin
name
Port
name
M4NR
(LQFP176)
M4NQ
(LQFP144)
M4NN
(LQFP100)
M4NR
(BGA177)
M4NQ
(BGA145)
CAN Controller
CANARX PF7 3 3 2 B1 B2
PV5 80 64 - T12 P9
CANATX PF6 2 2 1 B2 B3
PV4 81 65 - R12 N10
CANBRX PE1 59 51 38 R5 N5
PU6 40 - - M4 -
CANBTX
PE0
58
50
37
R4
N4
PU7 41 - - M2 -
Universal Serial Bus
USBA_SOF_TGL PY4 22 18 16 J4 J4
USBA_ID PB3 10 6 5 E4 B1
USBA_VBUSEN PB2 11 7 6 F5 D4
USBA_DP - 27 23 21 H1 F1
USBA_DM - 26 22 20 G1 E1
USBA_VBUS - 24 20 18 F1 D1
USBB_SOF_TGL PF5 1 1 - B3 A2
PM1 123 101 - F15 E13
USBB_ID PU0 35 31 - L2 J2
USBB_VBUSEN PU3 37 33 - K4 K2
USBB_DP - 30 26 - K1 H1
USBB_DM - 29 25 - J1 G1
USBB_VBUS - 34 30 - L1 J1
USB_ECLK PB0 13 9 8 D1 C1

TXZ+ Family
TMPM4N Group(1)
Input/Output Ports
2021-01-18
Rev. 1.0
20 / 82
Table 3.9 Signal connection list (9/21)
Related Reference Manual
Function pin
name
Port
name
M4NR
(LQFP176)
M4NQ
(LQFP144)
M4NN
(LQFP100)
M4NR
(BGA177)
M4NQ
(BGA145)
Ethernet MAC
EMAPPSOUT0 PA2 19 15 13 H5 H5
PE2 60 52 39 T5 P5
EMAPPSOUT1 PA6 15 11 9 E1 F5
PE3 61 53 40 T6 N6
EMAMDC PG7 94 78 56 M15 L13
PK2 109 91 69 J13 F14
EMAMDIO
PH0
93
77
55
N16
L11
PK3 108 90 68 K13 G13
EMACOL PG3 132 108 75 B16 B14
EMACRS PG2 131 107 74 C15 C13
EMARXDV PG0 129 105 72 D15 D13
EMARXER PG1 130 106 73 C16 C14
EMATXEN PK0 111 93 71 H12 H10
EMARXCLK PL1 102 84 62 K16 J14
EMATXCLK PK4 107 89 67 J15 G14
PT4 116 98 - F13 E11
EMARXD0 PL2 101 83 61 L15 J13
PV0 115 97 - F12 F10
EMARXD1 PL3 100 82 60 L16 K14
PV1 114 96 - G13 F11
EMARXD2 PG4 97 81 59 L12 K13
PV2 113 95 - G12 G11
EMARXD3 PG5 96 80 58 M13 K11
PV3 112 94 - H13 G10
EMATXD0 PL0 103 85 63 L13 J11
PM3 121 99 - E13 F13
EMATXD1
PK7
104
86
64
K12
J10
PM2 122 100 - F16 E14
EMATXD2 PK6 105 87 65 J16 H14
PM1 123 101 - F15 E13
EMATXD3 PK5 106 88 66 K15 H13
PM0 124 102 - E16 D14
EMA_R_CRSDV PG0 129 105 72 D15 D13
EMA_R_TXEN PK0 111 93 71 H12 H10
EMA_R_REFCLK PL1 102 84 62 K16 J14
EMA_R_RXD0 PL2 101 83 61 L15 J13
PV0 115 97 - F12 F10
EMA_R_RXD1 PL3 100 82 60 L16 K14
PV1 114 96 - G13 F11
EMA_R_TXD0 PL0 103 85 63 L13 J11
EMA_R_TXD1 PK7 104 86 64 K12 J10