Sino Wealth SH79F1622 User manual

SH79F1622
8051 Microcontroller with 20 channels Touch-key input and TONE
1 V2.2
1. Features
8bits micro-controller with Pipe-line structured 8051
compatible instruction set
Flash ROM: 16K Bytes
RAM: internal 256 Bytes, external 1280 Bytes
Operation Voltage: 2.7V - 5.5V
Oscillator:
- Internal RC: 27MHz (±2%)
- External crystal oscillator: 32.768kHz
28pin: 25 CMOS bi-directional I/O pins
20pin: 17 CMOS bi-directional I/O pins
Built-in pull-up resistor for input pin
Three 16-bit timer/counters T2, T3 & T4
20 channels Touch Key input
Built-in Touch Key comparison voltage:
1V, 1.5V, 2V, 2.5V
7 COM 16 SEG LED drive
Touch Key sharing with LED drive
Powerful interrupt sources:
- Timer2, 3, 4
- INT0, INT1, INT2, INT4
- EUART
- Touch Key
- TWI
EUART with Baud-rate generator
TWI communication interface
Built-in 2 channels programmable tone generator
CPU Machine cycle: 1 oscillator cycle
Watch Dog Timer (WDT)
Flash Type
Package: SOP28
SOP20
SOP16
2. General Description
The SH79F1622 is a high performance 8051 compatible micro-controller, regard to its build-in Pipe-line instruction fetch
structure, that helps the SH79F1622 can perform more fast operation speed and higher calculation performance, if compare
SH79F1622 with standard 8051 at same clock speed.
The SH79F1622 retains most features of the standard 8051. These features include internal 256 bytes RAM, three 16-bit
Timer/Counter. In addition, SH79F1622 provides external 1280 bytes RAM, It also contains 16K bytes Flash memory block for
storing programs.
SH79F1622 also integrate double channels tone generation module, LVR, TWI and Touch Key sharing with LED for saving pins.
SH79F1622 is very suitable for the application and control of Touch Key.
Also WDT and EUART are incorporated in SH79F1622.

SH79F1622
2
3. Block Diagram
16K Bytes
Flash ROM
Internal 256 Bytes
External 1280 Bytes
(Exclude System
Register)
Oscillator
Pipelined 8051 architecture
Timer 2 (16bit)
Timer 3 (16bit)
Timer 4(16bit)
v
Reset circuit RST
V
DD
External Interrupt
Power
Watch Dog
TONE
Port 3
Configuration I/Os
P1.0 - P1.7
P2.0 - P2.7
P0.0 - P0.7
Port 2
Configuration I/Os
P3.0 `
EUART0
Jtag ports
(for debug)
Touch key channel
Port 1
Configuration I/Os
Port 0
Configuration I/Os
TK1-TK20
LED Driver
TWI
SEG/COM

SH79F1622
3
4. Pin Configuration
SOP 28
79F1622
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TK4/SEG3/P0.3
TK3/SEG2/P0.2
XTAL2/TK2/SEG1/P0.1
XTAL1/TK1/SEG0/P0.0
VDD
Vss
C1
T2/TONE/COM6/INT40/P1.5
RST/T3/COM7/INT41/P1.6
P3.0/INT43/SDA/RXD
T4/COM1/P1.0
T2EX/TK17/COM2/P1.1
TK19/COM4/P1.3
TK20/COM5/P1.4 P2.7/INT0/SEG15/TK16
P2.6/INT1/SEG14/TK15
P2.5/INT2/SEG13/TK14
P2.4/SEG12/TK13
P2.3/SEG11/TK12
P2.2/SEG10/TK11
P2.1/SEG9/TK10
P2.0/SEG8/TK9
P0.7/SEG7/TK8/TDO
P0.6/SEG6/TK7/TMS
P0.5/SEG5/TK6/TDI
P0.4/SEG4/TK5/TCK
TK18/COM3/P1.2
P1.7/INT42/SCK/TXD
Pin Configuration Diagram SOP 28
SOP 20
79F1622
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TK4/SEG3/P0.3
TK3/SEG2/P0.2
XTAL2/TK2/SEG1/P0.1
XTAL1/TK1/SEG0/P0.0
VDD
Vss
C1
T4/COM1/P1.0
T2EX/TK17/COM2/P1.1
P1.3/COM4/TK19
P1.4/COM5/TK20
TK18/COM3/P1.2
P0.7/SEG7/TK8/TDO
P0.6/SEG6/TK7/TMS
P0.5/SEG5/TK6/TDI
P0.4/SEG4/TK5/TCK
P1.5/INT40/COM6/TONE/T2
P1.6/INT41/COM7/T3/RST
P3.0/INT43/SDA/RXD
P1.7/INT42/SCK/TXD
Pin Configuration Diagram SOP 20

SH79F1622
4
SOP 16
79F1622
1
2
3
4
5
6
7
8
TK3/SEG2/P0.2
XTAL2/TK2/SEG1/P0.1
XTAL1/TK1/SEG0/P0.0
VDD
Vss
C1
P1.5/INT40/COM6/TONE/T2
P3.0/INT43/SDA/RXD
T4/COM1/P1.0 P1.3/COM4/TK19
P1.4/COM5/TK20
P0.7/SEG7/TK8/TDO
P0.6/SEG6/TK7/TMS
P0.5/SEG5/TK6/TDI
TCK/TK5/SEG4/P0.4
P1.7/INT42/SCK/TXD
9
10
11
12
13
14
15
16
Pin Configuration Diagram SOP 16
Note:
1. SH79F1622 (SOP16) I/O (20PIN P0.3, P1.2, P1.6, P1.1), which is set to output low level, to avoid functional conflicts.
2. The out most pin function has the highest priority, and the inner most pin function has the lowest priority (Refer to Pin
Configuration Diagram). This means when one pin is occupied by a higher priority function (if enabled) cannot be used as the
lower priority functional pin, even when the lower priority function is also enabled. Until the higher priority function is closed by
software, can the corresponding pin be released for the lower priority function use.

SH79F1622
5
Table 4.1 28 Pin Function
Pin No. Pin Name Default Function Pin No. Pin Name Default Function
1 TK4/SEG3/P0.3 P0.3 15 P1.7/INT42/SCK/TXD P1.7
2 TK3/SEG2/P0.2 P0.2 16 P3.0/INT43/SDA/RXD P3.0
3 XTAL2/TK2/SEG1/P0.1 P0.1 17 P2.7/INT0/SEG15/TK16 P2.7
4 XTAL1/TK1/SEG0/P0.0 P0.0 18 P2.6/INT1/SEG14/TK15 P2.6
5 VDD ---- 19 P2.5/INT2/SEG13/TK14 P2.5
6 VSS ---- 20 P2.4/SEG12/TK13 P2.4
7 C1 ---- 21 P2.3/SEG11/TK12 P2.3
8 T4/COM1/P1.0 P1.0 22 P2.2/SEG10/TK11 P2.2
9 T2EX/TK17/COM2/P1.1 P1.1 23 P2.1/SEG9/TK10 P2.1
10 TK18/COM3/P1.2 P1.2 24 P2.0/SEG8/TK9 P2.0
11 TK19/COM4/P1.3 P1.3 25 P0.7/SEG7/TK8/TDO P0.7
12 TK20/COM5/P1.4 P1.4 26 P0.6/SEG6/TK7/TMS P0.6
13 T2/TONE/COM6/INT40/P1.5 P1.5 27 P0.5/SEG5/TK5/TDI P0.5
14 RST
————/T3/COM7/INT41/P1.6 P1.6 28 P0.4/SEG4/TK5/TCK P0.4
Table 4.2 20 Pin Function
Pin No. Pin Name Default Function Pin No. Pin Name Default Function
1 TK4/SEG3/P0.3 P0.3 11 P1.3/COM4/TK19 P1.3
2 TK3/SEG2/P0.2 P0.2 12 P1.4/COM5/TK20 P1.4
3 XTAL2/TK2/SEG1/P0.1 P0.1 13 P1.5/INT40/COM6/TONE/T2 P1.5
4 XTAL1/TK2/SEG0/P0.0 P0.0 14 P1.6/INT41/COM7/T3/RST
———— P1.6
5 VDD ---- 15 P1.7/INT42/SCK/TXD P1.7
6 VSS ---- 16 P3.0/INT43/SDA/RXD P3.0
7 C1 ---- 17 P0.7/SEG7/TK8/TDO P0.7
8 T4/COM1/P1.0 P1.0 18 P0.6/SEG6/TK7/TMS P0.6
9 T2EX/TK17/COM2/P1.1 P1.1 19 P0.5/SEG5/TK6/TDI P0.5
10 TK18/COM3/P1.2 P1.2 20 P0.4/SEG4/TK5/TCK P0.4
Table 4.3 16 Pin Function
Pin No. Pin Name Default Function Pin No. Pin Name Default Function
1 TCK/TK5/SEG4/P0.4 P0.4 9 TK19/COM4/P1.3 P1.3
2 TK3/SEG2/P0.2 P0.2 10 TK20/COM5/P1.4 P1.4
3 XTAL2/TK2/SEG1/P0.1 P0.1 11 T2/TONE/COM6/INT40/P1.5 P1.5
4 XTAL1/TK2/SEG0/P0.0 P0.0 12 TXD/SCK/INT42/P1.7 P1.7
5 VDD ---- 13 RXD/SDA/INT43/P3.0 P3.0
6 VSS ---- 14 TDO/TK8/SEG7/P0.7 P0.7
7 C1 ---- 15 TMS/TK7/SEG6/P0.6 P0.6
8 T4/COM1/P1.0 P1.0 16 TDI/TK5/SEG5/P0.5 P0.5
Note
：
SH79F1622 (SOP16) I/O (20PIN P0.3, P1.2, P1.6, P1.1), which is set to output low level, to avoid functional conflicts.

SH79F1622
6
5. Pin Description
Pin No. Type Description
I/O PORT
P0.0 - P0.7 I/O 8 bit General purpose CMOS I/O
P1.0 - P1.7 I/O 8 bit General purpose CMOS I/O
P2.0 - P2.7 I/O 8 bit General purpose CMOS I/O
P3.0 I/O General purpose CMOS I/O
Touch Key
TK1 - TK20 I Touch Key pin
C1 I External capacitor pin of Touch Key
Timer T2 I/O Timer2 external input/Baud-Rate generator
T3 I Timer3 external input
T4 I Timer4 external input
T2EX I Timer2 Reload/Capture/Direction Control
TONE
TONE O Tone output pin
LED
SEG1 - SEG16 O Segment signal output for LED display
COM1 - COM7 O Common signal output for LED display
EUART RXD I EUART0 data input
TXD O EUART0 data output
TWI SDA I/O TWI data input/output
SCK I/O TWI clock
Interrupt & Reset & Clock & Power
INT0 - INT2, INT4 I External interrupt 0-2, external interrupt 4 input source
RST
———— I The device will be reset by A low voltage on this pin longer than 10us, an internal
resistor about 30kΩ to VDD, So using only an external capacitor to GND can cause
a power-on reset.
VSS P Ground
VDD P Power supply (2.7 - 5.5V)
XTAL1 I Oscillator input
XTAL2 O Oscillator output
Programmer
TDO (P0.7) O Debug interface: Test data out
TMS (P0.6) I Debug interface: Test mode select
TDI (P0.5) I Debug interface: Test data in
TCK (P0.4) I Debug interface: Test clock in
Note: When P0.4-0.7 used as debug interface, functions of P0.4-0.7 are blocked.

SH79F1622
7
6. SFR Mapping
The SH79F1622 provides 256 bytes of internal RAM to contain general-purpose data memory and Special Function Register
(SFR). The SFR of the SH79F1622 fall into the following categories:
CPU Core Registers: ACC, B, PSW, SP, DPL, DPH
Enhanced CPU Core Registers: AUXC, DPL1, DPH1, INSCON, XPAGE
Power and Clock Control Registers: PCON, SUSLO, CLKL0, CLKRC0, CLKRC1
Flash Registers: IB_OFFSET, IB_DATA, IB_CON1, IB_CON2, IB_CON3, IB_CON4, IB_CON5
Data Memory Register: XPAGE
Hardware Watchdog Timer Registers: RSTSTAT
System Clock Control Register: CLKCON
Interrupt System Registers: IEN0, IEN1, IENC, IPH0, IPL0, IPH1, IPL1, EXF1
I/O Port Registers: P0, P1, P2, P3, P4, P5, P0CR, P1CR, P2CR, P3CR, P4CR, P5CR, P0PCR, P1PCR,
P2PCR, P3PCR, P4PCR, P5PCR, P1OS, P0SS, P1SS, P2SS
Timer Registers: TCON, T2CON, T2MOD, TH2, TL2, RCAP2L, RCAP2H, T3CON, TH3, TL3, T4CON,
TH4, TL4
EUART Registers: SCON, SBUF, SADEN, SADDR, PCON, SBRTL, SBRTH, BFINE
TONE Registers: TVCR1, TVCR2, TGCR11, TGCR12, TGCR21, TGCR22
TK Registers: TKCON1, TKF0, TKU1, TKU2, TKDIV01, TKDIV02, TKDIV03, TKDIV04, TKVREF,
TKST, TKRANDOM, TKCOUNT, TKW
LED Registers: DISPCON, SEG01, SEG02, DISPCLK, LEDCOM, DISCOM, LIGHTCOM
TWI Registers: TWIDAT, TWIADR, TWISTA, TWICON

SH79F1622
8
Table 6.1 CPU Core SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ACC E0H Accumulator 00000000 ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0
B F0H B Register 00000000 B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0
AUXC F1H C Register 00000000 C.7 C.6 C.5 C.4 C.3 C.2 C.1 C.0
PSW D0H Program Status Word 00000000 CY AC F0 RS1 RS0 OV F1 P
SP 81H Stack Pointer 00000111 SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0
DPL 82H Data Pointer Low byte 00000000 DPL0.7 DPL0.6 DPL0.5 DPL0.4 DPL0.3 DPL0.2 DPL0.1 DPL0.0
DPH 83H Data Pointer High byte 00000000 DPH0.7 DPH0.6 DPH0.5 DPH0.4 DPH0.3 DPH0.2 DPH0.1 DPH0.0
DPL1 84H Data Pointer 1 Low byte 00000000 DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0
DPH1 85H Data Pointer 1 High byte 00000000 DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0
INSCON 86H Data pointer select -0--00-0 - BKS0 - - DIV MUL - DPS
Table 6.2 Power and Clock control SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PCON 87H Power Control 00--0000 SMOD SSTAT - - GF1 GF0 PD IDL
SUSLO 8EH Suspend Mode Control 00000000 SUSLO.7 SUSLO.6 SUSLO.5 SUSLO.4 SUSLO.3 SUSLO.2 SUSLO.1 SUSLO.0

SH79F1622
9
Table 6.3 Flash control SFRs
Mnem Add Name
POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IB_OFF
SET FBH Low byte offset of flash memory for programming 00000000 IB_OFF SET.7 IB_OFF SET.6 IB_OFF SET.5 IB_OFF SET.4 IB_OFF SET.3 IB_OFF SET.2 IB_OFF SET.1 IB_OFF SET.0
IB_DATA FCH Data Register for programming
flash memory 00000000 IB_DATA.7 IB_DATA.6 IB_DATA.5 IB_DATA.4 IB_DATA.3 IB_DATA.2 IB_DATA.1 IB_DATA.0
IB_CON1 F2H Flash Memory Control Register 1 00000000 IB_CON1.7 IB_CON1.6 IB_CON1.5 IB_CON1.4 IB_CON1.3 IB_CON1.2 IB_CON1.1 IB_CON1.0
IB_CON2 F3H Flash Memory Control Register 2 ----0000 - - - - IB_CON2.3 IB_CON2.2 IB_CON2.1 IB_CON2.0
IB_CON3 F4H Flash Memory Control Register 3 ----0000 - - - - IB_CON3.3 IB_CON3.2 IB_CON3.1 IB_CON3.0
IB_CON4 F5H Flash Memory Control Register 4 ----0000 - - - - IB_CON4.3 IB_CON4.2 IB_CON4.1 IB_CON4.0
IB_CON5 F6H Flash Memory Control Register 5 ----0000 - - - - IB_CON5.3 IB_CON5.2 IB_CON5.1 IB_CON5.0
XPAGE F7H Memory Page 00000000 XPAGE.7 XPAGE.6 XPAGE.5 XPAGE.4 XPAGE.3 XPAGE.2 XPAGE.1 XPAGE.0
FLASHCON A7H Flash access control -------0 - - - - - - - FAC
Table 6.4 WDT SFR
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RSTSTAT B1H Watchdog Timer Control 0-000000* WDOF - PORF LVRF CLRF WDT.2 WDT.1 WDT.0
*Note: RSTSTAT initial value is determined by different RESET, refer to “Watchdog Timer (WDT)” section for details.

SH79F1622
10
Table 6.5 CLKCON SFR
Mnem Add Name POR/WDT/LVR
/PIN
Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CLKCON B2H System Clock Control Register 111-00-- 32k_SPDUP CLKS1 CLKS0 - OSC2ON FS - -
Table 6.6 Interrupt SFRs
Mnem Add Name POR/WDT/LVR
/PIN
Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
IEN0 A8H Interrupt Enable Control 0 0-00-000 EA - ET2 ES - EX1 TKIE EX0
IEN1 A9H Interrupt Enable Control 1 ---0000- - - - ET3 ETWI EX3 EX2 -
IENC BAH Interrupt 4channel enable control ----0000 - - - - EXS43 EXS42 EXS41 EXS40
IENC1 BBH Interrupt channel enable control 1 ------00 - - - - - - ESCM1 ELPD
IPH0 B4H Interrupt Priority Control High 0 -0000000 - PT4H PT2H PS0H PTKH PX1H PTWH PX0H
IPL0 B8H Interrupt Priority Control Low 0 -0000000 - PT4L PT2L PS0L PTKL PX1L PTWL PX0L
IPH1 B5H Interrupt Priority Control High 1 ---0-00- - - - PT3H - PX4H PX2H -
IPL1 B9H Interrupt Priority Control Low 1 ---0-00- - - - PT3L - PX4L PX2L -
EXF0 E8H External interrupt Control 0 00--0000 IT4.1 IT4.0 - - IT2.1 IT2.0 IE3 IE2
EXF1 D8H External interrupt Control 1 ----0000 - - - - IF43 IF42 IF41 IF40
EXCON0 ADH External interrupt sampling time
Control --000000 - - I2P1 I2P0 I1P1 I1P0 I0P1 I0P0
EXCON1 AEH External interrupt sampling time
Control 00000000 I43P1 I43P0 I42P1 I42P0 I41P1 I41P0 I40P1 I40P0

SH79F1622
11
Table 6.7 Port SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
P0 80H 8-bit Port 0 00000000 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
P1 90H 8-bit Port 1 00000000 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
P2 A0H 8-bit Port 2 00000000 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
P3 B0H 8-bit Port 3 -------0 - - - - - - - P3.0
P0CR E1H Port0 input/output direction control 00000000 P0CR.7 P0CR.6 P0CR.5 P0CR.4 P0CR.3 P0CR.2 P0CR.1 P0CR.0
P1CR E2H Port1 input/output direction control 00000000 P1CR.7 P1CR.6 P1CR.5 P1CR.4 P1CR.3 P1CR.2 P1CR.1 P1CR.0
P2CR E3H Port2 input/output direction control 00000000 P2CR.7 P2CR.6 P2CR.5 P2CR.4 P2CR.3 P2CR.2 P2CR.1 P2CR.0
P3CR E4H Port3 input/output direction control -------0 - - - - - - - P3CR.0
P0PCR E9H Internal pull-high enable for Port0 00000000 P0PCR.7 P0PCR.6 P0PCR.5 P0PCR.4 P0PCR.3 P0PCR.2 P0PCR.1 P0PCR.0
P1PCR EAH Internal pull-high enable for Port1 00000000 P1PCR.7 P1PCR.6 P1PCR.5 P1PCR.4 P1PCR.3 P1PCR.2 P1PCR.1 P1PCR.0
P2PCR EBH Internal pull-high enable for Port2 00000000 P2PCR.7 P2PCR.6 P2PCR.5 P2PCR.4 P2PCR.3 P2PCR.2 P2PCR.1 P2PCR.0
P3PCR ECH Internal pull-high enable for Port3 -------0 - - - - - - - P3PCR.0
P1OS EFH Output mode control -00----- - P1OS.6 P1OS.5 - - - - -
P0SS D9H Function mode control 00000000 P0SS.7 P0SS.6 P0SS.5 P0SS.4 P0SS.3 P0SS.2 P0SS.1 P0SS.0
P1SS DAH Function mode control ---0000- - - - P1SS.4 P1SS.3 P1SS.2 P1SS.1 -
P2SS DBH Function mode control 00000000 P2SS.7 P2SS.6 P2SS.5 P2SS.4 P2SS.3 P2SS.2 P2SS.1 P2SS.0

SH79F1622
12
Table 6.8 Timer SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TCON 88H Timer/Counter Control ----0000 - - - - IE1 IT1 IE0 IT0
T2CON C8H Timer/Counter 2 Control 00000000 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T
----2 ---- CP/R ----L ----2 ----
T2MOD C9H Timer/Counter 2 Mode 0-----00 TCLKP2 - - - - - T2OE DCEN
RCAP2L CAH Timer/Counter 2 Reload
/Caprure Low Byte 00000000 RCAP2L.7 RCAP2L.6 RCAP2L.5 RCAP2L.4 RCAP2L.3 RCAP2L.2 RCAP2L.1 RCAP2L.0
RCAP2H CBH Timer/Counter 2 Reload
/Caprure High Byte 00000000 RCAP2H.7 RCAP2H.6 RCAP2H.5 RCAP2H.4 RCAP2H.3 RCAP2H.2 RCAP2H.1 RCAP2H.0
TL2 CCH Timer/Counter 2 Low Byte 00000000 TL2.7 TL2.6 TL2.5 TL2.4 TL2.3 TL2.2 TL2.1 TL2.0
TH2 CDH Timer/Counter 2 High Byte 00000000 TH2.7 TH2.6 TH2.5 TH2.4 TH2.3 TH2.2 TH2.1 TH2.0
T3CON C0H Timer/Counter 3 Control 0-00-000 TF3 - T3PS.1 T3PS.0 - TR3 T3CLKS.1 T3CLKS.0
TL3 C4H Timer/Counter 3 Low Byte 00000000 TL3.7 TL3.6 TL3.5 TL3.4 TL3.3 TL3.2 TL3.1 TL3.0
TH3 C5H Timer/Counter 3 High Byte 00000000 TH3.7 TH3.6 TH3.5 TH3.4 TH3.3 TH3.2 TH3.1 TH3.0
T4CON C2H Timer/Counter 4 Control 00000000 TF4 TC4 T4PS1 T4PS0 T4M1 T4M0 TR4 T4CLKS
TL4 D6H Timer/Counter 4 Low Byte 00000000 TL4.7 TL4.6 TL4.5 TL4.4 TL4.3 TL4.2 TL4.1 TL4.0
TH4 D7H Timer/Counter 4 High Byte 00000000 TH4.7 TH4.6 TH4.5 TH4.4 TH4.3 TH4.2 TH4.1 TH4.0

SH79F1622
13
Table 6.9 EUART SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCON 98H Serial Control 00000000 SM0/FE SM1/RXOV SM2/TXCOL REN TB8 RB8 TI RI
SBUF 99H Serial Data Buffer 00000000 SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0
SADEN 9BH Slave Address Mask 00000000 SADEN.7 SADEN.6 SADEN.5 SADEN.4 SADEN.3 SADEN.2 SADEN.1 SADEN.0
SADDR 9AH Slave Address 00000000 SADDR.7 SADDR.6 SADDR.5 SADDR.4 SADDR.3 SADDR.2 SADDR.1 SADDR.0
PCON 87H Power & serial Control 00--0000 SMOD SSTAT - - GF1 GF0 PD IDL
SBRTH 9CH Baudrate generator 00000000 SBRTEN SBRT.14 SBRT.13 SBRT.12 SBRT.11 SBRT.10 SBRT.9 SBRT.8
SBRTL 9DH Baudrate generator 00000000 SBRT.7 SBRT.6 SBRT.5 SBRT.4 SBRT.3 SBRT.2 SBRT.1 SBRT.0
SFINE 9EH Baudrate generator ----0000 - - - - SFINE.3 SFINE.2 SFINE.1 SFINE.0
Table 6.10 TONE SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TVCR1 CFH Tone generator 1 volume Control 00000000 TG1EN TV1.6 TV1.5 TV1.4 TV1.3 TV1.2 TV1.1 TV1.0
TVCR2 D1H Tone generator 2 volume Control 00000000 TG2EN TV2.6 TV2.5 TV2.4 TV2.3 TV2.2 TV2.1 TV2.0
TGCR11 D2H Tone generator 1 00000000 TG1.7 TG1.6 TG1.5 TG1.4 TG1.3 TG1.2 TG1.1 TG1.0
TGCR12 D3H Tone generator 1 00000000 TG1.15 TG1.14 TG1.13 TG1.12 TG1.11 TG1.10 TG1.9 TG1.8
TGCR21 D4H Tone generator 2 00000000 TG2.7 TG2.6 TG2.5 TG2.4 TG2.3 TG2.2 TG2.1 TG2.0
TGCR22 D5H Tone generator 2 00000000 TG2.15 TG2.14 TG2.13 TG2.12 TG2.11 TG2.10 TG2.9 TG2.8

SH79F1622
14
Table 6.11 TK SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TKCON1 A1H Touch Key Control 0-000000 TKCON - TKGO/
D
----
O
----
N
----
E
----
SHARE MODE OVDD FSW1 FSW0
TKF0 A2H Touch Key interrupt flag Register -00000-- - IFERR IFGO IFAVE IFCOUNT IFTKOV - -
TKU1 A4H Touch Key channel selection
Register 00000000 TK8 TK7 TK6 TK5 TK4 TK3 TK2 TK1
TKU2 A5H Touch Key channel choosing
Register 00000000 TK16 TK15 TK14 TK13 TK12 TK11 TK10 TK9
TKU3 A6H Touch Key channel choosing
Register ----0000 - - - - TK20 TK19 TK18 TK17
TKDIV01 91H Touch Key amplification
coefficient Register 00000000 DIV7 DIV6 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0
TKDIV02 92H Touch Key amplification
coefficient Register 00000000 DIV15 DIV14 DIV13 DIV12 DIV11 DIV10 DIV9 DIV8
TKDIV03 93H Touch Key amplification
coefficient Register 00000000 DIV23 DIV22 DIV21 DIV20 DIV19 DIV18 DIV17 DIV16
TKDIV04 94H Touch Key amplification
coefficient Register ----0000 - - - - DIV27 DIV26 DIV25 DIV24
TKVREF 95H Reference voltage source
selection Register 00000000 VREF1 VREF0 CMPD1 CMPD0 VTK1 VTK0 TUNE1 TUNE0
TKST A3H Touch Key frequency
selection Register -0000000 - ST.6 ST.5 ST.4 ST.3 ST.2 ST.1 ST.0
TKRANDO
M 96H Touch Key frequency selection Register 0000--00 TKRADON TKOFFSET TKVDD TKOUT - - RANDOM1 RANDOM1
TKCOUNT 97H Touch Key clock width
selection Register 00000000 COUNT0.7 COUNT0.6 COUNT0.5 COUNT0.4 COUNT0.3 COUNT0.2 COUNT0.1 COUNT0.0
TKW BDH Touch Key channel error
display Register ---00000 - - - TW.4 TW.3 TW.2 TW.1 TW.0

SH79F1622
15
Table 6.12 LED SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DISPCON 89H LED Control -0----00 - LEDON - - - - DUTY1 DUTY0
SEG01 8AH SEG function selection Register 00000000 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0
SEG02 8BH SEG function selection Register 00000000 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8
DISPCLK 8CH LED clock frequency
selection Register 00000000 DCK0.7 DCK0.6 DCK0.5 DCK0.4 DCK0.3 DCK0.2 DCK0.1 DCK0.0
LEDCOM 8FH COM function selection Register -0000000 - COM7 COM6 COM5 COM4 COM3 COM2 COM1
DISCOM 9FH LED COM sweep length Register 00000000 DCOM.7 DCOM.6 DCOM.5 DCOM.4 DCOM.3 DCOM.2 DCOM.1 DCOM.0
LIGHTCOM
8DH LED COM brightness
selection Register -----000 - - - - - CC3 CC2 CC1
Table 6.13 TWI SFRs
Mnem Add Name POR/WDT/LVR
/PIN Reset Value
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TWICON F8H TWI setting Register 00000000 TOUT ENTWI STA STO TWINT AA TFREE EFREE
TWISTA E6H TWI state Register 11111000 TWISTA.7 TWISTA.6 TWISTA.5 TWISTA.4 TWISTA.3 CR.1 CR.0 ETOT
TWIADR E7H TWI data address Register 00000000 TWA.6 TWA.5 TWA.4 TWA.3 TWA.2 TWA.1 TWA.0 GC
TWIDAT DFH TWI data input/output Register 00000000 TWIDAT.7 TWIDAT.6 TWIDAT.5 TWIDAT.4 TWIDAT.3 TWIDAT.2 TWIDAT.1 TWIDAT.0

SH79F1622
16
SFR Map
Bank0
Bit
addressable
Non Bit addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8H TWICON IB_OFFSET IB_DATA FFH
F0H B AUXC IB_CON1 IB_CON2 IB_CON3 IB_CON4 IB_CON5 XPAGE F7H
E8H EXF0 P0PCR P1PCR P2PCR P3PCR P1OS EFH
E0H ACC P0CR P1CR P2CR P3CR TWISTA TWIADR E7H
D8H EXF1 P0SS P1SS P2SS TWIDAT DFH
D0H PSW TVCR2 TGCR11 TGCR12 TGCR21 TGCR22 TL4 TH4 D7H
C8H T2CON T2MOD RCAP2L RCAP2H TL2 TH2 TVCR1 CFH
C0H T3CON T4CON TL3 TH3 C7H
B8H IPL0 IPL1 IENC IENC1 TKW BFH
B0H P3 RSTSTAT CLKCON IPH0 IPH1 B7H
A8H IEN0 IEN1 EXCON0 EXCON1 AFH
A0H P2 TKCON1 TKF0 TKST TKU1 TKU2 TKU3 FLASHCON A7H
98H SCON SBUF SADDR SADEN SBRTH SBRTL SFINE DISCOM 9FH
90H P1 TKDIV01 TKDIV02 TKDIV03 TKDIV04 TKVREF TKRANDOM TKCOUNT 97H
88H TCON DISPCON SEG01 SEG02 DISPCLK LIGHTCOM SUSLO LEDCOM 8FH
80H P0 SP DPL DPH DPL1 DPH1 INSCON PCON 87H
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

SH79F1622
17
7. Normal Function
7.1 CPU
7.1.1 CPU Core SFR
Feature
CPU core registers: ACC, B, PSW, SP, DPL, DPH
Accumulator
ACC is the Accumulator register. Instruction system adopts A as mnemonic symbol of accumulator.
B Register
The B register is used during multiply and divide operations. For other instructions it can be treated as another scratch pad
register.
Stack Pointer (SP)
The Stack Pointer Register is 8 bits special register, It is incremented before data is stored during PUSH, CALL executions and
interrupt response. And it is decremented after data is out of stack during POP, RET, RETI executions. The stack may reside
anywhere in on-chip internal RAM (00H-FFH). On reset, the Stack Pointer is initialized to 07H causing the stack to begin at
location 08H.
Program Status Word Register (PSW)
The PSW register contains program status information.
Data Pointer Register (DPTR)
DPTR consists of a high byte (DPH) and a low byte (DPL). Its intended function is to hold a 16-bit address, but it may be
manipulated as a 16-bit register or as two independent 8-bit registers.
Table 7.1 PSW Register
D0H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PSW CY AC F0 RS1 RS0 OV F1 P
R/W R/W R/W R/W R/W R/W R/W R/W R
Reset Value
(POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0
Bit Number Bit Mnemonic Description
7 CY Carry flag bit
0: no carry or borrow in an arithmetic or logic operation
1: a carry or borrow in an arithmetic or logic operation
6 AC Auxiliary Carry flag bit
0: no auxiliary carry or borrow in an arithmetic or logic operation
1: an auxiliary carry or borrow in an arithmetic or logic operation
5 F0 F0 flag bit
Available to the user for general purposes
4-3 RS[1:0]
R0-R7 Register bank select bits
00: Bank0 (Address to 00H-07H)
01: Bank1 (Address to 08H-0FH)
10: Bank2 (Address to 10H-17H)
11: Bank3 (Address to 18H-1FH)
2 OV Overflow flag bit
0: no overflow happen
1: an overflow happen
1 F1 F1 flag bit
Available to the user for general purposes
0 P Parity flag bit
0: In the Accumulator,the bits whose value is 1 is even number
1: In the Accumulator,the bits whose value is 1 is odd number

SH79F1622
18
7.1.2 Enhanced CPU core SFRs
Extended 'MUL' and 'DIV' instructions: 16bit*8bit, 16bit/8bit
Dual Data Pointer
Enhanced CPU core registers: AUXC, DPL1, DPH1, INSCON
The SH79F1622 has modified 'MUL' and 'DIV' instructions. These instructions support 16 bit operand. A new register - the
register AUXC is applied to hold the upper part of the operand/result.
The AUXC register is used during 16 bit operand multiply and divide operations. For other instructions it can be treated as
another scratch pad register.
After reset, the CPU is in standard mode, which means that the 'MUL' and 'DIV' instructions are operating like the standard
8051 instructions. To enable the 16 bit mode operation, the corresponding enable bit in the INSCON register must be set.
Operation
Result
A
B
AUXC
MUL INSCON.2 = 0; 8 bit mode (A)*(B) Low Byte High Byte ---
INSCON.2 = 1; 16 bit mode (AUXC A)*(B) Low Byte Middle Byte High Byte
DIV INSCON.3 = 0; 8 bit mode (A)/(B) Quotient Low Byte Remainder ---
INSCON.3 = 1; 16 bit mode (AUXC A)/(B) Quotient Low Byte Remainder Quotient High Byte
Dual Data Pointer
Using two data pointers can accelerate data memory moves. The standard data pointer is called DPTR and the new data
pointer is called DPTR1.
DPTR1 is similar to DPTR, which consists of a high byte (DPH1) and a low byte (DPL1). Its intended function is to hold a 16-bit
address, but it may be manipulated as a 16-bit register or as two independent 8-bit registers.
The DPS bit in INSTCON register is used to choose the active pointer by setting 1 or 0. And all DPTR-related instructions will
use the currently selected data pointer.
7.1.3 Register
Table 7.2 Data Pointer Select Register
86H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
INSCON - - - - DIV MUL - DPS
R/W - - - - R/W R/W - R/W
Reset Value
(POR/WDT/LVR/PIN) - - - - 0 0 - 0
Bit Number Bit Mnemonic Description
3 DIV 16 bit/8 bit Divide Selection Bit
0: 8 bit Divide
1: 16 bit Divide
2 MUL 16 bit/8 bit Multiply Selection Bit
0: 8 bit Multiply
1: 16 bit Multiply
0 DPS Data Pointer Selection Bit
0: Data pointer
1: Data pointer1

SH79F1622
19
7.2 RAM
7.2.1 Features
SH79F1622 provides both internal RAM and external RAM for random data storage. The internal data memory is mapped into
four separated segments:
The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable
The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only
The Special Function Registers (SFR, addresses 80H to FFH) are directly addressable only
External RAM are indirectly accessed by MOVX instructions
The Upper 128 bytes occupy the same address space as SFR, but they are physically separate from SFR space. When an
instruction accesses an internal location above address 7FH, the CPU can distinguish whether to access the upper 128 bytes
data RAM or to access SFR by different addressing mode of the instruction.
SH79F1622 provides 1280 bytes RAM in external data space for supporting high-level language. SH79F1622 also configures
14 bytes LED RAM (530H - 53DH).
7FH
80H
0FFH
00H 00H
Upper
128 bytes
Internal
Ram
indirect accesses
Lower
128 bytes
Internal
Ram
direct or indirect
accesses
500H
SFR
direct accesses
80H
0FFH
EXRENAL
RAM
LED RAM
TOUCH DATA
528H
53DH
530H
The Internal and External RAM Configuration
The SH79F1622 provides traditional method for accessing of external RAM. Use MOVXA, @Ri or MOVX @Ri, A; to access
external low 256 bytes RAM; MOVX A, @DPTR or MOVX @DPTR, A also to access external 1280 bytes RAM.

SH79F1622
20
7.3 Flash Program Memory
7.3.1 Features
The program memory consists 16 X 1KB sectors, total 16KB
8 X 256 Bytes EEPROM-Like Built-in, total 2KB
Programming and erase can be done over the full operation voltage range
Supports 4 kinds of code protection
Write, read and erase operation are all supported by In-Circuit Programming (ICP)
Support overall/sector erase and programming
Minimum program/erase cycles:
Main program memory: 10,000
EEPROM like memory: 100,000
Minimum years data retention: 10
Low power consumption
EEPROM Like Data Block Program Memory Block
0000H
0000H
Information Block
07FFH
FFFFH
Program Memory Block
Reserved
3FFFH
The SH79F1622 embeds 16K flash program memory for program code. The flash program memory supports In-Circuit Progra-
mming (ICP) mode and Self-Sector Programming (SSP) mode. Every sector is 1024 bytes.
The SH79F1622 also embeds 2048 bytes EEPROM-like memory block for storing user data. Every sector is 256 bytes.It has 8
sectors.
Flash operation definition:
In-Circuit Programming(ICP): Through the Flash programmer to wipe the Flash memory, read and write operations.
Self-Sector Programming (SSP): User Program code run in Program Memory to wipe the Flash memory(including Flash
program memory and EEPROM like memory), read and write operations.But it can’t erase the sector which contains the code
itself.
Flash memory supports the following operations:
(1) Code-Protect Control mode Programming
SH79F1622 code protection function provides a high-performance security measures for the user. Each partition has four
modes are available.
Code-protect control mode 0: Used to enable/disable the write/read operation (except mass erase) from any programmer.
4K (4 sectors) as a unit which can be protected separately.
Code-protect control mode 1: Used to enable/disable the read operation through MOVC instruction from other sectors; or
the sector erase/write operation through SSP Function. 4K (4 sectors) as a unit which can be protected separately.
Code-protect control mode 2: Used to enable/disable the erase/write EEPROM operation through SSP Function.
Code-protect control mode 3: Customer password, write by customer, consists of 6 bytes. To enable the wanted protect
mode, the user must use the Flash Programmer to set the corresponding protect bit.
The user must use the following two ways to complete code protection control mode Settings:
1. Flash programmer in ICP mode is set to corresponding protection bit to enter the protected mode.
2. The SSP mode does not support code protection control mode programming.