ST STM32U5 User manual

Introduction
This application note is intended for system designers who require a hardware implementation overview of the development
board features: power supply, clock management, reset control, boot mode settings, and debug management.
It details how to use the STM32U5 series microcontrollers (named STM32U5) and describes the minimum hardware resources
required to develop an application using these MCUs.
This document also includes detailed reference design schematics with the description of the main components, interfaces, and
modes.
Getting started with STM32U5 MCU hardware development
AN5373
Application note
AN5373 - Rev 6 - September 2023
For further information contact your local STMicroelectronics sales office.
www.st.com

1 General information
This document applies to the STM32U5 series Arm® Cortex®‑M33‑based microcontrollers.
Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Reference documents
[1] Reference manual STM32U5 series Arm®-based 32-bit MCUs (RM0456)
[2] Application note STM32 microcontroller system memory boot mode (AN2606)
[3] Application note Oscillator design guide for STM8AF/AL/S, STM32 MCUs and MPUs (AN2867)
[4] Application note STM32 MCUs secure firmware install (SFI) overview (AN4992)
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General information
AN5373 - Rev 6 page 2/47

2 Power supply management
2.1 Power supplies
The STM32U5 devices require a 1.71 to 3.6 V operating voltage supply (VDD).
The independent supplies listed below, can be provided for specific peripherals:
•VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the internal regulator, and the system analog such as reset,
power management, and internal clocks. VDD is provided externally through the VDD pins.
•VDDA = 1.62 V (ADCs/COMPs/DACs/OPAMPs) / 1.8 V (VREFBUF) to 3.6 V
VDDA is the external-analog power supply for A/D converters, D/A converters, voltage reference buffer,
operational amplifiers, and comparators. The VDDA voltage level is independent from the VDD voltage. The
VDDA pin must preferably be connected to the VDD voltage supply when these peripherals are not used.
Note: In case the VDDA pin is left at high impedance or is tied to VSS, the maximum input voltage that can be
applied on the I/Os with "_a" I/O structure, is reduced (refer to device datasheet for more details).
•VDDSMPS = 1.71 V to 3.6 V
VDDSMPS is the external power supply for the SMPS step-down converter. It is provided externally through
the VDDSMPS pin, and must be connected to the same supply as VDD pin when the SMPS is used in the
application. When the SMPS is not used, it is recommended to connect both VDDSMPS and VLXSMPS to
ground.
•VLXSMPS
The VLXSMPS pin is the switched SMPS step-down converter output.
Note: The SMPS output can not be used to power external components.
•VDD11
VDD11 is a digital core supply provided through the internal SMPS step-down converter VLXSMPS pin.
VDD11 pins (two or three) are present only on packages with internal SMPS, connected to a total of 4.7 µF
(typical) external capacitors.
•VCAP
VCAP is the digital core supply, from the internal LDO regulator. VCAP pins (one or two) are present only on
packages with LDO only (without SMPS), connected to a total of 4.7 µF (typical) external capacitor.
Note: – In case there are two VCAP pins (UFBGA169 package), each pin must be connected to a 2.2 µF
capacitor, for a total around 4.4 µF.
– The SMPS power supply pins (VLXSMPS, VDD11, VDDSMPS, VSSSMPS) are available only on
packages with SMPS. In such packages, the STM32U5 devices embed two regulators, one LDO
and one SMPS in parallel, to provide the VCORE supply to digital peripherals. A 4.7 μF total external
capacitor and a 2.2 µH coil are required on VDD11 pins.
– The flash memory is supplied by VCORE and VDD.
•VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external-independent power supply for USB transceivers. The VDDUSB voltage level is
independent from the VDD voltage. The VDDUSB pin must preferably be connected to the VDD voltage
supply when the USB is not used.
Note: In case the VDDUSB pin is left at high impedance or is tied to VSS, the maximum input voltage that can
be applied on the I/Os with "_u" I/O structure, is reduced (refer to device datasheet for more details).
•VDD11USB = 1.0 V to 1.26 V (only available on STM32U59x/5Ax/5Fx/5Gx devices)
VDD11USB is the external power supply for the USB transceiver. This supply is only available on specific
packages and must be connected to VDD11.
•VDDIO2 = 1.08 V to 3.6 V
VDDIO2 is the external power supply for 14 I/Os (port G[15:2]). The VDDIO2 voltage level is independent
from the VDD voltage, and must preferably be connected to VDD when PG[15:2] is not used.
Note: On small packages, VDDA, VDDIO2, or VDDUSB independent power supplies may not be present as a
dedicated pin, and are internally bonded to a VDD pin. They are neither present when the related features
are not supported on the product.
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Power supply management
AN5373 - Rev 6 page 3/47

•VBAT = 1.55 V to 3.6 V
VBAT is the power supply when VDD is not present (through power switch) for RTC, TAMP, external clock
32 kHz oscillator, backup registers, and optionally backup SRAM.
•VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage
reference buffer (VREFBUF) when enabled. The VREF+ pin can be grounded when ADC and DAC are not
active.
The internal voltage reference buffer supports four output voltages that are configured with the VRS[2:0]
field in VREFBUF_CSR register:
– VREF+ around 1.5 V. This requires VDDA ≥ 1.8 V.
– VREF+ around 1.8 V. This requires VDDA ≥ 2.1 V.
– VREF+ around 2.048 V. This requires VDDA ≥ 2.4 V.
– VREF+ around 2.5 V. This requires VDDA ≥ 2.8 V.
VREF- and VREF+ pins are not available on all packages. When not available, they are bonded to VSSA
and VDDA pins, respectively.
When the VREF+ pin is double-bonded to VDDA in a package, the internal VREFBUF is not available, and
must be kept disabled.
VREF- must always be equal to VSSA.
•VDDDSI = 1.71 V to 3.6 V (only available on STM32U59x/5Ax/5Fx/5Gx devices)
VDDDSI is the external power supply for the DSI controller. It is provided externally through the VDDDSI
supply pin, and must be connected to the same supply as VDD pin.
•VDD11DSI = 1.0 V to 1.26 V (only available on STM32U59x/5Ax/5Fx/5Gx devices)
VDD11DSI is the external power supply for the DSI transceiver and must be connected to VDD11.
The following figures present an overview of the STM32U5 devices power supply, depending on the SMPS
presence.
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Power supplies
AN5373 - Rev 6 page 4/47

Figure 1. STM32U535xxxxQ and STM32U545xxxxQ power supply overview (with SMPS)
DT70511V2
USB transceiver
Core
SRAM1
SRAM2
SRAM4
Digital
peripherals
LSE crystal 32 kHz oscillator
LSI 32 kHz oscillator
Backup registers
RCC_BDCR and PWR_BDCR1 registers
RTC
TAMP
BKPSRAM
VDDA domain
Backup domain
Standby circuitry
(Wake-up logic, IWDG)
LDO regulator
Low-voltage detector
I/O ring
VCORE domain
Flash memory
VDDUSB
VDDIO2
VDDIO1
I/O ring
PG[15:2]
VDDIO2
VDDA
VSSA
VSS
VSS
VDDIO2 domain
VDD domain
VCORE
VSS
VDD
VBAT
2x VDD11
SMPS regulator
Voltage regulator
VLXSMPS
VDDSMPS
VSSSMPS
A/D converters
Comparators
D/A converters
Operational amplifiers
Voltage reference buffer
Temperature sensor
Reset block
3 x PLL
Internal RC oscillators
VSW
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Figure 2. STM32U535xx and STM32U545xx power supply overview (without SMPS)
DT70512V2
USB transceiver
Core
SRAM1
SRAM2
SRAM4
Digital
peripherals
VDDA domain
Standby circuitry
(Wake-up logic, IWDG)
Low-voltage detector
LDO regulator
I/O ring VCORE domain
Flash memory
VDDIO2
VDDIO1
I/O ring
PG[15:2]
VDDIO2
VDDA
VSSA
VSS
VSS
VDDIO2 domain
VDD domain
VCORE
VSS
VDD
VBAT
A/D converters
Comparators
D/A converters
Operational amplifiers
Voltage reference buffer
Temperature sensor
Reset block
3 x PLL
Internal RC oscillators
LSE crystal 32 kHz oscillator
LSI 32 kHz oscillator
Backup registers
RCC_BDCR and PWR_BDCR1 registers
RTC
TAMP
BKPSRAM
Backup domain
VSW
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Power supplies
AN5373 - Rev 6 page 6/47

Figure 3. STM32U575xQ and STM32U585xQ power supply overview (with SMPS)
DT63604V2
USB transceiver
Core
SRAM1
SRAM2
SRAM3
SRAM4
Digital
peripherals
VDDA domain
Backup domain
Standby circuitry
(Wake-up logic, IWDG)
LDO regulator
Low-voltage detector
I/O ring
VCORE domain
Temperature sensor
Reset block
3 x PLL
Internal RC oscillators
Flash memory
VDDUSB
VDDIO2
VDDIO1
I/O ring
PG[15:2]
VDDIO2
VDDA
VSSA
VSS
VSS
VDDIO2 domain
VDD domain
VCORE
VSS
VDD
VBAT
2x VDD11
SMPS regulator
Voltage regulator
VLXSMPS
VDDSMPS
VSSSMPS
2 x A/D converters
2 x comparators
2 x D/A converters
2 x operational amplifiers
Voltage reference buffer
VSW LSE crystal 32kHz oscillator
Backup registers
RCC_BDCR register
RTC
TAMP
BKPSRAM
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Figure 4. STM32U575xx and STM32U585xx power supply overview (without SMPS)
DT64350V2
USB transceiver
Core
SRAM1
SRAM2
SRAM3
SRAM4
Digital
peripherals
LSE crystal 32kHz oscillator
Backup registers
RCC_BDCR register
RTC
TAMP
BKPSRAM
VDDA domain
Backup domain
Standby circuitry
(Wake-up logic, IWDG)
Low-voltage detector
I/O ring VCORE domain
Temperature sensor
Reset block
3 x PLL
Internal RC oscillators
Flash memory
VDDUSB
VDDIO2
VDDIO1
I/O ring
PG[15:2]
VDDIO2
VDDA
VSSA
VSS
VSS
VDDIO2 domain
VDD domain
VCORE
VSS
VDD
VBAT
VCAP
2 x A/D converters
2 x comparators
2 x D/A converters
2 x operational amplifiers
Voltage reference buffer
LDO regulator
VSW
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Figure 5. STM32U5F/5G/59/5AxxxxxQ power supply overview (with SMPS)
DT70551V2
(1) Only available on specific packages.
(2) Only for STM32U5Fx/5Gx devices.
Core
SRAM1
SRAM2
SRAM3
SRAM4
SRAM5
SRAM6(2)
Digital
peripherals
LSE crystal 32kHz oscillator
Backup registers
RCC_BDCR register
RTC
TAMP
BKPSRAM
VDDA domain
Backup domain
Standby circuitry
(Wake-up logic, IWDG)
LDO regulator
Low-voltage detector
I/O ring
VCORE domain
Temperature sensor
Reset block
3 x PLL
Internal RC oscillators
Flash memory
VDDUSB
VDDIO2
VDDIO1
I/O ring
PG[15:2]
VDDIO2
VDDA
VSSA
VDD11USB(1)
VSS
VDDIO2 domain
VDD domain
VCORE
VSS
VDD
VBAT
2x or 3x VDD11
SMPS regulator
Voltage regulator
VLXSMPS
VDDSMPS
VSSSMPS
A/D converters
Comparators
D/A converters
Operational amplifiers
Voltage reference buffer
VDDDSI
VDD11DSI
USB transceiver
VSS
VSS
DSI transceiver
VSW
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Figure 6. STM32U5F/5G/59/5Axxx power supply overview (without SMPS)
DT66058V2
Core
SRAM1
SRAM2
SRAM3
SRAM4
SRAM5
SRAM6(2)
Digital
peripherals
LSE crystal 32kHz oscillator
LSI 32 kHz oscillator
Backup registers
RCC_BDCR and PWR_BDCR1 registers
RTC
TAMP
BKPSRAM
VDDA domain
Backup domain
Standby circuitry
(Wake-up logic, IWDG)
Low-voltage detector
I/O ring
VCORE domain
Temperature sensor
Reset block
3 x PLL
Internal RC oscillators
Flash memory
VDDUSB
VDDIO2
VDDIO1
I/O ring
PG[15:2]
VDDIO2
VDDA
VSSA
VDD11USB(1)
VSS
VDDIO2 domain
VDD domain
VCORE
VSS
VDD
VBAT
VCAP
A/D converters
Comparators
D/A converters
Operational amplifiers
Voltage reference buffer
USB transceiver
VSS
(1) Only available on specific packages.
(2) Only for STM32U5Fx/5Gx devices.
LDO regulator
VSW
In devices without SMPS, the VDD supply source feeds the I/Os and system analog peripherals (such as PLLs
and reset block). The VCORE power supply for digital peripherals and memories is generated from the LDO.
Note: If the selected package has the SMPS step-down converter option but the SMPS is not used by the application
(and the embedded LDO is used instead), the SMPS power supply pins must be set as follows:
• VDDSMPS and VLXSMPS connected to VSS
• VDD11 pins connected to VSS through two 2.2 µF capacitors as in normal mode
2.1.1 Independent analog peripherals supply
To improve ADC and DAC conversion accuracy and to extend the supply flexibility, the analog peripherals have
an independent power supply that can be separately filtered and shielded from noise on the PCB.
The voltage supply input of the analog peripherals is available on a separate VDDA pin. An isolated supply
ground connection is provided on VSSA pin.
The VDDA supply voltage can be different from VDD. After reset, the analog peripherals supplied by VDDA are
logically and electrically isolated and therefore are not available. The isolation must be removed before using
these peripherals, by setting the ASV bit in PWR_SVMCR, once the VDDA supply is present.
The VDDA supply can be monitored by analog voltage monitors (AVM), and compared with two thresholds
(1.6 V for AVM1 or 1.8 V for AVM2). For more details, refer to the device datasheet and section Peripheral voltage
monitoring (PVM) of document [1].
When a single supply is used, the VDDA pin can be externally connected to the same VDD supply, through an
external filtering circuit, to ensure a noise-free VDD reference voltage.
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ADC and DAC reference voltage
To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to VREF+ pin, a separate
reference voltage lower than VDDA.
VREF+ is the highest voltage, represented by the full-scale value, for an analog input (ADC) or output (DAC)
signal. VREF+ can be provided either by an external reference or by the VREFBUF that can output a configurable
voltage: 1.5, 1.8, 2.048 or 2.5 V. The VREFBUF can also provide the voltage to external components through the
VREF+ pin.
For further information, refer to the device datasheet and section Voltage reference buffer (VREFBUF) of
document [1].
2.1.2 Independent I/O supply rail
Some I/Os from port G (PG[15:2]) are supplied from a separate supply rail. The power supply for this rail can
range from 1.08 V to 3.6 V, and is provided externally through the VDDIO2 pin. The VDDIO2 voltage level is
completely independent from VDD or VDDA.
The VDDIO2 pin is available only for some packages (refer to the pinout details in the datasheet for the I/O list).
After reset, the I/Os supplied by VDDIO2 are logically and electrically isolated and are therefore not available.
The isolation must be removed before using any I/O from PG[15:2], by setting the IO2SV bit in PWR_SVMR, once
the VDDIO2 supply is present.
The VDDIO2 supply is monitored by the VDDIO2 voltage monitoring (IO2VM) and compared with the internal
reference voltage (3/4 VREFINT, around 0.9 V).
For more details, refer to the device datasheet and section Peripheral voltage monitoring (PVM) of document [1].
2.1.3 Independent USB transceiver supply
The USB transceivers are supplied from a separate VDDUSB power supply. VDDUSB range is from 3.0 V to 3.6 V
and is completely independent from VDD or VDDA.
After reset, the USB features supplied by VDDUSB are logically and electrically isolated, and are therefore not
available. The isolation must be removed before using the USB OTG peripheral, by setting the USV bit in the
PWR_SVMR register, once the VDDUSB supply is present.
The VDDUSB supply is monitored by the USB voltage monitoring (UVM) and compared with the internal reference
voltage (VREFINT, around 1.2 V). For more details, refer to the device datasheet and section Peripheral voltage
monitoring (PVM) of document [1].
For STM32U59x/5Ax/5Fx/5Gx devices only, the USB high-speed transceiver can be supplied from an optional
power supply VDD11USB. VDD11USB range is from 1.0 V to 1.26 V and must be connected to VDD11.
2.1.4 Battery backup domain
To retain the content of the backup registers and supply the RTC when VDD is turned off, the VBAT pin can be
connected to an optional backup voltage, supplied by a battery or by another source.
The VBAT pin powers RTC, TAMP, LSE oscillator, and PC13 to PC15 I/Os. That allows the RTC to operate even
when the main power supply is turned off.
The backup SRAM is optionally powered through the VBAT pin, when the BREN bit is set in PWR_BDCR1.
The switch to the VBAT supply is controlled by the power-down reset embedded in the reset block.
Caution: • During tRSTTEMPO (at VDD startup) or after a PDR (power-down reset) detection, the power switch
between VBAT and VDD remains connected to the VBAT pin.
• During the startup phase, if VDD is established in less than tRSTTEMPO (refer to the datasheet for
tRSTTEMPO value), and VDD > VBAT + 0.6 V, a current may be injected into the VBAT pin through an
internal diode connected between the VDD pin and the power switch (VBAT). If the power supply/battery
connected to the VBAT pin cannot support this current injection, it is strongly recommended to connect an
external low-drop diode between this power supply and the VBAT pin.
If no external battery is used in the application, it is recommended to connect the VBAT pin externally to VDD with
a 100 nF external ceramic decoupling capacitor.
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When the backup domain is supplied by VDD (analog switch connected to the VDD pin), the following pins are
available:
• PC13, PC14, and PC15 that can be used as GPIO pins
• PC13, PC14, and PC15 that can be configured by RTC or LSE (refer to the RTC section of document [1])
• Pins listed below, that are configured by TAMP as tamper pins:
– PE3 (TAMP_IN6/TAMP_OUT3)
– PE4 (TAMP_IN7/TAMP_OUT8)
– PE5 (TAMP_IN8/TAMP_OUT7)
– PE6 (TAMP_IN3/TAMP_OUT6)
– PC13 (TAMP_IN1/TAMP_OUT2)
– PA0 (TAMP_IN2/TAMP_OUT1)
– PA1 (TAMP_IN5/TAMP_OUT4)
– PC5 (TAMP_IN4/TAMP_OUT5)
Note: • Because the power switch can transfer only a limited amount of current (3 mA), the use of PC13 to PC15
I/Os in output mode is restricted: the speed must be limited to 2 MHz with a maximum load of 30 pF.
These I/Os must not be used as current source (for example to drive an LED).
• Under VDD, TAMP_OUTx pins (PE3, PE4, PE5, PE6, PA0, PA1, PC5) keep the same speed features as
the GPIOs to which they are connected. However, under VBAT, the speed of TAMP_OUTx pins must be
limited to 500 kHz.
• The speed of the PC13 pin is always limited to 2 MHz, under VDD or under VBAT.
Backup domain access
After a system reset, the backup domain (RCC_BDCR, PWR_BDCR1, RTC, TAMP and backup registers, plus
backup SRAM) is protected against possible unwanted write accesses. To enable access to the backup domain,
proceed as follows:
1. Enable the power interface clock by setting the PWREN bit RCC_AHB3ENR.
2. Set the DBP bit in PWR_DBPR to enable access to the backup domain.
VBAT battery charging
When VDD is present, the external battery can be charged on VBAT through an internal resistance, 5 kΩ, or
1.5 kΩ, depending on the VBRS bit in PWR_BDCR2.
The battery charging is enabled by setting VBE bit in PWR_BDCR2. It is automatically disabled in VBAT mode.
2.1.5 Voltage regulator
The STM32U5 devices embed the following internal regulators in parallel to provide the VCORE supply for digital
peripherals, SRAMs, and the embedded flash memory:
• SMPS step-down converter
• LDO (linear voltage regulator)
They can be selected when the application runs, depending on the application requirements. The SMPS allows
the power consumption to be reduced. However, the noise generated by the SMPS may impact some peripheral
behaviors, requiring the application to switch to LDO when running the peripheral, in order to reach the best
performances.
Except for Standby circuitries and the Backup domain, LDO or SMPS can be used in all voltage scaling ranges
(range 1/2/3/4), in all Stop modes (Stop 0/1/2/3), and in Standby mode with SRAM2. Refer to the low-power mode
summary table in document [1].
On some packages, the SMPS supply pins are not available, consequently only the LDO might be used to supply
VCORE domain.
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Dynamic Voltage scaling management
Both LDO and SMPS regulators can provide four different voltages (voltage scaling) and can operate in all Stop
modes. Both regulators also can operate in the following ranges:
•Range 1 (1.2 V, 160 MHz), high performance: provides a typical output voltage at 1.2 V. It is used when the
system clock frequency is up to 160 MHz.
•Range 2 (1.1 V, 110 MHz), medium-high performance: provides a typical output voltage at 1.1 V. It is used
when the system clock frequency is up to 110 MHz.
•Range 3 (1.0 V, 55 MHz), medium-low power: provides a typical output voltage at 1.0 V. It is used when the
system clock frequency is up to 55 MHz.
•Range 4 (0.9 V, 24 MHz), low power: provides a typical output voltage at 0.9 V. It is is used when the
system clock frequency is up to 24 MHz.
Voltage scaling is selected through the VOS[1:0] field in PWR_VOSR.
Caution: The EPOD (embedded power distribution) booster must be enabled and ready before increasing the system
clock frequency above 50 MHz in Range 1 and Range 2 (refer to document [1] for sequences to switch between
voltage scaling ranges).
2.1.6 Power supply for I/O analog switches
Some I/Os embed analog switches for both analog peripherals (ADCs, COMPs, DACs) and TSC (touch sensing
controller) functions. These switches are by default supplied by VDDA. However, they can be supplied by a VDDA
voltage booster or by VDD, depending on the configuration of ANASWVDD and BOOSTEN bits in
SYSCFG_CFGR1.
It is recommended to supply the I/O switches with the highest voltage value between VDDA, VDDA booster,
and VDD.
Note: If possible, select VDDA or VDDA booster rather than VDD, as they are often less noisy.
The analog switches for TSC function are supplied by VDD.
2.2 Power supply schemes
The device is powered by a stabilized VDD power supply as described below:
•VDD pins must be connected to VDD with external decoupling capacitors: a 10 μF (typical value, 4.7 µF
minimum) single tantalum or ceramic capacitor for the package, and a 100 nF ceramic capacitor for each
VDD pin.
•VDD11 pins are present only on packages with SMPS. The SMPS step-down converter requires a 2.2 μH
(typical) external ceramic coil connected between VLXSMPS and VDD11 pins. In addition, two 2.2 μF
capacitors on VDD11 pins are connected to the VSSSMPS pin.
• The VCAP pin is present only on standard packages (without SMPS). It requires a 4.7 µF (typical) external
decoupling capacitor connected to VSS. If there are two VCAP pins (UFBGA169 package), each VCAP pin
must be connected to a 2.2 µF (typical) capacitor (for a total around 4.4 µF).
• The VDDA pin must be connected to two external decoupling capacitors: 100 nF ceramic and 1 μF
tantalum or ceramic.
Additional precautions can be taken to filter digital noise: VDDA can be connected to VDD through a ferrite
bead.
• The VREF+ pin can be provided by an external voltage reference. In this case, an external 100 nF + 1 μF
tantalum or ceramic capacitor must be connected on this pin.
It can also be provided internally by the VREFBUF. In this case, an external 1 μF (typical) capacitor must
be connected on this pin.
• The VBAT pin can be connected to an external battery to preserve the content of the Backup domain:
– When VDD is present, the external battery can be charged on VBAT through a 5 kΩ or 1.5 kΩ
internal resistor. In this case, the user can insert a capacitor according to the expected discharging
time (1 µF is recommended).
– If no external battery is used in the application, it is recommended to connect the VBAT pin to VDD
with a 100 nF external ceramic decoupling capacitor.
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Figure 7. Power supply scheme for U535/545/575/585xxxxQ (with SMPS)
DT64359V1
VDDIO2
VDD
Kernel logic
(CPU, digital
and memories)
Level shifter
IO
logic
Backup circuitry
(LSE, RTC, TAMP,
backup registers,
backup SRAM)
IN
OUT
GPIOs
1.65 – 3.6 V
IN
OUT
GPIOs
n x 100 nF
+ 10 µF
m x100 nF
Level shifter
IO
logic
+ 4.7 µF
m x VDDIO2
m x VSS
n x VSS
n x VDD
VBAT
VCORE
Power switch
VDDIO2
VDDIO1
ADCs/
DACs/
OPAMPs/
COMPs/
VREFBUF
VREF+
VREF-
VDDA
100 nF
+ 1 µF
VDDA
VSSA
VREF
100 nF+ 1 µF
VSSSMPS
2 x VDD11
VLXSMPS
VDDSMPS
VDD
2.2 µH
2 x 2.2 µF
10 µF
SMPS ON
SMPS OFF
LDO
SMPS
VDDUSB
3.3 V
100 nF
Voltage regulator
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Figure 8. Power supply scheme for STM32U535/545/575/585xx (without SMPS)
DT64358V1
VDDIO2
VDD
Level shifter
I/O
logic
Kernel logic
(CPU, digital
and
memories)
Backup circuitry
(LSE, RTC, TAMP
backup registers,
backup SRAM)
IN
OUT
LDO
regulator
GPIOs
1.65 – 3.6 V
IN
OUT
GPIOs
n x 100 nF
+ 1 x 10 µF
m x 100 nF
Level shifter
I/O
logic
+ 4.7 µF
m x VDDIO2
m x VSS
n x VSS
n x VDD
VBAT
VCORE
Power switch
VDDIO2
VDDIO1
ADCs/
DACs/
OPAMPs/
COMPs/
VREFBUF
VREF+
VREF-
VDDA
100 nF
+1 µF
VDDA
VSSA
VREF
100 nF+ 1 µF
VCORE
4.7 µF
VCAP
VDDUSB
3.3 V
100 nF
Caution: If there are two VCAP pins (UFBGA169 package), each pin must be connected to a 2.2 µF (typical) capacitor
(for a total around 4.4 µF).
AN5373
Power supply schemes
AN5373 - Rev 6 page 15/47

Figure 9. Power supply scheme for STM32U5F/5G/59/5Axxx (with SMPS)
DT69108V1
VDDIO2
VDD
Kernel logic
(CPU, digital
and memories)
Level shifter
IO
logic
Backup circuitry
(LSE, RTC, TAMP,
backup registers,
backup SRAM)
IN
OUT
GPIOs
1.55 – 3.6 V
IN
OUT
GPIOs
n x 100 nF
+ 10 µF
m x100 nF
Level shifter
IO
logic
+ 4.7 µF
m x VDDIO2
m x VSS
n x VSS
n x VDD
VBAT
VCORE
Power switch
VDDIO2
VDDIO1
ADCs/
DACs/
OPAMPs/
COMPs/
VREFBUF
VREF+
VREF-
VDDA
100 nF
+ 1 µF
VDDA
VSSA
VREF
100 nF+ 1 µF
VSSSMPS
2 x VDD11
VLXSMPS
VDDSMPS
VDD
2.2 µH
2 x 2.2 µF
10 µF
SMPS ON
SMPS OFF
LDO
SMPS
VDDUSB
3.3 V
100 nF
Voltage regulator
VDDDSI(2)
100 nF
VDD11(1)
VDD11USB(1)
VDD11DSI(2)
(1) Only available on specific packages.
(2) Only available on STM32U5x9 devices.
AN5373
Power supply schemes
AN5373 - Rev 6 page 16/47

Figure 10. Power supply scheme for STM32U5F/5G/59/5Axxx (without SMPS)
DT71165V1
VDDIO2
VDD
Kernel logic
(CPU, digital
and memories)
Level shifter
I/O
logic
Backup circuitry
(LSE, RTC, TAMP,
backup registers,
backup SRAM)
IN
OUT
GPIOs
1.65 – 3.6 V
IN
OUT
GPIOs
m x100 nF
Level shifter
I/O
logic
+ 4.7 µF
m x VDDIO2
m x VSS
n x VSS
n x VDD
VBAT
VCORE
Power switch
VDDIO2
VDDIO1
ADCs/
DACs/
OPAMPs/
COMPs/
VREFBUF
VREF+
VREF-
VDDA
100 nF
+ 1 µF
VDDA
VSSA
VREF
100 nF+ 1 µF
VCAP
4.7 µF
VDDUSB
VDDUSB
100 nF
LDO
regulator VCORE
Note: • SMPS and LDO regulators provide, in a concurrent way, the VCORE supply depending on application
requirements. However, only one of them is active at the same time. When SMPS is active, it feeds the
VCORE on the two VDD11 pins provided through the SMPS VLXSMPS output pin. A 2.2 µH coil and a
2.2 μF capacitor on each VDD11 pin are then required. When LDO is active, it provides the VCORE and
regulates it using the same decoupling capacitors on VDD11 pins.
• It is recommended to add a decoupling capacitor of 100 nF near each VDD11 pin/ball, but it is not
mandatory.
AN5373
Power supply schemes
AN5373 - Rev 6 page 17/47

2.3 Power supply sequence between VDDA, VDDUSB, VDDIO2, and VDD
2.3.1 Power supply isolation
The devices feature a powerful reset system that ensures the main power supply (VDD) has reached a valid
operating range before releasing the MCU reset.
This reset system is also in charge of isolating the independent power domains: VDDA, VDDUSB, VDDIO2, and VDD.
This reset system is supplied by VDD and is not functional before VDD reaches a minimal voltage (1 V in
worse‑case conditions).
To avoid leakage currents between the available supplies and VDD (or ground), VDD must be provided first to the
MCU, and then released with tolerance during power down (see Section 2.3.3).
2.3.2 General requirements
During power-up and power-down phases, the following power sequence requirements must be respected:
• When VDD is below 1 V, other power supplies (VDDA, VDDIO2, and VDDUSB) must remain below
VDD + 300 mV.
• When VDD is above 1 V, all power supplies are independent.
Figure 11. Power-up/power-down sequence
DT47490V2
0.3
1
VPDR
3.6
Operating modePower-on Power-down time
V
VDDX(1)
VDD
Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
VPOR
(1) VDDX refers to any power supply among VDDA, VDDUSB, and VDDIO2.
Note: VBAT is an independent supply and has no constraint versus VDD. All power supply rails can be tied together.
2.3.3 Particular conditions during the power-down phase
During the power-down phase, VDD can temporarily become lower than other supplies only if the energy provided
to the MCU remains below 1 mJ. This allows external decoupling capacitors to be discharged with different time
constants during the power-down transient phase (see Figure 11).
VDDX (VDDA, VDDIO2, or VDDUSB) power rails must be switched off before VDD.
Note: During the power-down transient phase, VDDX can remain temporarily above VDD (see Figure 11).
AN5373
Power supply sequence between VDDA, VDDUSB, VDDIO2, and VDD
AN5373 - Rev 6 page 18/47

Example of computation of the energy provided to the MCU during the power-down phase
If the sum of decoupling capacitors on VDDX is 10 μF and VDD drops below 1 V while VDDX is still at 3.3 V,
the energy remaining in the decoupling capacitors is:
E=1
2C×V2=1 2× 10−5× 3.32= 0.05 mJ
The energy remaining in the decoupling capacitors is below 1 mJ, so it is acceptable for the MCU to absorb it.
2.4 Reset and power-supply supervisor
2.4.1 Brownout reset (BOR)
The devices have a brownout reset (BOR) circuitry. The BOR is active in all power modes except Shutdown
mode, and cannot be disabled. The BOR monitors the backup domain supply voltage that is VDD when present,
VBAT otherwise.
Five BOR thresholds can be selected through option bytes.
During power-on, the BOR keeps the device under reset until the supply voltage VDD reaches the specified VBORx
threshold. When VDD drops below the selected threshold, a device reset is generated. When VDD is above the
VBORx upper limit, the device reset is released, and the system can start.
For more details on the brownout reset thresholds, refer to the electrical characteristics section in the datasheet.
Figure 12. Brownout reset waveform
DT31444V1
VBOR0 (rising edge)
hysteresis
Temporization
tRSTTEMPO
Reset
VDD
VBOR0 (falling edge)
Note: The reset temporization tRSTTEMPO is present only for the BOR lowest threshold (VBOR0).
2.4.2 System reset
A system reset sets all registers to their reset values except the reset flags in RCC_CSR and the registers in the
backup domain.
A system reset is generated when one of the following events occurs (refer to document [1] for more details):
• a low level on the NRST pin (external reset)
• a window watchdog event (WWDG reset)
• an independent watchdog event (IWDG reset)
• a software reset
• a low-power mode security reset
• an option-byte loader reset
• a brownout reset
These sources act on the NRST pin that is always kept low during the delay phase. The reset service routine
vector is selected via the boot option bytes.
AN5373
Reset and power-supply supervisor
AN5373 - Rev 6 page 19/47

The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a
minimum reset pulse duration of 20 μs for each internal reset source. In case of an external reset, the reset pulse
is generated while the NRST pin is asserted low.
In case of an internal reset, the internal pull-up RPU is deactivated in order to save the power consumption
through the pull-up resistor.
Figure 13. Simplified diagram of the reset circuit
DT40966V1
External
reset
VDD
RPU
WWDG reset
Software reset
Low-power manager reset
IWDG reset
Option byte loader reset
Pulse
generator
(min 20 μs)
NRST
System reset
Filter
BOR
2.4.3 Backup domain reset
A backup domain reset is generated when one of the following events occurs:
• a software reset, triggered by setting the BDRST bit in RCC_BDCR
• a VDD or VBAT power-on, if both supplies have previously been powered off
A backup domain reset only affects the LSE oscillator, RTC and TAMP, backup registers, the backup SRAM, and
RCC_BDCR and PWR_BDCR1.
AN5373
Reset and power-supply supervisor
AN5373 - Rev 6 page 20/47