ST STA309A User manual

October 2009 Doc ID 13855 Rev 4 1/67
67
STA309A
Multi-channel digital audio processor with DDX®
Features
8 channels of 24-bit DDX®(direct digital
amplification)
>100 dB of SNR and dynamic range
Selectable 32 kHz - 192 kHz input sample rates
6 channels of DSD/SACD input
Digital gain/attenuation +58 dB to -100 dB in
0.5-dB steps
Soft volume update
Individual channel and master gain/attenuation
plus channel trim (-10 dB to +10 dB)
Up to 10 independent 32-bit user
programmable biquads (EQ) per channel
Bass/treble tone control
Pre and post EQ full 8-channel input mix on all
8 channels
Dual independent limiters/compressors
Dynamic range compression
Automode™:
– 5-band graphic EQ
– 32 preset EQ curves (rock, jazz, pop, etc.)
– Automatic volume controlled loudness
– 5.1 to 2-channel downmix
– Simultaneous 5.1- and 2-channel downmix
outputs
– 3 preset volume curves
– 2 preset anti-clipping modes
– Preset movie nighttime listening mode
– Preset TV channel/commercial AGC mode
– 5.1, 2.1 bass management configurations
– 8 preset crossover filters
Individual channel and master soft/hard mute
Automatic zero-detect and invalid input mute
Automatic invalid input detect mute
Advanced PopFree operation
Advanced AM interference frequency
switching and noise suppression modes
I2S output channel mapping function
Independent channel volume and DSP bypass
Channel mapping of any input to any
processing/DDX®channel
DC blocking selectable high-pass filter
Selectable per-channel DDX®damped ternary
or binary PWM output
Max power correction for lower full-power THD
Variable per channel DDX®o utput delay control
192 kHz internal processing sample rate, 24-bit
to 36-bit precision
Description
The STA309A is a single chip solution for digital
audio processing and control in multi-channel
applications. It provides output capabilities for
DDX®. In conjunction with a DDX®power device,
the STA309A provides high-quality,
high-efficiency, all digital amplification. The device
is extremely versatile, allowing inputs of most
digital formats including 6.1/7.1-channel and
192 kHz, 24-bit DVD-audio, DSD/SACD. In 5.1
applications the additional 2 channels can be
used for audio line-out or headphone drive. In
speaker mode, with 8 channel outputs in parallel,
the STA309A can deliver more than 1 W.
Table 1. Device summary
Order code Package
STA309A TQFP64
STA309A13TR TQFP64
TQFP64
www.st.com

Contents STA309A
2/67 Doc ID 13855 Rev 4
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5I
2C bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 Application reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.2.1 Configuration register A (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.2.2 Configuration register B (0x01) - serial input formats . . . . . . . . . . . . . . 24
7.2.3 Configuration register C (0x02) - serial output formats . . . . . . . . . . . . . 26
7.2.4 Configuration register D (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.2.5 Configuration register E (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2.6 Configuration register F (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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Doc ID 13855 Rev 4 3/67
7.2.7 Configuration register G (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2.8 Configuration register H (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.2.9 Configuration register I (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2.10 Master mute register (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.11 Master volume register (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.12 Channel 1 volume (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.13 Channel 2 volume (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.14 Channel 3 volume (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.15 Channel 4 volume (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.16 Channel 5 volume (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.17 Channel 6 volume (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.18 Channel 7 volume (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.19 Channel 8 volume (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.20 Channel 1 volume trim, mute, bypass (0x13) . . . . . . . . . . . . . . . . . . . . 35
7.2.21 Channel 2 volume trim, mute, bypass (0x14) . . . . . . . . . . . . . . . . . . . . 35
7.2.22 Channel 3 volume trim, mute, bypass (0x15) . . . . . . . . . . . . . . . . . . . . 35
7.2.23 Channel 4 volume trim, mute, bypass (0x16) . . . . . . . . . . . . . . . . . . . . 36
7.2.24 Channel 5 volume trim, mute, bypass (0x17) . . . . . . . . . . . . . . . . . . . . 36
7.2.25 Channel 6 volume trim, mute, bypass (0x18) . . . . . . . . . . . . . . . . . . . . 36
7.2.26 Channel 7 volume trim, mute, bypass (0x19) . . . . . . . . . . . . . . . . . . . . 36
7.2.27 Channel 8 volume trim, mute, bypass (0x1A) . . . . . . . . . . . . . . . . . . . . 36
7.2.28 Channel input mapping channels 1 and 2 (0x1B) . . . . . . . . . . . . . . . . . 38
7.2.29 Channel input mapping channels 3 and 4 (0x1C) . . . . . . . . . . . . . . . . . 38
7.2.30 Channel input mapping channels 5 and 6 (0x1D) . . . . . . . . . . . . . . . . . 38
7.2.31 Channel input mapping channels 7 and 8 (0x1E) . . . . . . . . . . . . . . . . . 38
7.2.32 AUTO1 - Automode™ EQ, volume, GC (0x1F) . . . . . . . . . . . . . . . . . . . 39
7.2.33 AUTO2 - Automode™ bass management2 (0x20) . . . . . . . . . . . . . . . . 40
7.2.34 AUTO3 - Automode™ AM/prescale/bass management scale (0x21) . . 41
7.2.35 PREEQ - Preset EQ settings (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.2.36 AGEQ - graphic EQ 80-Hz band (0x23) . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.37 BGEQ - graphic EQ 300-Hz band (0x24) . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.38 CGEQ - graphic EQ 1-kHz band (0x25) . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.39 DGEQ - graphic EQ 3-kHz band (0x26) . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.40 EGEQ - graphic EQ 8-kHz band (0x27) . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.2.41 Biquad internal channel loop-through (0x28) . . . . . . . . . . . . . . . . . . . . . 45
7.2.42 Mix internal channel loop-through (0x29) . . . . . . . . . . . . . . . . . . . . . . . 45
7.2.43 EQ bypass (0x2A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Contents STA309A
4/67 Doc ID 13855 Rev 4
7.2.44 Tone control bypass (0x2B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.2.45 Tone control (0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.2.46 Channel limiter select channels 1,2,3,4 (0x2D) . . . . . . . . . . . . . . . . . . . 47
7.2.47 Channel limiter select channels 5,6,7,8 (0x2E) . . . . . . . . . . . . . . . . . . . 47
7.2.48 Limiter 1 attack/release rate (0x2F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.2.49 Limiter 1 attack/release threshold (0x30) . . . . . . . . . . . . . . . . . . . . . . . . 48
7.2.50 Limiter 2 attack/release rate (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.2.51 Limiter 2 attack/release threshold (0x32) . . . . . . . . . . . . . . . . . . . . . . . . 48
7.2.52 Bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.2.53 Channel 1 and 2 output timing (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.2.54 Channel 3 and 4 output timing (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.2.55 Channel 5 and 6 output timing (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.2.56 Channel 7 and 8 output timing (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.2.57 Channel I2S output mapping channels 1 and 2 (0x37) . . . . . . . . . . . . . 54
7.2.58 Channel I2S output mapping channels 3 and 4 (0x38) . . . . . . . . . . . . . 54
7.2.59 Channel I2S output mapping channels 5 and 6 (0x39) . . . . . . . . . . . . . 54
7.2.60 Channel I2S output mapping channels 7 and 8 (0x3A) . . . . . . . . . . . . . 54
7.2.61 Coefficient address register 1 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.2.62 Coefficient address register 2 (0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.2.63 Coefficient b1 data register, bits 23:16 (0x3D) . . . . . . . . . . . . . . . . . . . . 55
7.2.64 Coefficient b1 data register, bits 15:8 (0x3E) . . . . . . . . . . . . . . . . . . . . . 55
7.2.65 Coefficient b1 data register, bits 7:0 (0x3F) . . . . . . . . . . . . . . . . . . . . . . 55
7.2.66 Coefficient b2 data register, bits 23:16 (0x40) . . . . . . . . . . . . . . . . . . . . 55
7.2.67 Coefficient b2 data register, bits 15:8 (0x41) . . . . . . . . . . . . . . . . . . . . . 55
7.2.68 Coefficient b2 data register, bits 7:0 (0x42) . . . . . . . . . . . . . . . . . . . . . . 56
7.2.69 Coefficient a1 data register, bits 23:16 (0x43) . . . . . . . . . . . . . . . . . . . . 56
7.2.70 Coefficient a1 data register, bits 15:8 (0x44) . . . . . . . . . . . . . . . . . . . . . 56
7.2.71 Coefficient a1 data register, bits 7:0 (0x45) . . . . . . . . . . . . . . . . . . . . . . 56
7.2.72 Coefficient a2 data register, bits 23:16 (0x46) . . . . . . . . . . . . . . . . . . . . 56
7.2.73 Coefficient a2 data register, bits 15:8 (0x47) . . . . . . . . . . . . . . . . . . . . . 56
7.2.74 Coefficient a2 data register, bits 7:0 (0x48) . . . . . . . . . . . . . . . . . . . . . . 56
7.2.75 Coefficient b0 data register, bits 23:16 (0x49) . . . . . . . . . . . . . . . . . . . . 56
7.2.76 Coefficient b0 data register, bits 15:8 (0x4A) . . . . . . . . . . . . . . . . . . . . . 57
7.2.77 Coefficient b0 data register, bits 7:0 (0x4B) . . . . . . . . . . . . . . . . . . . . . . 57
7.2.78 Coefficient write control register (0x4C) . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.3 Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.4 Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 58

STA309A Contents
Doc ID 13855 Rev 4 5/67
7.5 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.6 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8 Equalization and mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8.1 Postscale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8.2 Variable max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.2.1 MPCC1-2 (0x4D, 0x4E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.3 Variable distortion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.3.1 DCC1-2 (0x4F, 0x50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.4 PSCorrect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8.4.1 PSC1-2: ripple correction value (RCV) (0x51, 0x52) . . . . . . . . . . . . . . . 63
8.4.2 PSC3: correction normalization value (CNV) (0x53) . . . . . . . . . . . . . . . 63
9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 65
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

List of tables STA309A
6/67 Doc ID 13855 Rev 4
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. General interface electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. DC electrical characteristics: 3.3-V buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. MSC bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. MSC sample rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 11. Interpolation ratio bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. IR sample rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. DSPB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 14. COS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. SAI bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. SAIFB bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 17. SAI and SAIFB serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 18. SAO bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 19. SAOFB bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20. SAO serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 21. OM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 22. Output stage mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 23. CSZ bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 24. CSZ definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 25. MPC bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 26. CnBO bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 27. HPB bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 28. DRC bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 29. DEMP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 30. PSL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 31. BQL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 32. PWMS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 33. PWM output speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 34. Register G bit definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 35. AM2E bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 36. HPE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 37. DCCV bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 38. MPCV bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 39. NSBW bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 40. ZCE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 41. SVE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 42. ZDE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 43. IDE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 44. BCLE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 45. LDTE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 46. ECLE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 47. PSCE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 48. EAPD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

STA309A List of tables
Doc ID 13855 Rev 4 7/67
Table 49. MV bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 50. CnV bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 51. CnVT bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 52. CnIM bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 53. AMEQ bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 54. AMV bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 55. AMDM bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 56. AMBMME bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 57. AMBMXE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 58. CSS and RSS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 59. FSS and SUB bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 60. AMPS bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 61. MSA bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 62. AMAME bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 63. AMAM bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 64. XO bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 65. PEQ bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 66. xGEQ bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 67. CnBLP bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 68. CnMXLP bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 69. CnEQBP bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 70. BTC and TTC bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 71. Channel limiter mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 72. Attack rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 73. Release rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 74. LnAT bits, anti-clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 75. LnRT bits, anti-clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 76. LnAT bits, dynamic range compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 77. LnRT bits, dynamic range compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 78. PWM slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 79. CnOM serial output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 80. RAM block for biquads, mixing, and bass management. . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 81. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

List of figures STA309A
8/67 Doc ID 13855 Rev 4
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2. Channel signal flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. Read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. Reference schematic for STA309A-based application . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 8. Channel mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 9. TQFP64 (10 x 10 x 1.4 mm) package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

STA309A Block diagram
Doc ID 13855 Rev 4 9/67
1 Block diagram
Figure 1. Block diagram
Figure 2. Channel signal flow
OUT1A/B
OUT2A/B
OUT3A/B
OUT4A/B
OUT5A/B
OUT6A/B
OUT7A/B
OUT8A/B
LRCKI
BICKI
SDI12
SDI34
SDI56
SDI78
SA
SERIAL
DATA
IN
I
2
C
CHANNEL
MAPPING
VARIABLE
OVER-
SAMPLING
TREBLE,
BASS, EQ
(
BIQUADS
)
VOLUME
LIMITING
SDO78
SDO12
SDO34
SDO56
OVERSAMPLING
VARIABLE
DOWN-
SAMPLING
POWER
DOWN
PWDN EAPD
PLL
PLLB
XTI CKOUT
SCL SDA
LRCKO
BICKO
MVO
SERIAL
DATA
OUT
SYSTEM
CONTROL
SYSTEM TIMING
DDX
1x,2x,4x
Interp
Biq uads
B/T
Volume
Limiter
2x
Interp
Distortion
Compensation
NS C_Con PWM
DDX
Output
Interp_Rate
8 Inputs
From I2S
DSD
Conversion
6 Inputs
From DSD
Mapping/
Mix #1
DSDE
Mix #2
PreScale Hig h- P as s
Filter
Bi qu a d
#2
Biquad
#3
Biquad
#4
Biq u a d
#5
Biquad
#6
Biquad
#7
Biquad
#8 Ba s s
Hard Set to
-18dB when
AutoMode EQ
(AMEQ)
Hard Set Coeffecients when AutoMode EQ
(AMEQ)
Hard Set
Coeffec ients when
Aut oMod e
Bass Management
Cross over
(AMBMXE)
Har d S e t
Coeffec ients when
DeEmphasis
Enabled
(DEMP)
From
Mix#1
Engine
Or
Previous
Channel
Bi qu a d # 1 0
Output
(CxBLP)
To
Mix#2
Engine
Treble
User Progammable
Biquad #1 when
High-Pass Bypassed
(HPB)
User Programmable
Biquads #9 and #10
When Tone Bypassed
(CxTCB)

Pin connections STA309A
10/67 Doc ID 13855 Rev 4
2 Pin connections
Figure 3. Pin connection (top view)
Table 2. Pin description
Pin Type Name Description
1 5-V tolerant TTL input buffer MVO/DSD_CLK Master volume override/
DSD input clock
6 5-V tolerant TTL input buffer SDI_78/DSD_6 Input serial data channels 7 & 8/
DSD input channel 6
7 5-V tolerant TTL input buffer SDI_56/DSD_5 Input serial data channels 5 & 6/
DSD input channel 5
8 5-V tolerant TTL input buffer SDI_34/DSD_4 Input serial data channels 3 & 4/
DSD input channel 4
9 5-V tolerant TTL input buffer SDI_12/DSD_3 Input serial data channels 1 & 2/
DSD input channel 3
10 5-V tolerant TTL input buffer LRCKI/DSD_2 Input left/right clock/
DSD input channel 2
11 5-V tolerant TTL input buffer BICKI/DSD_1 Input serial clock/
DSD input channel 1
15 5-V tolerant TTL schmitt
trigger input buffer RESET Global reset
16 CMOS input buffer with
pull-down PLL_BYPASS Bypass phase locked loop
1
2
3
5
6
4
7
8
9
10
27
11
28 29 30 31 32
59 58 57 56 54 55 53 52 51 50 49
43
42
41
39
38
40
48
47
46
44
45
SDI_78
NC
GND
GND
MVO
VDD
BICKI
LRCKI
SDI_12
SDI_56
SDI_34
NC
GNDA
VDDA
CKOUT
GND
NC
VDD
OUT8_B OUT8_A OUT7_B OUT7_A
VDD SDO_34 SDO_12 LRCKO
NC
BICKO GND VDD EAPD OUT1_A OUT1_B
OUT3_A
OUT3_B
OUT4_A
OUT5_A
OUT5_B
OUT4_B
OUT2_A
OUT2_B
NC
VDD
GND
STA308APINCON
22 23 24 25 26
60
GND
61
NC
62
SDO_56
63
SDO_78
64
PWDN
SA
SDA
SCL
XTI
FILTER_PLL
17 18 19 20 21
37
36
34
33
35
NC
GND
OUT6_A
OUT6_B
VDD
12
13
14
15
16
PLLB
RESET
NC
VDD
GND

STA309A Pin connections
Doc ID 13855 Rev 4 11/67
17 CMOS input buffer with
pull-down SA Select address (I2C)
18
Bidirectional buffer: 5-V
tolerant TTL schmitt trigger
input; 3.3-V capable 2mA
slew-rate controlled output.
SDA Serial data (I2C)
19 5-V tolerant TTL schmitt
trigger input buffer SCL Serial clock (I2C)
20 5-V tolerant TTL schmitt
trigger input buffer XTI Crystal oscillator input (clock input)
21 Analog pad FILTER_PLL PLL filter
23 Analog ground GNDA PLL ground
24 3.3V analog supply voltage VDDA PLL supply
25 3.3-V capable TTL tristate
4mA output buffer CKOUT Clock output
29 3.3-V capable TTL 16mA
output buffer OUT8B PWM channel 8 output B
30 3.3-V capable TTL 16mA
output buffer OUT8A PWM channel 8 output A
31 3.3-V capable TTL 16mA
output buffer OUT7B PWM channel 7 output B
32 3.3-V capable TTL 16mA
output buffer OUT7A PWM channel 7 output A
33 3.3-V capable TTL 16mA
output buffer OUT6B PWM channel 6 output B
34 3.3-V capable TTL 16mA
output buffer OUT6A PWM channel 6 output A
38 3.3-V capable TTL 16mA
output buffer OUT5B PWM channel 5 output B
39 3.3-V capable TTL 16mA
output buffer OUT5A PWM channel 5 output A
40 3.3-V capable TTL 16mA
output buffer OUT4B PWM channel 4 output B
41 3.3-V capable TTL 16mA
output buffer OUT4A PWM channel 4 output A
42 3.3-V capable TTL 16mA
output buffer OUT3B PWM channel 3 output B
43 3.3-V capable TTL 16mA
output buffer OUT3A PWM channel 3 output A
47 3.3-V capable TTL 16mA
output buffer OUT2B PWM channel 2 output B
Table 2. Pin description (continued)
Pin Type Name Description

Pin connections STA309A
12/67 Doc ID 13855 Rev 4
48 3.3-V capable TTL 16mA
output buffer OUT2A PWM channel 2 output A
49 3.3-V capable TTL 16mA
output buffer OUT1B PWM channel 1 output B
50 3.3-V capable TTL 16mA
output buffer OUT1A PWM channel 1 output A
51 3.3-V capable TTL 4mA
output buffer EAPD Ext. amp power-down
55 3.3-V capable TTL 2mA
output buffer BICKO Output serial clock
56 3.3-V capable TTL 2mA
output buffer LRCKO Output left/right clock
57 3.3-V capable TTL 2mA
output buffer SDO_12 Output serial data channels 1&2
58 3.3-V capable TTL 2mA
output buffer SDO_34 Output serial data channels 3&4
62 3.3-V capable TTL 2mA
output buffer SDO_56 Output serial data channels 5&6
63 3.3-V capable TTL 2mA
output buffer SDO_78 Output serial data channels 7&8
64 5-V tolerant TTL schmitt
trigger input buffer PWDN Device power-down
3,12,28,35,
44,52,59 3.3-V digital supply voltage VDD 3.3-V supply
2,4,13,27,
36,45,53,60 Digital ground GND Ground
5, 14, 22,
26,37,46,54,
61
- NC No internal connection
Table 2. Pin description (continued)
Pin Type Name Description

STA309A Electrical specification
Doc ID 13855 Rev 4 13/67
3 Electrical specification
3.1 Absolute maximum ratings
3.2 Thermal data
3.3 Recommended operating condition
Table 3. Absolute maximum ratings
Symbol Parameter Min Typ Max Unit
VDD 3.3-V I/O power supply, pin VDD -0.5 - 4 V
VDDA 3.3-V logic power supply, pin VDDA -0.5 - 4 V
ViVoltage on input pins -0.5 - VDD +
0.5 V
VoVoltage on output pins -0.5 - VDD +
0.3 V
Tstg Storage temperature -40 - 150 °C
Tamb Ambient operating temperature -40 - 90 °C
Table 4. Thermal data
Symbol Parameter Min Typ Max Unit
Rthj-amb Thermal resistance, junction to ambient - 85 - °C/W
Table 5. Recommended operating condition
Symbol Parameter Min Typ Max Unit
VDD I/O power supply, pin VDD 3.0 - 3.6 V
VDDA Logic power supply, pin VDDA 3.0 - 3.6 V
TjOperating junction temperature -40 - 125 °C

Electrical specification STA309A
14/67 Doc ID 13855 Rev 4
3.4 Electrical specifications
The following specifications are valid for VDD = 3.3 V ± 0.3 V, VDDA = 3.3 V ± 0.3 V and
Tamb = 0 to 70 °C, unless otherwise stated
Table 6. General interface electrical specifications
Symbol Parameter Conditions Min Typ Max Unit
Iil Low-level input no pull-up Vi=0V --1(1)
1. The leakage currents are generally very small, < 1 nA. The values given here are maximum after an
electrostatic stress on the pin.
µA
Iih
High-level input no
pull-down Vi= VDD --2µA
IOZ
Tristate output leakage
without pull-up/down Vi= VDD --2µA
Vesd
Electrostatic protection
(human body model) Leakage < 1µA 2000--V
Table 7. DC electrical characteristics: 3.3-V buffers
Symbol Parameter Conditions Min Typ Max Unit
VIL Low-level input voltage - - - 0.8 V
VIH High-level input voltage - 2.0 - - V
VILhyst Low-level threshold Input falling 0.8 - 1.35 V
VIHhyst High-level threshold Input rising 1.3 - 2.0 V
Vhyst Schmitt trigger hysteresis - 0.3 - 0.8 V
VOL Low-level output IOL = 100uA - - 0.2 V
VOH High-level output IOH = -100uA VDD -
0.2 --V
IOH = -2mA 2.4 - - V

STA309A Pin description
Doc ID 13855 Rev 4 15/67
4 Pin description
Master volume override (MVO)
This pin enables the user to bypass the volume control on all channels. When MVO is pulled
high, the master volume register is set to 0x00, which corresponds to its full scale setting.
The master volume register setting offsets the individual channel volume settings, which
default to 0 dB.
Serial data in (SDI_12, SDI_34, SDI_56, SDI_78)
Audio information enters the device here. Six format choices are available including I2S,
left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
RESET
Driving this pin low turns off the outputs and returns all settings to their defaults.
I
2
C bus
The SA, SDA and SCL pins operate per the Phillips I2C specification. See Section 5.
Phase locked loop (PLL)
The phase locked loop section provides the system timing signals and CKOUT.
Clock output (CKOUT)
System synchronization and master clocks are provided by the CKOUT.
PWM outputs (OUT1 through OUT8)
The PWM outputs provide the input signal for the power devices.
External amplifier power-down (EAPD)
This signal can be used to control the power-down of DDX power devices.
Serial data out (SDO_12, SDO_34, SDO_56, SDO_78)
These are the outputs for audio information. Six different formats are available including I2S,
left- or right-justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.
Device power-down (PWDN)
Pulling PWDN low begins the power-down sequence which puts the STA309A into a
low-power state. EAPD (pin 51) goes low approximately 30 ms later.

I2C bus operation STA309A
16/67 Doc ID 13855 Rev 4
5 I2C bus operation
The STA309A supports the I2C protocol via the input ports SCL and SDA_IN (master to
slave) and the output port SDA_OUT (slave to master).
This protocol defines any device that sends data on to the bus as a transmitter and any
device that reads the data as a receiver.
The device that controls the data transfer is known as the master and the other as the slave.
The master always starts the transfer and provides the serial clock for synchronization. The
STA309A is always a slave device in all of its communications.
5.1 Communication protocol
5.1.1 Data transition or change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition
while the clock is high is used to identify a START or STOP condition.
5.1.2 Start condition
START is identified by a high to low transition of the data bus SDA signal while the clock
signal SCL is stable in the high state. A START condition must precede any command for
data transfer.
5.1.3 Stop condition
STOP is identified by low to high transition of the data bus SDA signal while the clock signal
SCL is stable in the high state. A STOP condition terminates communication between
STA309A and the bus master.
5.1.4 Data input
During the data input the STA309A samples the SDA signal on the rising edge of clock SCL.
For correct device operation the SDA signal must be stable during the rising edge of the
clock and the data can change only when the SCL line is low.
5.2 Device addressing
To start communication between the master and the Omega DDX core, the master must
initiate with a start condition. Following this, the master sends 8 bits onto the SDA line (MSB
first) corresponding to the device select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I2C bus
definition. In the STA309A the I2C interface has two device addresses depending on the SA
port configuration, 0x40 or 0100000x when SA = 0, and 0x42 or 0100001x when SA = 1.
The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode and 0
for write mode. After a START condition the STA309A identifies on the bus the device

STA309A I2C bus operation
Doc ID 13855 Rev 4 17/67
address and if a match is found, it acknowledges the identification on SDA bus during the
9th-bit time. The byte following the device identification byte is the internal space address.
5.3 Write operation
Following the START condition the master sends a device select code with the RW bit set
to 0. The STA309A acknowledges this and the writes for the byte of internal address.
After receiving the internal byte address the STA309A again responds with an
acknowledgement.
5.3.1 Byte write
In the byte write mode the master sends one data byte, this is acknowledged by the Omega
DDX core. The master then terminates the transfer by generating a STOP condition.
5.3.2 Multi-byte write
The multi-byte write modes can start from any internal address. The master generating a
STOP condition terminates the transfer.
Figure 4. Write mode sequence
Figure 5. Read mode sequence
DEV-ADDR
ACK
START RW
SUB-ADDR
ACK
DATA IN
A
CK
STOP
BYTE
WRITE
DEV-ADDR
ACK
START RW
SUB-ADDR
ACK
DATA IN
A
CK
STOP
MULTIBYTE
WRITE
DATA IN
A
CK
DEV-ADDR
ACK
START RW
DATA
NO ACK
STOP
CURRENT
ADDRESS
READ
DEV-ADDR
ACK
START RW
SUB-ADDR
ACK
DEV-ADDR
A
CK
STOP
RANDOM
ADDRESS
READ
DATA
NO
A
CK
START RW
DEV-ADDR
ACK
START
DATA
ACK
DATA
ACK
STOP
SEQUENTIAL
CURRENT
READ
DATA
NO
A
CK
DEV-ADDR
ACK
START RW
SUB-ADDR
ACK
DEV-ADDR
A
CK
SEQUENTIAL
RANDOM
READ
DATA
A
CK
START RW
DATA
A
CK NO
A
CK
STOP
DATA
RW=
HIGH

Application reference schematic STA309A
18/67 Doc ID 13855 Rev 4
6 Application reference schematic
Figure 6. Reference schematic for STA309A-based application
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The PLL filter must be placed as close as possible to the STA309A pins

STA309A Registers
Doc ID 13855 Rev 4 19/67
7 Registers
7.1 Register summary
Table 8. Register summary
Addr Name D7 D6 D5 D4 D3 D2 D1 D0
Configuration
0x00 CONFA COS1 COS0 DSPB IR1 IR0 MCS2 MCS1 MCS0
0x01 CONFB Reserved SAIFB SAI3 SAI2 SAI1 SAI0
0x02 CONFC Reserved SAOFB SAO3 SAO2 SAO1 SAO0
0x03 CONFD MPC CSZ4 CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0
0x04 CONFE C8BO C7BO C6BO C5BO C4BO C3BO C2BO C1BO
0x05 CONFF PWMS2 PWMS1 PWMS0 BQL PSL DEMP DRC HPB
0x06 CONFG MPCV DCCV HPE AM2E AME COD SID PWMD
0x07 CONFH ECLE LDTE BCLE IDE ZDE SVE ZCE NSBW
0x08 CONFI EAPD Reserved PSCE
Volume control
0x09 MMUTE Reserved MMUTE
0x0A MVOL MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0
0x0B C1VOL C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0
0x0C C2VOL C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0
0x0D C3VOL C3V7 C3V6 C3V5 C3V4 C3V3 C3V2 C3V1 C3V0
0x0E C4VOL C4V7 C4V6 C4V5 C4V4 C4V3 C4V2 C4V1 C4V0
0x0F C5VOL C5V7 C5V6 C5V5 C5V4 C5V3 C5V2 C5V1 C5V0
0x10 C6VOL C6V7 C6V6 C6V5 C6V4 C6V3 C6V2 C6V1 C6V0
0x11 C7VOL C7V7 C7V6 C7V5 C7V4 C7V3 C7V2 C7V1 C7V0
0x12 C8VOL C8V7 C8V6 C8V5 C8V4 C8V3 C8V2 C8V1 C8V0
0x13 C1VTMB C1M C1VBP Reserved C1VT4 C1VT3 C1VT2 C1VT1 C1VT0
0x14 C2VTMB C2M C2VBP Reserved C2VT4 C2VT3 C2VT2 C2VT1 C2VT0
0x15 C3VTMB C3M C3VBP Reserved C3VT4 C3VT3 C3VT2 C3VT1 C3VT0
0x16 C4VTMB C4M C4VBP Reserved C4VT4 C4VT3 C4VT2 C4VT1 C4VT0
0x17 C5VTMB C5M C5VBP Reserved C5VT4 C5VT3 C5VT2 C5VT1 C5VT0
0x18 C6VTMB C6M C6VBP Reserved C6VT4 C6VT3 C6VT2 C6VT1 C6VT0
0x19 C7VTMB C7M C7VBP Reserved C7VT4 C7VT3 C7VT2 C7VT1 C7VT0
0x1A C8VTMB C8M C8VBP Reserved C8VT4 C8VT3 C8VT2 C8VT1 C8VT0
Input mapping
0x1B C12IM Reserved C2IM2 C2IM1 C2IM0 Reserved C1IM2 C1IM1 C1IM0

Registers STA309A
20/67 Doc ID 13855 Rev 4
0x1C C34IM Reserved C4IM2 C4IM1 C4IM0 Reserved C3IM2 C3IM1 C3IM0
0x1D C56IM Reserved C6IM2 C6IM1 C6IM0 Reserved C5IM2 C5IM1 C5IM0
0x1E C78IM Reserved C8IM2 C8IM1 C8IM0 Reserved C7IM2 C7IM1 C7IM0
Automode™
0x1F AUTO1 AMDM AMGC2 AMGC1 AMGC0 AMV1 AMV0 AMEQ1 AMEQ0
0x20 AUTO2 SUB RSS1 RSS0 CSS1 CSS0 FSS AMBMXE AMBMME
0x21 AUTO3 AMAM2 AMAM1 AMAM0 AMAME Reserved MSA AMPS
0x22 PREEQ XO2 XO1 XO0 PEQ4 PEQ3 PEQ2 PEQ1 PEQ0
0x23 AGEQ Reserved AGEQ4 AGEQ3 AGEQ2 AGEQ1 AGEQ0
0x24 BGEQ Reserved BGEQ4 BGEQ3 BGEQ2 BGEQ1 BGEQ0
0x25 CGEQ Reserved CGEQ4 CGEQ3 CGEQ2 CGEQ1 CGEQ0
0x26 DGEQ Reserved DGEQ4 DGEQ3 DGEQ2 DGEQ1 DGEQ0
0x27 EGEQ Reserved EGEQ4 EGEQ3 EGEQ2 EGEQ1 EGEQ0
Processing loop
0x28 BQLP C8BLP C7BLP C6BLP C5BLP C4BLP C3BLP C2BLP C1BLP
0x29 MXLP C8MXLP C7MXLP C6MXLP C5MXLP C4MXLP C3MXLP C2MXLP C1MXLP
Processing bypass
0x2A EQBP C8EQBP C7EQBP C6EQBP C5EQBP C4EQBP C3EQBP C2EQBP C1EQBP
0x2B TONEBP C8TCB C7TCB C6TCB C5TCB C4TCB C3TCB C2TCB C1TCB
Tone control
0x2C TONE TTC3 TTC2 TTC1 TTC0 BTC3 BTC2 BTC1 BTC0
Dynamics control
0x2D C1234LS C4LS1 C4LS0 C3LS1 C3LS0 C2LS1 C2LS0 C1LS1 C1LS0
0x2E C5678LS C8LS1 C8LS0 C7LS1 C7LS0 C6LS1 C6LS0 C5LS1 C5LS0
0x2F L1AR L1A3 L1A2 L1A1 L1A0 L1R3 L1R2 L1R1 L1R0
0x30 L1ATRT L1AT3 L1AT2 L1AT1 L1AT0 L1RT3 L1RT2 L1RT1 L1RT0
0x31 L2AR L2A3 L2A2 L2A1 L2A0 L2R3 L2R2 L2R1 L2R0
0x32 L2ATRT L2AT3 L2AT2 L2AT1 L2AT0 L2RT3 L2RT2 L2RT1 L2RT0
PWM output timing
0x33 C12OT Reserved C2OT2 C2OT1 C2OT0 Reserved C1OT2 C1OT1 C1OT0
0x34 C34OT Reserved C4OT2 C4OT1 C4OT0 Reserved C3OT2 C3OT1 C3OT0
0x35 C56OT Reserved C6OT2 C6OT1 C6OT0 Reserved C5OT2 C5OT1 C5OT0
0x36 C78OT Reserved C8OT2 C8OT1 C8OT0 Reserved C7OT2 C7OT1 C7OT0
I2S output channel mapping
0x37 C12OM Reserved C2OM2 C2OM1 C2OM0 Reserved C1OM2 C1OM1 C1OM0
Table 8. Register summary (continued)
Addr Name D7 D6 D5 D4 D3 D2 D1 D0