TechNexion PICO-IMX6 User manual

PICO-IMX6
REV. A1 –VER. 1.01
January 28, 2016

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 2of 64
REVISION HISTORY
Revision
Date
Originator
Notes
1.00
September 30, 2015
TechNexion
Initial Public release
1.01
January 28, 2016
TechNexion
Minor changes and
updated regarding NXP
instead Freescale

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 3of 64
TABLE OF CONTENTS
1. Introduction ...............................................................................................................................................7
1.1. General Introduction...........................................................................................................................7
1.2. General Care and Maintenance .........................................................................................................8
1.3. Block Diagram..................................................................................................................................10
1.4. PICO Compute Module Compatibility...............................................................................................11
1.5. Dimensional Drawing........................................................................................................................12
1.6. Component Location ........................................................................................................................13
2. Core Components...................................................................................................................................15
2.1. NXP i.MX6 Cortex-A9 Multi-core Processor.....................................................................................15
2.1.1. i.MX6 Memory Interfaces...........................................................................................................17
2.1.2. i.MX6 DMA Engine ....................................................................................................................17
2.1.3. i.MX6 Video and Graphics Subsystems ....................................................................................18
2.2. Memory.............................................................................................................................................19
2.2.1 SKHynix ......................................................................................................................................19
2.2.2. Micron ........................................................................................................................................20
2.3. eMMC Storage (PICO-IMX6-EMMC Only).......................................................................................21
2.3.1. Sandisk iNAND SDIN7DP2 .......................................................................................................21
2.3.2. Kingston KE4CN2H5A...............................................................................................................22
2.3.3. Micro-SD Cardslot (PICO-IMX6-SD only)..................................................................................23
2.5. Broadcom BCM4339 WiFi/Bluetooth SiP Module............................................................................24
3. PICO Compute Module Connector Interfaces ........................................................................................27
3.1 Ethernet.............................................................................................................................................27
3.2. HDMI (High Definition Multi-Media Interface)...................................................................................28
3.3. LVDS Interface.................................................................................................................................29
3.4. Digital Display Sub-System (DSS) or TTL Interface ........................................................................30
3.5. MIPI Display .....................................................................................................................................32
3.6. MIPI Camera ....................................................................................................................................33
3.7. Audio Interface .................................................................................................................................34
3.8. PCI Express......................................................................................................................................35
3.9. Serial ATA Interface .........................................................................................................................36
3.10. Universal Serial Bus (USB) Interface .............................................................................................37
3.11. SDIO/MMC Interface......................................................................................................................38
3.12. CAN BUS Interface signals ............................................................................................................39
3.13. Universal Asynchronous Receiver/Transmitter (UART) Interface..................................................40
3.14. Serial Peripheral Interface (SPI).....................................................................................................41
3.15. I2C Bus............................................................................................................................................42

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 4of 64
3.16. General Purpose Input/Output (GPIO)...........................................................................................43
3.17. Pulse Width Modulation (PWM) .....................................................................................................44
3.18. Manufacturing and Boot Control.....................................................................................................45
3.19. Input Power Requirements.............................................................................................................46
3.19.1. Power Management Signals....................................................................................................46
3.19.2. Power Sequence .....................................................................................................................47
4. PICO Compute Module Pin Assignment.................................................................................................48
5. Development Kits, Proto-type Components and Accessories................................................................56
5.1. PICO-IMX6 Evaluation Kits ..............................................................................................................56
5.1.1. PICO Evaluation Start Kit Pack Content....................................................................................56
5.2. PICO Compatible Displays...............................................................................................................57
5.2.1. LVDSEXPANDER Translation Board to Connect to LVDS Panels...........................................57
5.2.2. TDHJ070NA4RESKIT Resistive Touch Display Kit Pack Content............................................58
5.2.3. TDHJ070NAPCAPKIT PCAP Touch Display Kit Pack Content ................................................59
5.3. Accessories ......................................................................................................................................60
5.3.1. EDMANTP150A138045D2450BK Pack Content.......................................................................60
5.4. PICO Compute Module Product Ordering Part Numbers ................................................................61
5.4.1 Standard Part Numbers..............................................................................................................61
5.4.2. Custom Part Number Creation Rules........................................................................................62
6. Important Notice......................................................................................................................................63
7. DISCLAIMER ..........................................................................................................................................64

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 5of 64
LIST OF TABLES
Table 1 - PICO Compatibility Overview ......................................................................................................11
Table 2 - eMMC Signal Description ............................................................................................................23
Table 3 - SD Cardslot Signal Description ...................................................................................................23
Table 4 - BCM4339 WiFi Signal Description...............................................................................................25
Table 5 - BCM4339 Bluetooth Signal Description ......................................................................................26
Table 6 - Ethernet Signal Description .........................................................................................................27
Table 7 - HDMI Signal Description..............................................................................................................28
Table 8 - LVDS Signal Description .............................................................................................................29
Table 9 - TTL Display Signal Description....................................................................................................31
Table 10 - MIPI Display Signal Description.................................................................................................32
Table 11 - MIPI Camera Signal Description................................................................................................33
Table 12 - I2S Audio Signal Description......................................................................................................34
Table 13 - PCI Express Signal Description.................................................................................................35
Table 14 - Serial ATA Signal Description....................................................................................................36
Table 15 - USB Host Signal Description.....................................................................................................37
Table 16 - USB OTG Signal Description.....................................................................................................37
Table 17 - SDIO/MMC Interface Signal Description ...................................................................................38
Table 18 - CAN Bus Signal Description......................................................................................................39
Table 19 - UART Signal Description...........................................................................................................40
Table 20 - SPI Channel Signal Description.................................................................................................41
Table 21 - I2C Bus Signal Description.........................................................................................................42
Table 22 - GPIO Signal Description............................................................................................................43
Table 23 - PWM Signal Description...........................................................................................................44
Table 24 - Boot Selection Pins....................................................................................................................45
Table 25 - Boot Signal Configuration..........................................................................................................45
Table 26 - Input Power Signals...................................................................................................................46
Table 27 - Power Management Signals......................................................................................................46
Table 28 - Input Power Sequencing for AT based configurations ..............................................................47

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 6of 64
LIST OF FIGURES
Figure 1 - PICO-IMX6-SD Block Diagram...................................................................................................10
Figure 2 - PICO-IMX6-EMMC Block Diagram.............................................................................................10
Figure 3 - PICO-IMX6 Compatibility Chart..................................................................................................11
Figure 4 - PICO-IMX6 Dimensional Drawing..............................................................................................12
Figure 5 - PICO-IMX6 Top view..................................................................................................................13
Figure 6 - PICO-IMX6-SD Bottom view ......................................................................................................13
Figure 7 - PICO-IMX6-EMMC Bottom view ................................................................................................14
Figure 8 - NXP i.MX6 Processor Blocks .....................................................................................................15
Figure 9 - NXP i.MX6 Processor Scalability Overview (Solo/Duallite/Dual/Quad) .....................................16
Figure 10 - PICO-IMX6 Antenna u.FL Connector Location ........................................................................24
Figure 11 - Input Power sequence for AT based configurations.................................................................47

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 7of 64
1. Introduction
1.1. General Introduction
The PICO-IMX6 is a high performance highly integrated PICO Compute Module designed around the
NXP i.MX6 Multicore ARM Cortex-A9. The PICO-IMX6 provides an ideal building block that easily
integrates with a wide range of target markets requiring rich multimedia functionality, powerful graphics
and video capabilities, as well as high-processing power, compact, cost effective and with low power
consumption.
The modular approach offered by the PICO Compute Module gives your project scalability, fast time to
market and upgradability while reducing engineering risk and maintain a competitive total cost of
ownership.

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 8of 64
1.2. General Care and Maintenance
Your device is a product of superior design and craftsmanship and should be treated with care.
The following suggestions will help you.
Keep the device dry. Precipitation, humidity, and all types of liquids or moisture can contain
minerals that will corrode electronic circuits. If your device does get wet, allow it to dry completely.
Do not use or store the device in dusty, dirty areas. Its moving parts and electronic components
can be damaged.
Do not store the device in hot areas. High temperatures can shorten the life of electronic devices,
damage batteries, and warp or melt certain plastics.
Do not store the device in cold areas. When the device returns to its normal temperature,
moisture can form inside the device and damage electronic circuit boards.
Do not attempt to open the device.
Do not drop, knock, or shake the device. Rough handling can break internal circuit boards and
fine mechanics.
Do not use harsh chemicals, cleaning solvents, or strong detergents to clean the device.
Do not paint the device. Paint can clog the moving parts and prevent proper operation.
Unauthorized modifications or attachments could damage the device and may violate regulations
governing radio devices.
These suggestions apply equally to your device, battery, charger, or any enhancement. If any device is
not working properly, take it to the nearest authorized service facility for service.
Regulatory information
Disposal of Waste Equipment by Users in Private Household in the European Union
This symbol on the product or on its packaging indicates that this product must not be
disposed of with your other household waste. Instead, it is your responsibility to dispose
of your waste equipment by handing it over to a designated collection point for the
recycling of waste electrical and electronic equipment. The separate collection and
recycling of your waste equipment at the time of disposal will help to conserve natural
resources and ensure that it is recycled in a manner that protects human health and the
environment. For more information about where you can drop off your waste equipment
for recycling, please contact your local city office, your household waste disposal service or the shop
where you purchased the product.
We hereby declare that the product is in compliance with the essential requirements and
other relevant provisions of European Directive 1999/5/EC (radio equipment and
telecommunications terminal equipment Directive).

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 9of 64
Federal Communications Commission (FCC) Unintentional emitter per FCC Part 15
This device has been tested and found to comply with the limits for a Class B digital
device, pursuant to Part 15 of the FCC rules. These limits are designed to provide
reasonable protection against harmful interference in a residential installation. This
equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instructions, may cause harmful interference
to radio or television reception. However, there is no guarantee that interference will
not occur in a particular installation. If this equipment does cause interference to radio and television
reception, which can be determined by turning the equipment off and on, the user is encouraged to try to
correct the interference by one or more of the following measures:
■ Reorient or relocate the receiving antenna
■ Increase the separation between the equipment and receiver
■ Connect the equipment to an outlet on a different circuit from that to which the receiver is connected
■ Consult the dealer or an experienced radio/TV technician for help.
WARNING! To reduce the possibility of heat-related injuries or of overheating the
computer, do not place the computer directly on your lap or obstruct the computer air
vents. Use the computer only on a hard, flat surface. Do not allow another hard surface,
such as an adjoining optional printer, or a soft surface, such as pillows or rugs or
clothing, to block airflow. Also, do not allow the AC adapter to contact the skin or a soft
surface, such as pillows or rugs or clothing, during operation. The computer and the AC
adapter comply with the user-accessible surface temperature limits defined by the International Standard
for Safety of Information Technology Equipment (IEC 60950).

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 10 of 64
1.3. Block Diagram
Figure 1 - PICO-IMX6-SD Block Diagram
Figure 2 - PICO-IMX6-EMMC Block Diagram

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 11 of 64
1.4. PICO Compute Module Compatibility
The PICO-IMX6 is function compatible with Intel®Edison and adds additional multimedia I/O Interfaces on
two additional expansion interfaces.
Figure 3 - PICO-IMX6 Compatibility Chart
Table 1 - PICO Compatibility Overview
Interface
Description
LAN
1 Gigabit Ethernet Signaling
LVDS
1 single channel 18/24 bit
HDMI
1 HDMI ver.1.4 compatible
TTL Display
1 TTL 18/24 bit Display
PCIe
1 Lane PCIe 2.0
SATA
Not available (Check PICO-IMX6POP for availability)
USB Host
1 USB 2.0 Host port
USB OTG
1 USB 2.0 OTG port (possible to use in Host mode)
I2S
2 Independent I2S interfaces
CAN Bus
2 FlexCAN CAN 2.0B protocol compliant interfaces
UART
1 UART (2 wire)
1 UART (4 wire)
SDIO
1 SDIO interface 4 bit
SPI
1 SPI interfaces with 2 chip selects
I2C
3 independent I2C channels
GPIO
13 dedicated GPIO’s available
PWM
4 PWM available

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 12 of 64
1.5. Dimensional Drawing
The PICO-IMX6 Compute Module is partly size compatible with Intel®Edison and adds several additional
I/O expansion interfaces on an enlarged footprint.
2D and 3D files can be obtained from the www.technexion.com homepage.
Figure 4 - PICO-IMX6 Dimensional Drawing

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 13 of 64
1.6. Component Location
Figure 5 - PICO-IMX6 Top view
Item
Description
Item
Description
1
NXP i.MX6 Processor
2
Memory IC
3
BCM4339 WiFi/Bluetooth IC
4
Antenna connector
Figure 6 - PICO-IMX6-SD Bottom view
Item
Description
Item
Description
1
Memory IC
2
Micro-SD Slot
3
Intel® Edison Compatible Connector
4
Expansion Connector 1
5
Expansion Connector 2
1
2
3
4
1
3
2
5
4

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 14 of 64
Figure 7 - PICO-IMX6-EMMC Bottom view
Item
Description
Item
Description
1
Memory IC
2
eMMC Storage IC
3
Intel® Edison Compatible Connector
4
Expansion Connector 1
5
Expansion Connector 2
1
3
2
5
4

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 15 of 64
2. Core Components
2.1. NXP i.MX6 Cortex-A9 Multi-core Processor
The NXP i.MX6 processor is an implementation of the Single/Dual/Quad ARM Cortex™-A9 core, which
operates at frequencies up to 1.2 GHz. The i.MX6 provides a variety of interfaces and supports the
following main features:
Single / Dual / Quad Core ARM Cortex™-A9. Core configuration is symmetric, where each core
includes:
o32 KByte L1 Instruction Cache
o32 KByte L1 Data Cache
oPrivate Timer and Watchdog
oCortex-A9 NEON MPE (Media Processing Engine) Co-processor
Level 2 Cache—Unified instruction and data (up to 1 MByte)
General Interrupt Controller (GIC) with 128 interrupt support
Global Timer
Snoop Control Unit (SCU)
NEON MPE coprocessor:
oSIMD Media Processing Architecture
oNEON register file with 32x64-bit general-purpose registers
oNEON Integer execute pipeline (ALU, Shift, MAC)
oNEON dual, single-precision floating point execute pipeline (FADD, FMUL)
oNEON load/store and permute pipeline
Integrated Power Management unit:
oTemperature Sensor for monitoring the die temperature
oDVFS techniques for low power modes
oFlexible clock gating control scheme
Multimedia Hardware Accelerators
Figure 8 - NXP i.MX6 Processor Blocks

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 16 of 64
Figure 9 - NXP i.MX6 Processor Scalability Overview (Solo/Duallite/Dual/Quad)

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 17 of 64
2.1.1. i.MX6 Memory Interfaces
The memory system consists of the following components:
oLevel 1 Cache—32 KB Instruction, 32 KB Data cache per core
oLevel 2 Cache—Unified instruction and data (1 MByte)
On-Chip Memory:
oBoot ROM, including HAB (96 KB)
oInternal multimedia / shared, fast access RAM (OCRAM, 256 KB)
oSecure/non-secure RAM (16 KB)
External memory interfaces:
o16-bit, 32-bit, and 64-bit DDR3-1066 and LV-DDR3-1066
o8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
oBA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 32 bit.
2.1.2. i.MX6 DMA Engine
The SDMA is multi-channel flexible DMA engine. It helps in maximizing system performance by off-
loading the various cores in dynamic data routing. It has the following features:
Powered by a 16-bit Instruction-Set micro-RISC engine
Multi-channel DMA supporting up to 32 time-division multiplexed DMA channels
48 events with total flexibility to trigger any combination of channels
Memory accesses including linear, FIFO, and 2D addressing
Shared peripherals between ARM and SDMA
Very fast Context-Switching with 2-level priority based preemptive multi-tasking
DMA units with auto-flush and prefetch capability
Flexible address management for DMA transfers (increment, decrement, and no address
changes on source and destination address)
DMA ports can handle unit-directional and bi-directional flows (copy mode)
Up to 8-word buffer for configurable burst transfers
Support of byte-swapping and CRC calculations
Library of Scripts and API is available

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 18 of 64
2.1.3. i.MX6 Video and Graphics Subsystems
The PICO-IMX6 video graphics subsystem consists of the following i.MX6 sub-blocks.
VPU: A multi-standard high performance video codec engine supporting encode/decode
operations of the following:
oDecoding: H.264 BP/CBP/MP/HP, VC-1 SP/MP/AP, MPEG-4 SP/ASP, H.263 P0/P3,
MPEG-1/2 MP, Divx (Xvid) HP/PP/HTP/HDP, VP8 (1280x720), AVS, H.264-MVC
(1280x720), MJPEG BP (max. 8192x8192) up to full-HD 1920x1088 @30fps plus D1
@30fps.
oEncoding: H.264 BP/CBP, MPEG-4 SP, H.263 P0/P3, MJPEG BP (max. 192x8192) up to
full-HD 1920x1088@30fps.
GPU2Dv2: Hardware acceleration of 2D graphics (Bit BLT and Stretch BLT). Based on the
Vivante GC320 IP core.
GPUVG: An OpenVG 1.1 Graphics Processing Unit providing hardware acceleration of vector
graphics. Based on the Vivante GC355 IP core
Additionally the PICO-IMX6 incorporates the following 3D GPU engine
The PICO-IMX6 featuring an i.MX6 Dual or Quad processor (Availability restrictions apply):
GPU3Dv4: A 3D GPU (Vivante GC2000), compliant with OpenGL ES2.0, OpenGL ES1.1 and
OpenVG 1.1.
The PICO-IMX6 featuring an i.MX6 Duallite or Solo processor:
GPU3Dv5: A 3D GPU (Vivante GC880), compliant with OpenGL ES2.0, OpenGL ES1.1 and
OpenVG 1.1.

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 19 of 64
2.2. Memory
The PICO-IMX6 integrates Double Data Rate III (DDR3) Synchronous DRAM in a single (32 bit) channel
configuration.
The following memory chips have been validated and tested on the PICO-IMX6 Compute Module:
2.2.1 SKHynix
SKHynix CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory
applications which requires large memory density and high bandwidth. SKHynix DDR3 SDRAMs offer
fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses
and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes
and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are
internally pipelined and 8-bit prefetched to achieve very high bandwidth.
SK Hynix memory features:
VDD=VDDQ=1.5V +/- 0.075V
Fully differential clock inputs (CK, CK) operation
Differential Data Strobe (DQS, DQS)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM masks write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
Programmable CAS latency 5, 6, 7, 8, 9, 10 and 11, 13 supported
Programmable additive latency 0, CL-1, and CL-2 supported
Programmable CAS Write latency (CWL) = 5, 6, 7, 8
Programmable burst length 4/8 with both nibble sequential and interleave mode
BL switch on the fly
8banks
Average Refresh Cycle (Tcase of 0o C~ 95 o C)
- 7.8 μs at 0 o C ~ 85 o C
- 3.9 μs at 85 o C ~ 95 o C
• Auto Self Refresh supported
JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA (x16)
Driver strength selected by EMRS
Dynamic On Die Termination supported
Asynchronous RESET pin supported
ZQ calibration supported
TDQS (Termination Data Strobe) supported (x8 only)
Write Levelization supported
8 bit pre-fetch
More information can be retrieved from SKHynix:
Part number:
H5TQ2G63FFR-PBC preferred part 2Gbit
H5TQ2G63DFR-H9C backup part 2Gbit
H5TQ4G63FFR-PBC preferred part 4Gbit
H5TQ4G63DFR-H9C backup part 4Gbit

PICO-IMX6 REV. A1. HARDWARE MANUAL –VER 1.01 –JAN 28 2016
Page 20 of 64
2.2.2. Micron
Micron 1.35V DDR3L SDRAM device is a low-voltage version of the 1.5V DDR3 SDRAM device. Unless
stated otherwise, the DDR3L SDRAM device meets the functional and timing specifications listed in the
equivalent density standard or automotive DDR3 SDRAM data sheet located on www.micron.com.
Micron memory features:
VDD = VDDQ = 1.35V (1.283–1.45V)
Backward-compatible to VDD = VDDQ = 1.5V ±0.075V
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
Programmable CAS (READ) latency (CL)
Programmable posted CAS additive latency (AL)
Programmable CAS (WRITE) latency (CWL)
Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self-refresh mode
TC of 0°C to +95°C
–64ms, 8192-cycle refresh at 0°C to +85°C
–32ms at +85°C to +95°C
Self-refresh temperature (SRT)
More information can be retrieved from Micron:
Part number:
MT41K128M16JT-125 IT:K for general configurations 2Gbit
MT41K256M16HA-125 IT:E for general configurations 4Gbit