TechNexion PICO-IMX6UL-EMMC User manual

PICO-IMX6UL-EMMC
PICO Compute Module with NXP i.MX6Ultralite SoC
REV. A1 –VER. 1.00
March 28, 2016

PICO-IMX6UL-EMMC REV. A1. HARDWARE MANUAL –VER 1.00 –MAR 28 2016
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REVISION HISTORY
Revision
Date
Originator
Notes
1.00
March 28, 2016
TechNexion
Initial Public release

PICO-IMX6UL-EMMC REV. A1. HARDWARE MANUAL –VER 1.00 –MAR 28 2016
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TABLE OF CONTENTS
1. Introduction .........................................................................................................................................7
1.1. General Introduction.....................................................................................................................7
1.2. General Care and Maintenance ...................................................................................................8
1.3. Block Diagram............................................................................................................................10
1.4. PICO Compute Module Compatibility.........................................................................................11
1.5. Dimensional Drawing..................................................................................................................12
1.6. Component Location ..................................................................................................................13
2. Core Components.............................................................................................................................14
2.1. NXP i.MX6Ultralite Cortex-A7 Processor...................................................................................14
2.2. Power Management IC (NXP PF3000) ......................................................................................15
2.2.1. NXP PF3000 Reset Signal ..................................................................................................15
2.3. Memory.......................................................................................................................................16
2.3.1 SK Hynix...............................................................................................................................16
2.3.2. Micron ..................................................................................................................................17
2.4. eMMC Storage ...........................................................................................................................18
2.4.1. Sandisk iNAND....................................................................................................................18
2.4.2. Kingston EMMC...................................................................................................................19
2.5. Broadcom BCM4339 WiFi/Bluetooth SiP Module......................................................................21
3. PICO Compute Module Connector Interfaces ..................................................................................24
3.1 Ethernet.......................................................................................................................................24
3.2. Digital Display Sub-System (DSS) or TTL Interface ..................................................................25
3.3. Audio Interface ...........................................................................................................................27
3.4. Universal Serial Bus (USB) Interface.........................................................................................28
3.5. CAN BUS Interface signals ........................................................................................................29
3.6. Universal Asynchronous Receiver/Transmitter (UART) Interface..............................................30
3.7. Serial Peripheral Interface (SPI).................................................................................................31
3.8. I2C Bus........................................................................................................................................32
3.9. General Purpose Input/Output (GPIO).......................................................................................33
3.10. Pulse Width Modulation (PWM) ...............................................................................................34
3.11. Manufacturing and Boot Control...............................................................................................35
3.11.1. Boot Modes........................................................................................................................35
3.12. Input Power Requirements.......................................................................................................36
3.12.1. Power Management Signals..............................................................................................36
3.12.2. Power Sequence ...............................................................................................................37
4. PICO Compute Module Pin Assignment...........................................................................................38
5. PICO Compute Module Pinmux Overview........................................................................................45
6. Development Kits, Proto-type Components and Accessories..........................................................48
6.1. PICO-IMX6UL-EMMC Evaluation Kits .......................................................................................48
6.1.1. PICO Evaluation Start Kit Pack Content..............................................................................48

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6.2. PICO Compatible Displays.........................................................................................................49
6.2.1. Multi Touch PCAP Displays.................................................................................................49
6.3. Accessories ................................................................................................................................50
6.3.1. EDMANTP150A138045D2450BK Pack Content.................................................................50
6.4. PICO Compute Module Product Ordering Part Numbers ..........................................................51
6.4.1 Standard Part Numbers........................................................................................................51
6.4.2. Custom Part Number Creation Rules..................................................................................52
7. Important Notice................................................................................................................................53
8. DISCLAIMER ....................................................................................................................................54

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LIST OF TABLES
Table 1 - PICO Compatibility Overview ................................................................................................11
Table 2 - PMIC Signal Description........................................................................................................15
Table 3 - PMIC Reset Signal Description .............................................................................................15
Table 4 - PMIC Reset Signal Description .............................................................................................15
Table 5 - eMMC Signal Description ......................................................................................................20
Table 6 - BCM4339 WiFi Signal Description.........................................................................................22
Table 7 - BCM4339 Bluetooth Signal Description ................................................................................23
Table 8 - Ethernet Signal Description ...................................................................................................24
Table 9 - TTL Display Signal Description..............................................................................................26
Table 10 - I2S Audio Signal Description................................................................................................27
Table 11 - USB Host Signal Description...............................................................................................28
Table 12 - USB OTG Signal Description...............................................................................................28
Table 13 - CAN Bus Signal Description................................................................................................29
Table 14 - UART Signal Description.....................................................................................................30
Table 15 - SPI Channel Signal Description...........................................................................................31
Table 16 - I2C Bus Signal Description...................................................................................................32
Table 17 - GPIO Signal Description......................................................................................................33
Table 18 - PWM Signal Description......................................................................................................34
Table 19 - Boot Selection Pins..............................................................................................................35
Table 20 - Serial Downloader Boot Mode Configuration ......................................................................35
Table 21 - Internal Downloader Boot Mode Configuration....................................................................35
Table 22 - Input Power Signals.............................................................................................................36
Table 23 - Power Management Signals................................................................................................36
Table 24 - Input Power Sequencing for AT based configurations ........................................................37

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LIST OF FIGURES
Figure 1 - PICO-IMX6UL-EMMC Block Diagram..................................................................................10
Figure 2 - PICO-IMX6UL-EMMC Compatibility Chart...........................................................................11
Figure 3 - PICO-IMX6UL-EMMC Dimensional Drawing .......................................................................12
Figure 4 - PICO-IMX6UL-EMMC Top view...........................................................................................13
Figure 5 - PICO-IMX6UL-EMMC Bottom view......................................................................................13
Figure 6 - NXP i.MX6Ultralite Processor Blocks...................................................................................14
Figure 7 - PICO-IMX6UL-EMMC Antenna u.FL Connector Location ...................................................21
Figure 8 - Input Power sequence for AT based configurations.............................................................37

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1. Introduction
1.1. General Introduction
The PICO-IMX6UL-EMMC is a high performance highly integrated PICO Compute Module designed
around the NXP i.MX6Ultralite ARM Cortex-A7. The PICO-IMX6UL-EMMC provides an ideal building
block that easily integrates with a wide range of target markets requiring compact, cost effective with
low power consumption.
The modular approach offered by the PICO Compute Module gives your project scalability, fast time
to market and upgradability while reducing engineering risk and maintain a competitive total cost of
ownership.

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1.2. General Care and Maintenance
Your device is a product of superior design and craftsmanship and should be treated with care.
The following suggestions will help you.
Keep the device dry. Precipitation, humidity, and all types of liquids or moisture can contain
minerals that will corrode electronic circuits. If your device does get wet, allow it to dry
completely.
Do not use or store the device in dusty, dirty areas. Its moving parts and electronic
components can be damaged.
Do not store the device in hot areas. High temperatures can shorten the life of electronic
devices, damage batteries, and warp or melt certain plastics.
Do not store the device in cold areas. When the device returns to its normal temperature,
moisture can form inside the device and damage electronic circuit boards.
Do not attempt to open the device.
Do not drop, knock, or shake the device. Rough handling can break internal circuit boards
and fine mechanics.
Do not use harsh chemicals, cleaning solvents, or strong detergents to clean the device.
Do not paint the device. Paint can clog the moving parts and prevent proper operation.
Unauthorized modifications or attachments could damage the device and may violate
regulations governing radio devices.
These suggestions apply equally to your device, battery, charger, or any enhancement. If any device
is not working properly, take it to the nearest authorized service facility for service.
Regulatory information
Disposal of Waste Equipment by Users in Private Household in the European Union
This symbol on the product or on its packaging indicates that this product must not be
disposed of with your other household waste. Instead, it is your responsibility to
dispose of your waste equipment by handing it over to a designated collection point
for the recycling of waste electrical and electronic equipment. The separate collection
and recycling of your waste equipment at the time of disposal will help to conserve
natural resources and ensure that it is recycled in a manner that protects human
health and the environment. For more information about where you can drop off your
waste equipment for recycling, please contact your local city office, your household waste disposal
service or the shop where you purchased the product.
We hereby declare that the product is in compliance with the essential requirements
and other relevant provisions of European Directive 1999/5/EC (radio equipment and
telecommunications terminal equipment Directive).

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Federal Communications Commission (FCC) Unintentional emitter per FCC Part
15
This device has been tested and found to comply with the limits for a Class B
digital device, pursuant to Part 15 of the FCC rules. These limits are designed to
provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses, and can radiate radio frequency
energy and, if not installed and used in accordance with the instructions, may
cause harmful interference to radio or television reception. However, there is no guarantee that
interference will not occur in a particular installation. If this equipment does cause interference to radio
and television reception, which can be determined by turning the equipment off and on, the user is
encouraged to try to correct the interference by one or more of the following measures:
■ Reorient or relocate the receiving antenna
■ Increase the separation between the equipment and receiver
■ Connect the equipment to an outlet on a different circuit from that to which the receiver is connected
■ Consult the dealer or an experienced radio/TV technician for help.
WARNING! To reduce the possibility of heat-related injuries or of overheating the
computer, do not place the computer directly on your lap or obstruct the computer
air vents. Use the computer only on a hard, flat surface. Do not allow another hard
surface, such as an adjoining optional printer, or a soft surface, such as pillows or
rugs or clothing, to block airflow. Also, do not allow the AC adapter to contact the
skin or a soft surface, such as pillows or rugs or clothing, during operation. The
computer and the AC adapter comply with the user-accessible surface temperature limits defined by
the International Standard for Safety of Information Technology Equipment (IEC 60950).

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1.3. Block Diagram
Figure 1 - PICO-IMX6UL-EMMC Block Diagram

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1.4. PICO Compute Module Compatibility
The PICO-IMX6UL-EMMC is function compatible with Intel®Edison and adds additional multimedia
I/O Interfaces on two additional expansion interfaces.
Many of the pins on PICO-IMX6UL-EMMC can be used for other functions. Chapter 5. PICO
Compute Module Pinmux Overview of this manual provides a complete overview.
Figure 2 - PICO-IMX6UL-EMMC Compatibility Chart
Table 1 - PICO Compatibility Overview
Interface
Description
LAN
1 Fast Ethernet
LVDS
Not available
HDMI
Not available
TTL Display
1 TTL 18/24 bit Display
PCIe
Not available
SATA
Not available
USB Host
1 USB 2.0 Host port
USB OTG
1 USB 2.0 OTG port (possible to use in Host mode)
I2S
1 I2S interface
CAN Bus
2 FlexCAN CAN 2.0B protocol compliant interfaces
UART
1 UART (2 wire)
1 UART (4 wire)
SDIO
Not available
SPI
1 SPI interface
I2C
3 independent I2C channels
GPIO
10 dedicated GPIO’s available
PWM
4 PWM available

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1.5. Dimensional Drawing
The PICO-IMX6UL-EMMC Compute Module is partly size compatible with Intel®Edison and adds
several additional I/O expansion interfaces on an enlarged footprint.
2D and 3D files can be obtained from the www.technexion.com homepage.
Figure 3 - PICO-IMX6UL-EMMC Dimensional Drawing

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1.6. Component Location
Figure 4 - PICO-IMX6UL-EMMC Top view
Item
Description
Item
Description
1
NXP i.MX6Ultralite Processor
2
Memory IC
3
NXP PF300 Power Management IC
4
BCM4339 WiFi/Bluetooth IC
5
Antenna connector
Figure 5 - PICO-IMX6UL-EMMC Bottom view
Item
Description
Item
Description
1
eMMC Storage IC
2
Intel® Edison Compatible Connector
3
Expansion Connector 1
4
Expansion Connector 2
1
2
3
4
1
3
2
4
5

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2. Core Components
2.1. NXP i.MX6Ultralite Cortex-A7 Processor
The i.MX 6UltraLite is an ultra-efficient processor family with featuring Freescale’s advanced
implementation of the single ARM Cortex®-A7 core, which operates at speeds of up to 528 MHz.
The device is composed of the following major subsystems:
oSingle-core ARM Cortex-A7 MPCore™Platform
o32 KBytes L1 Instruction Cache
o32 KBytes L1 Data Cache
oPrivate Timer and Watchdog
oTrustZone support
oCortex-A7 NEON MPE (Media Processing Engine) Co-processor
PXP—PiXel Processing Pipeline for imagine resize, rotation, overlay and CSC. Offloading key
pixel processing operations are required to support the LCD display applications.
Figure 6 - NXP i.MX6Ultralite Processor Blocks

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2.2. Power Management IC (NXP PF3000)
The PICO-IMX6UL-EMMC has on onboard NXP PF3000 power management integrated circuit
(PMIC) that features a configurable architecture supporting the numerous outputs with various current
ratings as well as programmable voltage and sequencing required by the components on the PICO-
IMX6UL-EMMC module.
Table 2 - PMIC Signal Description
CPU
BALL
CPU PAD
NAME
Pinmux (mode)
Signal
V
I/O
Description
L17
GPIO1_I
O03
i2c1.SDA
(mode0)
SDA
3V3
I/O
I2C bus data line
L14
GPIO1_I
O02
i2c1.SCL
(mode0)
SCL
3V3
I/O
I2C bus clock line
T9
SNVS_P
MIC_ON_
REQ
snvs_lp_wrapper.
PMIC_ON_REQ
(mode0)
PWRON
3V3
I
PMIC Power ON/OFF
Input from processor
P9
SNVS_TA
MPER4
gpio5.IO[4]
(mode5)
INT
3V3
I
PMIC Interupt Signal
P8
POR_B
src.POR_B
(mode0)
RESETBMC
U
3V3
I
PMIC Reset Signal
U9
CCM_PM
IC_STBY
_REQ
ccm.PMIC_VSTB
Y_REQ
(mode0)
STANDBY
3V3
I
PMIC Standby Input
Signal
2.2.1. NXP PF3000 Reset Signal
To perform a hard-reset of the PICO-IMX6UL-EMMC a software reset signal can be implemented.
Table 3 - PMIC Reset Signal Description
CPU
BALL
CPU PAD
NAME
Pinmux (mode)
Signal
V
I/O
Description
E9
LCD_RESET
lcdif.RESET
(mode0)
RESET
3V3
I
Connected to the
PWRON signal of PMIC
To perform a hard-reset of the PICO-IMX6UL-EMMC an external circuit (for example a button or
external watchdog IC) can be integrated on the carrier board.
Table 4 - PMIC Reset Signal Description
Connector
Signal
V
I/O
Description
E1_36
RESET
3V3
I
Connected to the PWRON signal of PMIC on the PICO
Compute Module.
Connected to the RESET Button on the Hobbitboard.

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2.3. Memory
The PICO-IMX6UL-EMMC integrates Double Data Rate III (DDR3) Synchronous DRAM in a single
(16 bit) channel configuration.
The following memory chips have been validated and tested on the PICO-IMX6UL-EMMC Compute
Module:
2.3.1 SK Hynix
SK Hynix low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main
memory applications which requires large memory density, high bandwidth and low power operation
at 1.35V.
SK Hynix DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling
edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK
(falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very
high bandwidth.
SK Hynix memory features:
VDD=VDDQ=1.35V + 0.100 / - 0.067V
Fully differential clock inputs (CK, CK) operation
Differential Data Strobe (DQS, DQS)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM masks write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the
rising edges of the clock
Programmable CAS latency 5, 6, 7, 8, 9, 10 and 11, 13 supported
Programmable additive latency 0, CL-1, and CL-2 supported
Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9
Programmable burst length 4/8 with both nibble sequential and interleave mode
BL switch on the fly
8banks
Average Refresh Cycle (Tcase of 0o C~ 95 o C)
- 7.8 μs at 0 o C ~ 85 o C
- 3.9 μs at 85 o C ~ 95 o C
Driver strength selected by EMRS
Dynamic On Die Termination supported
Asynchronous RESET pin supported
ZQ calibration supported
Write Levelization supported
8 bit pre-fetch
More information can be retrieved from SKHynix.

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2.3.2. Micron
Micron 1.35V DDR3L SDRAM device is a low-voltage version of the 1.5V DDR3 SDRAM device.
Unless stated otherwise, the DDR3L SDRAM device meets the functional and timing specifications
listed in the equivalent density standard or automotive DDR3 SDRAM data sheet located on
www.micron.com.
Micron memory features:
VDD = VDDQ = 1.35V (1.283–1.45V)
Backward-compatible to VDD = VDDQ = 1.5V ±0.075V
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
Programmable CAS (READ) latency (CL)
Programmable posted CAS additive latency (AL)
Programmable CAS (WRITE) latency (CWL)
Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self-refresh mode
TC of 0°C to +95°C
–64ms, 8192-cycle refresh at 0°C to +85°C
–32ms at +85°C to +95°C
Self-refresh temperature (SRT)
More information can be retrieved from Micron.

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2.4. eMMC Storage
The PICO-IMX6UL-EMMC can be ordered with onboard eMMC storage in different configurations and
capacity.
The onboard eMMC device is connected on the SD1 pins of the i.MX6Ultralite processor in an 8 bit
width configuration.
The following eMMC chips have been validated and tested on the PICO-IMX6UL-EMMC Compute
Module:
2.4.1. Sandisk iNAND
iNAND Ultra is an Embedded Flash Drive (EFD) designed for mobile handsets and consumer
electronic devices. iNAND Ultra is a hybrid device combining an embedded thin flash controller and
standard MLC NAND flash memory, with an industry standard e.MMC 4.511 interface. Empowered
with a new e.MMC4.51 feature set such as Power Off Notifications and Packed commands, as well as
legacy e.MMC4.41 features such as Boot and RPMB partitions, HPI, and HW Reset the iNAND Ultra
e.MMC is the optimal device for reliable code and data storage.
iNAND provides mass storage of up to 128GB in JEDEC compatible form factors, with low power
consumption and high performance.
In addition to the high reliability and high system performance, it offers plug-and-play integration and
support for multiple NAND technology transitions, as well as features such as advanced power
management scheme.
iNAND Ultra uses advanced Multi-Level Cell (MLC) NAND flash technology, enhanced by embedded
flash management software running as firmware on the flash controller.
The architecture and embedded firmware fully emulates a hard disk to the host processor, enabling
read/write operations identical to a standard, sector-based hard drive. In addition, SanDisk firmware
employs patented methods, such as virtual mapping, dynamic and static wear-levelling, and automatic
block management to ensure high data reliability and maximize flash life expectancy.
SanDisk iNAND Extreme, with MMC interface, features include the following:
Memory controller and NAND flash
Complies with e.MMC Specification Ver. 4.512
Mechanical design complies with JEDED MO-276C Specification
Offered in two TFBGA packages of e.MMC 4.513
Operating temperature range: -25C° to +85C°
Dual power system
Core voltage (VCC) 2.7-3.6v
I/O (VCCQ) voltage 2.7-3.6v
Supports three data bus widths: 1bit (default), 4bit, 8bit.
Variable clock frequencies of 0-20 MHz, 0-26 MHz (default), 0-52 MHz (high-speed)
Up to 104 MB/sec bus transfer rate, using 8 parallel data lines at 52 MHz, DDR Mode
Correction of memory field errors
Designed for portable and stationary applications that require high performance and reliable
data storage
More information can be retrieved from SanDisk.

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2.4.2. Kingston EMMC
Kingston e•MMC™ products follow the JEDEC e•MMC™ 4.5 standard. It is an ideal universal storage
solutions for many electronic devices, including smartphones, tablet PCs, PDAs, eBook readers,
digital
cameras, recorders, MP3, MP4 players, electronic learning products, digital TVs and set-top boxes.
E•MMC™ encloses the MLC NAND and e•MMC™ controller inside as one JEDEC standard package,
providing a standard interface to the host. The e•MMC™ controller directly manages NAND flash,
including ECC, wear-leveling, IOPS optimization and read sensing.
The Kingston NAND Device is fully compatible with the JEDEC Standard Specification No.JESD84-
B45.
This datasheet describes the key and specific features of the Kingston e•MMC™ Device. Any
additional
information required interfacing the Device to a host system and all the practical methods for device
detection and access can be found in the proper sections of the JEDEC Standard Specification.
Kingston e•MMC™, with MMC interface, features include the following:
Packaged NAND flash memory with e•MMC™ 4.5 interface
Compliant with e•MMC™ Specification Ver.4.4, 4.41 & 4.5
Bus mode
oHigh-speed e•MMC™ protocol
oProvide variable clock frequencies of 0-200MHz.
oTen-wire bus (clock, 1 bit command, 8 bit data bus) and a hardware reset.
Supports three different data bus widths : 1 bit(default), 4 bits, 8 bits
oData transfer rate: up to 52Mbyte/s (using 8 parallel data lines at 52 MHz)
oSingle data rate : up to 200Mbyte/s @ HS200(Host clock @ 200MHz)
oDual data rate : up to 104Mbyte/s @ 52MHz
Supports (Alternate) Boot Operation Mode to provide a simple boot sequence method
Supports SLEEP/AWAKE (CMD5).
Host initiated explicit sleep mode for power saving
Enhanced Write Protection with Permanent and Partial protection options
Supports Multiple User Data Partition with Enhanced User Data Area options
Supports Background Operations & High Priority Interrupt (HPI)
Supports enhanced storage media feature for better reliability
Operating voltage range :
oVCCQ = 1.8 V/3.3 V
oVCC = 3.3 V
Error free memory access
oInternal error correction code (ECC) to protect data communication
oInternal enhanced data management algorithm
oSolid protection of sudden power failure safe-update operations for data content
Security
oSupport secure bad block erase commands
oEnhanced write Protection with permanent and partial protection options
More information can be retrieved from Kingston.

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Table 5 - eMMC Signal Description
CPU
BALL
CPU PAD NAME
Pinmux
(mode)
Signal
V
I/O
Description
B3
SD1_DATA0
usdhc1.DATA0
(mode0)
eMMC_DATA0
3V3
I/O
MMC/SDIO Data bit 0
B2
SD1_DATA1
usdhc1.DATA1
(mode0)
eMMC_DATA1
3V3
I/O
MMC/SDIO Data bit 1
B1
SD1_DATA2
usdhc1.DATA2
(mode0)
eMMC_DATA2
3V3
I/O
MMC/SDIO Data bit 2
A2
SD1_DATA3
usdhc1.DATA3
(mode0)
eMMC_DATA3
3V3
I/O
MMC/SDIO Data bit 3
A3
NAND_READY_B
usdhc1.DATA4
(mode1)
eMMC_DATA4
3V3
I/O
MMC/SDIO Data bit 4
C5
NAND_CE0_B
usdhc1.DATA5
(mode1)
eMMC_DATA5
3V3
I/O
MMC/SDIO Data bit 5
B5
NAND_CE1_B
usdhc1.DATA6
(mode1)
eMMC_DATA6
3V3
I/O
MMC/SDIO Data bit 6
A4
NAND_CLE
usdhc1.DATA7
(mode1)
eMMC_DATA7
3V3
I/O
MMC/SDIO Data bit 7
C2
SD1_CMD
usdhc1.CMD
(mode0)
eMMC_CMD
3V3
I/O
MMC/SDIO
Command
C1
SD1_CLK
usdhc1.CLK
(mode0)
eMMC_CLK
3V3
O
MMC/SDIO Clock