Tektronix 7l5 User manual

-

COI\I\MITTED

TO

EXCELLENCE

WARNING

THE

FOLLOWING SERVICING INSTRUCTIONS ARE

FOR USE BY QUALIFIED PERSONNEL ONLY.

TO

AVOID PERSONAL INJURY, DO

NOT

PERFORM ANY

SERVICING OTHER

THAN

THAT

CONTAINED

IN

OPERATING INSTRUCTIONS UNLESS YOU ARE

QUALIFIED

TO

DO SO.

Tektronix, Inc.

P.O. Box 500

Beaverton, Oregon 97077

070·2

1

84

-01

7L5

SPECTRUM

ANALYZER

SERVICE

INSTRUCTION

MANUAL

Serial Number

_____

_

Flnl

Pr

I

nting

NOV

1

976

ScflIU

Iw

O"I3oUI'U-l)pdoIfS ".>

-

COMMITTED

TO

EXCELLENCE

WARNING

THE

FOLLOWING SERVICING INSTRUCTIONS ARE

FOR USE BY QUALIFIED PERSONNEL ONLY.

TO

AVOID PERSONAL INJURY, DO

NOT

PERFORM ANY

SERVICING OTHER

THAN

THAT

CONTAINED

IN

OPERATING INSTRUCTIONS UNLESS YOU ARE

QUALIFIED

TO

DO SO.

Tektronix, Inc.

P.O. Box 500

Beaverton, Oregon 97077

070

·2 18 4 -

01

7L5

SPECTRUM

ANALYZER

SERVICE

INSTRUCTION

MANUAL

Serial Number

_____

_

Flnl

Pr

i

nting

NOV

1976

SnlU

by

OIlDoMrc

e-Opd

OIfS

:z>

DIGITALY REMASTERED

OUT OF PRINT- MANUAL SCANS

By

Artek Media

18265 200th St.

Welch, MN 55089

www.artekmedia.com

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WARRANTY

Tektr

onix

warrants

that

this

product

is

freefrorn

defects

in

materials

and workmanship. The

warranty

period

is

one

(1) year

from

the

dale

of

s

hipment.

Te

ktr

onix

will.

at

its

option,

repair or

rep

lace

th

e

produc

t if

Tektronix

determines

it

is

defective

with

in

the

warranty

period

and

if

it

is

return

ed,

freight

prepaid

,

to

a

service

center

designated by

Tektronix

.

Tektr

onix

is

not

obl

igated

to

fur

nish service u

nder

this

warranty:

8.

to repair

damage

resulting from attempts by personnel other

than

Tektronix

representatives

to

install, repair,

or

servicethe

product

;

b. to repair

damage

r

esulting

from

imp

r

oper

use

or

from

connecting

the

product

to

incompat

ible

equipment

~

c.

if

personnel other

than

Tektronix

representatives

modify

the

hardw

are or software.

There

Is

no

impUed

warranty

ot

Illness

for

a

parllcular

purpose

.

Tektronix

is

not

liable

for

consequential damages.

Copyright

10

1976, 1978Tektr

onix

,IncoAil

rights

reserved.

Contents

of

this

publication

may

not

berepro

duced

in

any

form

without

the

written

permission of Tekt

ronix

,

Inc

.

Products of

Tektronix,

Inc

. and its subsidiaries are

covered by U.S. and fore

ign

patents and/

or

pending

patents.

TEKTRONIX, TEK,

SCOP

E-MOBILE

,

and

~

are reg-

istered

trademarks

of

Tektronix.

Inc. TELEQUIPMENT is

a registered

trademark

of

Tektronix

U.K. Lim

ite

d.

Printed in U.S.A. Speci

fication

and

price

change

privileges are reserved.

ScIl/lS bp Olll$ource-Oplions =>

WARRANTY

Tek

tronix

warrants

that

th

is

product

is

fr

ee

from

defects

in

ma

terials

and

workmanship.

T

he

warranty

period

is

o

ne

(1)

year

from

the

da

le

of sh

ip

ment.

Tektr

on

ix

will, at its option. repair

or

replace

th

e

product

if

Tektronix

dete

r

mines

it

is

defective

with

in

the

wa

rr

anty

period

and

if

it

is returned,

freight

prepaid.

to

a service center

designat

ed by

Tek

tr

on

ix

.

Tektronix is not obligat

ed

to furnish service under this warranty:

a.

to

repair

damage

r

esulting

from

attempts

by

personnel

other

tha

n T

ektro

nix

repr

esentatives

to

instal

l.

re

pair

,

or

servicethe

product

i

b. to repair damage resulting

from

Improper us r

from

connecting

the

product

to

incompatible

equipment

;

c.

if

personnel

olher

t

han

Tektr

onix

representa

lives

modify

the

har

dwa

re or soft

ware

.

There

i,

no

impUed

warranty

01

Illness

for

8 part

ic

ular

purpose

.

Tektronix

Is

not

liable

for

consequential damages.

Copyright

01976, 1978

Tektronix,

I

nco

Ali

rights

reserved.

Contentsol

this

publication

may

not

be

repr

od

uced

in

any

form

without

the

written

permission

of

Tektronix,

Inc

.

Pr

oducts

of

Tektronix

,

Inc

. and its

subsidia

ries

are

covered

by U.

S.

and

foreign

patents

and

/

or

pending

patents

.

T

EKT

RON

I

X,

TEK

,

SCO

PE-MOB

ILE,

and

'8

are

reg

-

ist

ered

trademarks

of

Tektronix,

In

c.

TELEQUI

PME

NT

is

a

registered

trademark

of

Tekt

r

onix

U.K.

Limi

ted.

Printed

in U.S.A.

Specif

i

cation

and

price

change

privileges

are reserved.

Scans bp OIl/Sollrce-OpliolfS

->

7L5 Service

TABLE

OF

CONTENTS

Page Page

SECTION 1 GENERAL INFORMATION SECTION 4 CALIBRATION PROCEDURE

Introduction and Description

1-1

Complete

or

Partial Calibration

4-1

Manual Organization 1-2 History Information

4-1

Electrical Characteristics 1-2 Interaction

4-1

Frequency 1-2 Equipment Required

4-1

Input

1-3 Short Form Procedure and Record 4-2

Amplitude 1-3 Preliminary Procedure 4-3

Sweep 1-4

1.

Check/Adjust the Reference

Output Connectors 1-4 Oscillator Frequency 4-6

Environmental Characteristics 1-5

2.

Check/Adjust the Calibrator

Physical Characteristics 1-5

Output

Level 4-6

Accessories and Options 1-5

3.

Frequency Span/Div Calibration 4-7

Installation 1-5

4.

Sweep Timing 4-9

Repackaging

for

Shipment 1-6

5.

1st LO and 1st LO Phase Lock

Calibration 4-10

SECTION 2 CIRCUIT DESCRIPTION

6.

Function IF Calibration

4-11

Block Diagrams

2-1

7.

Calibrate the

250

kHz, 2nd

IF Processing Chain

2-1

Mixer, and 10.7 MHz Input Filter 4-12

Sweep Control and Frequency

8.

Variable Resolution Calibration 4-13

Reference 2-2

9.

Digital Storage Calibration

Frequency Control Circuits 2-3 (SN B069999 and below) 4-16

Readout 2-5 9A. Digital Storage Calibration

Display Processing 2-6 (SN B070000 and up) 4-18

Detailed

Circuit

Description 2-7

Sweep Control 2-7 SECTION 5 MAINTENANCE

Trigger Logic and Sweep I

ntroduction

5-1

Control

2-11

Preventive Maintenance

Frequency Span and Readout 2-13

5-1

Tune Reference

+N

Loops 2-13 Cleaning

5-1

A&B Oscillator and Control 2-14 Lubrication 5-2

1st LO/1st LO Lock 2-15 Visual Inspection 5-2

Reference Level, Readout, and Transistor and Integrated

Timeslot 2-15

Circuit

Checks 5-2

Readout and Timeslot Decode 2-18 Troubleshooting 5-2

IF Processing Chain 2-19 Troubleshooting Aids 5-2

Variable Resolution 2-20 Finding Faulty Semiconductors 5-3

10

kHz &

30

kHz Filters and General Troubleshooting

Post

VR

Amplifier 2-22 Techniques 5-5

Corrective Maintenance 5-5

Log/Lin

Amplifier 2-22 Disassembly

of

the 7L5 and

Detector and Video Amplifier 2-22 Replacing Assemblies

Display Processing 2-23 5-7

Horizontal and Vertical Display Removing the Front Panel 5-7

Removing the IF Module

Processing 2-23 Assembly 5-7

Average Calculator (SN B069999 Removing the Sweep Board 5-8

and below) 2-24 Removing the

RF

Module 5-9

Digital Storage (SN B069999 Reassembling the 7L5 5-9

and below) 2-25

Digital Storage and Averaging Internal Operational Adjustments 5-9

(SN B070oo0 and up) 2-30 SECTION 6 OPTION INFORMATION

SECTION 3 PERFORMANCE CHECK

Introduction

3-1

SECTION 7 REPLACEABLE ELECTRICAL

Equipment Required

or

PARTS

Recommended

3-1

1.

Sweep Triggering 3-2 SECTION 8 DIAGRAMS AND CIRCUIT

2.

Dot Frequency Range and BOARD ILLUSTRATIONS

Accuracy 3-2

3.

Display Flatness 3-3 SECTION 9 REPLACEABLE MECHANICAL

4.

Frequency Span Accuracy & PARTS AND EXPLODED

Linearity 3-4 DRAWINGS

5.

Sweep Rate Accuracy 3-5 CHANGEINFORMATION

6.

Intermodulation Distortion 3-6

7.

Display Frequency St!ibility 3-7

REV.

A MAY 1978

7L5 Service

TABLE

OF

CONTENTS

Page Page

SECTION 1 GENERAL INFORMATION SECTION 4 CALIBRATION PROCEDURE

Introduction and Description

1-1

Complete

or

Partial Calibration

4-1

Manual Organization 1-2 History Information

4-1

Electrical Characteristics 1-2 Interaction

4-1

Frequency 1-2 Equipment Required

4-1

Input

1-3 Short Form Procedure and Record 4-2

Amplitude 1-3 Preliminary Procedure 4-3

Sweep 1-4

1.

Check/Adjust the Reference

Output Connectors 1-4 Oscillator Frequency 4-6

Environmental Characteristics 1-5

2.

Check/Adjust the Calibrator

Physical Characteristics 1-5

Output

Level 4-6

Accessories and Options 1-5

3.

Frequency Span/Div Calibration 4-7

Installation 1-5

4.

Sweep Timing 4-9

Repackaging

for

Shipment 1-6

5.

1st LO and 1st LO Phase Lock

Calibration 4-10

SECTION 2 CIRCUIT DESCRIPTION

6.

Function IF Calibration

4-11

Block Diagrams

2-1

7.

Calibrate the

250

kHz, 2nd

IF Processing Chain

2-1

Mixer, and 10.7 MHz Input Filter 4-12

Sweep Control and Frequency

8.

Variable Resolution Calibration 4-13

Reference 2-2

9.

Digital Storage Calibration

Frequency Control Circuits 2-3 (SN B069999 and below) 4-16

Readout 2-5 9A. Digital Storage Calibration

Display Processing 2-6 (SN B070000 and up) 4-18

Detailed

Circuit

Description 2-7

Sweep Control 2-7 SECTION 5 MAINTENANCE

Trigger Logic and Sweep Introduction

5-1

Control

2-11

Preventive Maintenance

Frequency Span and Readout 2-13

5-1

Tune Reference

+N

Loops 2-13 Cleaning

5-1

A&B Oscillator and Control 2-14 Lubrication 5-2

1st LO/1st LO Lock 2-15 Visual Inspection 5-2

Reference Level, Readout, and Transistor and Integrated

Timeslot 2-15

Circuit

Checks 5-2

Readout and Timeslot Decode 2-18 Troubleshooting 5-2

IF Processing Chain 2-19 Troubleshooting Aids 5-2

Variable Resolution 2-20 Finding Faulty Semiconductors 5-3

10

kHz &

30

kHz Filters and General Troubleshooting

Post

VR

Amplifier 2-22 Techniques 5-5

Corrective Maintenance 5-5

Log/Lin

Amplifier 2-22 Disassembly

of

the 7L5 and

Detector and Video Amplifier 2-22 Replacing Assemblies

Display Processing 2-23 5-7

Horizontal and Vertical Display Removing the Front Panel 5-7

Removing the IF Module

Processing 2-23 Assembly 5-7

Average Calculator (SN B069999 Removing the Sweep Board 5-8

and below) 2-24 Removing the

RF

Module 5-9

Digital Storage (SN B069999 Reassembling the 7L5 5-9

and below) 2-25

Digital Storage and Averaging Internal Operational Adjustments 5-9

(SN B070oo0 and up) 2-30 SECTION 6 OPTION INFORMATION

SECTION 3 PERFORMANCE CHECK

Introduction

3-1

SECTION 7 REPLACEABLE ELECTRICAL

Equipment Required

or

PARTS

Recommended

3-1

1.

Sweep Triggering 3-2 SECTION 8 DIAGRAMS AND CIRCUIT

2.

Dot Frequency Range and BOARD ILLUSTRATIONS

Accuracy 3-2

3.

Display Flatness 3-3 SECTION 9 REPLACEABLE MECHANICAL

4.

Frequency Span Accuracy & PARTS AND EXPLODED

Linearity 3-4 DRAWINGS

5.

Sweep Rate Accuracy 3-5 CHANGEINFORMATION

6.

Intermodulation Distortion 3-6

7.

Display Frequency St!ibility 3-7

REV.

A MAY 1978

"-

I

--

So!

-

I

...

-

...

-

173

4-1 A

Fig. 1-1.

7LS

Spectrum

An.'yzer,

I 7L5 Service

REV

A,

MAY

1

978

Sc

allS

by

OlltsDllrce-()DlioIl

S->

Fig. 1

-1

. 7LS

Spectrum

Analyter

.

7L5 Service

..

-

REV A,

MAY

19

78

Sc.1U

bp

OM""UN:t-()pt;OIlS

.,.

7L5 Service

GENERAL

INFORMATION

INTRODUCTION

AND

DESCRIPTION

To

effectively use the 7L5 Spectrum Analyzer, the

operation and capabilities of the instrument must

be

known. This instruction manual covers general service

information

for

the instrument. It contains the specifica-

tion, test and calibration procedure,

circuit

description,

and maintenance procedure

for

the 7L5.

The 7L5

is

a 5 MHz spectrum analyzer with digital

storage. Frequency stability is within 5

Hz/hr

and center

frequency (dot) can be read with six

digit

accuracy

immediately after turn-on; therefore there

is

no need

to

fine tune the display. Complex measurements and

analysis can

be

made with relative ease. Built-in

microprocessingcircuitsdecodecontrol settings, process

frequency and reference level information, and optimize

sweep time and resolution

for

the selected frequency

span. At turn-on, the 7L5

is

preset

to

a reference level of

+17

dBm (50 °input) and center frequency

of

00.0

kHz:

This provides

input

attenuation to protect the front-end

circuitry

and a marker

to

verify correct operation.

The 7L5 with 80

dB

or

more

of

spurious free dynam'ic

range provides the ability

to

measure wide relative

amplitudes. Nanovolt sensitivity provides very low-level

signal and noise requirements.

The 7L5 display is

fully

calibrated in dBm, dBV,

or

volts/div. The reference level can beaccuratelyset in 1

dB

increments.

A

front

panel

input

buffer control increases front-end

immunity

to

intermodulation distortion while maintaining

a constant reference level.

@

To

accommodate a wide variety ofimpedancesources,

the 7L5 uses quick disconnect plug-in

input

impedance

modules of

50

0,

75

0,

600

0,

1 MO/28 pF and customiz-

ed

units

to

meet special requirements.

When the

7L5'sdigital

storage capability is employed,

one

or

two

complete displays can

be

held in memory

for

subsequent viewing, comparison,

or

graphic reproduc-

tion. This capability converts a nonstorage, 7000-Series

oscilloscope display

into

a stored display. The small

dot

size (of the conventional oscilloscope) used with the 7L5

enhances the resolution of low amplitude signals and

other

fine details that are often lost with a variable

persistence oscilloscope. In storage mode, the vertical

display may be bisected by

an

averaging threshold, above

which video peak detection occurs (prior

to

storage) and

below which video signal averaging occurs

(prior

to

storage). Denoted by a cursor, the averaging threshold is

continuously

adjustable with a

front

panel control. The

storage

circuitry

includes a maximum hold capability.

This feature allows monitoring

of

signals thatmaychange

with time

to

provide a graphic record

of

amplitude/fre-

quency

excursion.

WARNING

I

The

following

service

instructions

are

for

personnel

qualified

toservice

electronic

circuits. Personnel

not

familiar

with

electrical

circuit

operation

should

not

perform

any

service

other

than that

contained

in the

Operating

Instuction

manual.

1-1

7L5 Service

GENERAL

INFORMATION

INTRODUCTION

AND

DESCRIPTION

To

effectively use the 7L5 Spectrum Analyzer, the

operation and capabilities of the instrument must

be

known. This instruction manual covers general service

information

for

the instrument. It contains the specifica-

tion, test and calibration procedure,

circuit

description,

and maintenance procedure

for

the 7L5.

The 7L5

is

a 5 MHz spectrum analyzer with digital

storage. Frequency stability is within 5

Hz/hr

and center

frequency (dot) can be read with six

digit

accuracy

immediately after turn-on; therefore there

is

no need

to

fine tune the display. Complex measurements and

analysis can

be

made with relative ease. Built-in

microprocessingcircuitsdecodecontrol settings, process

frequency and reference level information, and optimize

sweep time and resolution

for

the selected frequency

span. At turn-on, the 7L5

is

preset

to

a reference level of

+17

dBm (50 °input) and center frequency

of

00.0

kHz:

This provides

input

attenuation to protect the front-end

circuitry

and a marker

to

verify correct operation.

The 7L5 with 80

dB

or

more

of

spurious free dynam'ic

range provides the ability

to

measure wide relative

amplitudes. Nanovolt sensitivity provides very low-level

signal and noise requirements.

The 7L5 display is

fully

calibrated in dBm, dBV,

or

volts/div. The reference level can beaccuratelyset in 1

dB

increments.

A

front

panel

input

buffer control increases front-end

immunity

to

intermodulation distortion while maintaining

a constant reference level.

@

To

accommodate a wide variety ofimpedancesources,

the 7L5 uses quick disconnect plug-in

input

impedance

modules of

50

0,

75

0,

600

0,

1 MO/28 pF and customiz-

ed

units

to

meet special requirements.

When the

7L5'sdigital

storage capability is employed,

one

or

two

complete displays can

be

held in memory

for

subsequent viewing, comparison,

or

graphic reproduc-

tion. This capability converts a nonstorage, 7000-Series

oscilloscope display

into

a stored display. The small

dot

size (of the conventional oscilloscope) used with the 7L5

enhances the resolution of low amplitude signals and

other

fine details that are often lost with a variable

persistence oscilloscope. In storage mode, the vertical

display may be bisected by

an

averaging threshold, above

which video peak detection occurs (prior

to

storage) and

below which video signal averaging occurs

(prior

to

storage). Denoted by a cursor, the averaging threshold is

continuously

adjustable with a

front

panel control. The

storage

circuitry

includes a maximum hold capability.

This feature allows monitoring

of

signals thatmaychange

with time

to

provide a graphic record

of

amplitude/fre-

quency

excursion.

WARNING

I

The

following

service

instructions

are

for

personnel

qualified

toservice

electronic

circuits. Personnel

not

familiar

with

electrical

circuit

operation

should

not

perform

any

service

other

than that

contained

in the

Operating

Instuction

manual.

1-1

General

Information-7L5

Service

MANUAL

ORGANIZATION

AND

CONTENT

The

abbreviations,

graphic

symbols, and

logic

sym-

bology

used in

the

text

and

diagrams

of

this

manual are in

accord

with

and based

on

ANSI Y1.1-1972, ANSI Y 32.3-

1975,

and

ANSI Y32.14-1973

(American

National

Standard

Institute, 345 East 47 Street;

New

York, N.Y. 10017).

Change

information

is

contained

on

insert pages

at

the

back

of

the

manual.

Original

pages are

identified

by

the

symbol

@ and revised pages are

identifed

by

a revision

date

in

the

lower

inside

corner

of

the page.

If

the

serial

number

of

your

instrument

is

lower

than

the

one

on

the

title

page,

the

manual

contains

revisions

that

may

not

apply

to

your

instrument.

History

information,

applicable

to

with

the

updated

data, is

integrated

when

the

page

or

diagram

is revised.

The

following

describes

the

sections

and

information

provided

in

this

manual.

Section

1-General

Information:

Contains

the

instru-

ment

description

and

specification.

Section

2-Circuit

Description:

Provides basic and

general

circuit

theory.

This

information

may

be useful

when

servicing

or

operating

the

instrument.

Section

3-Performance

Check:

Procedures

to

verify

that

the

instrument

is

performing

within

its

specified

limits.

Section

4-Calibration

Procedure:

Test

equipment

setup and

adjustment

procedures

required

to

calibrate

the

instrument.

Section

5-Maintenance:

Describes

routine

and

cor-

rective

maintenance

procedures

with

detailed

instructions

for

replacing assemblies, sub-assemblies,

or

individual

components.

An

exploded

drawing

is

part

of

Section

9.

Troubleshooting

procedures

plus

general

information

that

may

aid in

servicing

the

instrument

arealso provided.

Section

6-0ptions

Information:

Describes

options

to

the

instrument or

directs

the

reader

to

where

the

options

are

documented.

Section

7-Replaceable

Electrical

Parts: Provides

in-

formation

necessary

to

order

replaceable parts and

assemblies.

1-2

Section

8-Diagrams:

Functional

block

diagrams

and

detailed

circuit

schematics

are

provided.

Located

adja-

cent

to

the

diagram

(usually

on

the

back

of

the

preceding

diagram)

are

pictorial

layout

drawings

that

show

sub-

assembly and

component

locations.

Integrated

circuit

diagrams,

waveforms

and

voltage

data

for

troubleshooting

or

circuit

analysis are also

provided

adjacent

to

or

on

the

diagram.

Section

9-Replaceable

Mechanical

Parts, Exploded

Drawings

and Accessories: Provides

information

necessary

to

order

replaceable parts.

The

Replaceable

Parts

list

is

cross-referenced

to

the Replaceable Electrical

Parts list.

The

exploded

drawing

identifies

assembliesand

mechanical

components.

Change

Information:

Provides

updating

information

in

the

form

of

inserts

for

the

manual. These inserts are later

incorporated

into

the

manual

text

and

diagrams

when

the

manual is reprinted.

ELECTRICAL

CHARACTERISTICS

The

following

electrical

characterstics

apply

when

the

7L5

Spectrum

Analyzer, in

combination

with

a

Plug-In

Module,

are

normally

installed in a 7000-Series

os-

cilloscope

and

after

a

warm-up

of

ten

minutes

or

more.

Frequency Characteristics

Range

Input

Frequency: 10 Hz

through

5.0 MHz.

Dot

Frequency: 0

Hz

through

4999.75 kHz.

Accuracy

20°C

to

30°C:

±(5

Hz +2 X 10-6

of

dot

readout).

O°C

to

50°C:

±(20

Hz +

lO-

l

of

dot

readout).

Drift

5

Hz/hour

or

less.

Residual (Incidental) FM

50

Hz/div

to

2

kHz/div:

1 Hz (p-p)

or

less.

5

kHz/div

to 500

kHz/div:

40 Hz (p-p)

or

less.

@

Scans

by

Ollbollrce-Options =>

General

Information-7L5

Service

MANUAL

ORGANIZATION

AND

CONTENT

The

abbreviations,

graphic

symbols, and

logic

sym-

bology

used in

the

text

and

diagrams

of

this

manual are in

accord

with

and based

on

ANSI Y1.1-1972, ANSI Y 32.3-

1975,

and

ANSI Y32.14-1973

(American

National

Standard

Institute, 345 East 47 Street;

New

York, N.Y. 10017).

Change

information

is

contained

on

insert pages

at

the

back

of

the

manual.

Original

pages are

identified

by

the

symbol

@ and revised pages are

identifed

by

a revision

date

in

the

lower

inside

corner

of

the page.

If

the

serial

number

of

your

instrument

is

lower

than

the

one

on

the

title

page,

the

manual

contains

revisions

that

may

not

apply

to

your

instrument.

History

information,

applicable

to

with

the

updated

data, is

integrated

when

the

page

or

diagram

is revised.

The

following

describes

the

sections

and

information

provided

in

this

manual.

Section

1-General

Information:

Contains

the

instru-

ment

description

and

specification.

Section

2-Circuit

Description:

Provides basic and

general

circuit

theory.

This

information

may

be useful

when

servicing

or

operating

the

instrument.

Section

3-Performance

Check:

Procedures

to

verify

that

the

instrument

is

performing

within

its

specified

limits.

Section

4-Calibration

Procedure:

Test

equipment

setup and

adjustment

procedures

required

to

calibrate

the

instrument.

Section

5-Maintenance:

Describes

routine

and

cor-

rective

maintenance

procedures

with

detailed

instructions

for

replacing assemblies, sub-assemblies,

or

individual

components.

An

exploded

drawing

is

part

of

Section

9.

Troubleshooting

procedures

plus

general

information

that

may

aid in

servicing

the

instrument

arealso provided.

Section

6-0ptions

Information:

Describes

options

to

the

instrument or

directs

the

reader

to

where

the

options

are

documented.

Section

7-Replaceable

Electrical

Parts: Provides

in-

formation

necessary

to

order

replaceable parts and

assemblies.

1-2

Section

8-Diagrams:

Functional

block

diagrams

and

detailed

circuit

schematics

are

provided.

Located

adja-

cent

to

the

diagram

(usually

on

the

back

of

the

preceding

diagram)

are

pictorial

layout

drawings

that

show

sub-

assembly and

component

locations.

Integrated

circuit

diagrams,

waveforms

and

voltage

data

for

troubleshooting

or

circuit

analysis are also

provided

adjacent

to

or

on

the

diagram.

Section

9-Replaceable

Mechanical

Parts, Exploded

Drawings

and Accessories: Provides

information

necessary

to

order

replaceable parts.

The

Replaceable

Parts

list

is

cross-referenced

to

the Replaceable Electrical

Parts list.

The

exploded

drawing

identifies

assembliesand

mechanical

components.

Change

Information:

Provides

updating

information

in

the

form

of

inserts

for

the

manual. These inserts are later

incorporated

into

the

manual

text

and

diagrams

when

the

manual is reprinted.

ELECTRICAL

CHARACTERISTICS

The

following

electrical

characterstics

apply

when

the

7L5

Spectrum

Analyzer, in

combination

with

a

Plug-In

Module,

are

normally

installed in a 7000-Series

os-

cilloscope

and

after

a

warm-up

of

ten

minutes

or

more.

Frequency Characteristics

Range

Input

Frequency: 10 Hz

through

5.0 MHz.

Dot

Frequency: 0

Hz

through

4999.75 kHz.

Accuracy

20°C

to

30°C:

±(5

Hz +2 X 10-6

of

dot

readout).

O°C

to

50°C:

±(20

Hz +

lO-

l

of

dot

readout).

Drift

5

Hz/hour

or

less.

Residual (Incidental) FM

50

Hz/div

to

2

kHz/div:

1 Hz (p-p)

or

less.

5

kHz/div

to 500

kHz/div:

40 Hz (p-p)

or

less.

@

Scans

by

Ollbollrce-Options =>

Resolution Bandwidth

Accuracy

30

kHz-30

Hz:

Within

20%ofselected

resolution

(6

dB

down).

10

Hz:

Within

100 Hz

±20

Hz (70

dB

down).

The

COUPLED

setting

electronically

selects

the best

resolution

bandwidth

for

each

setting

of

the

FREQUENCY

SPAN/DIV

control.

Shape

Factor

30

kHz-3

kHz:

5:1

or

better

(60:6

dB

ratio).

1

kHz-10

Hz:

10:1

or

better

(60:6

dB

ratio).

Amplitude

Deviation

30

kHz-100

Hz: 0.5

dB

or

less.

30

kHz-10

Hz: 2.0

dB

or

less.

Input Characteristics

~

The

application

of

a

dc

voltage to the

INPUT

of

the

L1

or

L2

Plug-In

Modules

may

cause

permanent

damage to the

mixer

circuit.

Input Impedance (Nominal):

L1

500

L2

750

L3 Selectable (50

0,

600

0,

and

1

MO/28

pF).

Input Power

(maximum

input

level

for

reference levels

of

0

dBm

or

greater):

L1

21

dBm

or

2.5 V rms

L2

21

dBm

or

3.07 V rms

L3

21

dBm-input

terminated

50 0

or

6000;

100 V (peak ac +

dc)

input

1

MO/28

pF.

Input Power

(maximum

input

level

for

reference levels

below

0

dBm):

L1

+10

dBm

L2

+10

dBm

L3

+10

dBm-input

terminated

500

or

600

0,

and 100 V (peak ac +

dc)

with

input

of

1

MO/28

pF.

@

Generallnformation-7L5

Service

Amplitude Characteristics

NOTE

If

digital

storage

is used, an

additional

quantization

error

of

0.5%

of

full

screen

should

be

added

to the

amplitude

characteristics.

Residual Response

Internally

generated

spurious

signalsare

-130

dBm

or

less referred

to

the

input

(harmonics

of

the

calibrator

are

-125

dBm)

with

L1

or

L2

plug-in

module

and

-143

dBV

with

the

L3

plug-in

module.

Sensitivity

The

following

tabulation

of

equivalent

input

noise

for

each

resolution

bandwidth

is measured

with;

the

INPUT

BUFFER off, the

VIDEO

PEAK/AVG

at

max

cw,

and

the

TIME/DIV

set

to

10 seconds.

Equivalent Input Noise

Resolution (equal

to

or

better than)

Bandwidth

L1

L2

L3

10 Hz

-135

dBm

-135

dBm

-148

dBV

30 Hz

-133

dBm

-133

dBm

-146

dBV

100 Hz

-130

dBm

-130

dBm

-143

dBV

300

Hz

-125

dBm

-125

dBm

-138

dBV

1

kHz

-120

dBm

-120

dBm

-133

dBV

3

kHz

-115

dBm

-115

dBm

-128

dBV

10 kHz

-110

dBm

-110dBm

-123

dBV

30

kHz

-105

dBm

-105

dBm

-118

dBV

NOTE

Sensitivity

is

degraded

an

additional

8

dB

when the

INPUT

BUFFER is on; e.g.,

at

3 kHz, the

equivalent

input

nOise

would

be

-107

dBm

instead

of

-115

dBm. Noise level

will

increase

by

ap-

proximately

10

dB

when

operation

is in video

peak

mode.

Intermodulation Distortion

Intermodulation

products

from

two

on-screen

signals,

within

any

frequency

span are

?75

dB

down

for

third

order

products

and

at

least 72

dB

down

for

second

order

products.

Second

and

third

order

intermodulation

products

from

two

on-screen

-53

dBV

or

less

signals

within

any

frequency

span are at least 80

dB

down.

1-3

Scans

by

O"tso",ce-Options =>

Resolution Bandwidth

Accuracy

30

kHz-30

Hz:

Within

20%ofselected

resolution

(6

dB

down).

10

Hz:

Within

100 Hz

±20

Hz (70

dB

down).

The

COUPLED

setting

electronically

selects

the best

resolution

bandwidth

for

each

setting

of

the

FREQUENCY

SPAN/DIV

control.

Shape

Factor

30

kHz-3

kHz:

5:1

or

better

(60:6

dB

ratio).

1

kHz-10

Hz:

10:1

or

better

(60:6

dB

ratio).

Amplitude

Deviation

30

kHz-100

Hz: 0.5

dB

or

less.

30

kHz-10

Hz: 2.0

dB

or

less.

Input Characteristics

~

The

application

of

a

dc

voltage to the

INPUT

of

the

L1

or

L2

Plug-In

Modules

may

cause

permanent

damage to the

mixer

circuit.

Input Impedance (Nominal):

L1

500

L2

750

L3 Selectable (50

0,

600

0,

and

1

MO/28

pF).

Input Power

(maximum

input

level

for

reference levels

of

0

dBm

or

greater):

L1

21

dBm

or

2.5 V rms

L2

21

dBm

or

3.07 V rms

L3

21

dBm-input

terminated

50 0

or

6000;

100 V (peak ac +

dc)

input

1

MO/28

pF.

Input Power

(maximum

input

level

for

reference levels

below

0

dBm):

L1

+10

dBm

L2

+10

dBm

L3

+10

dBm-input

terminated

500

or

600

0,

and 100 V (peak ac +

dc)

with

input

of

1

MO/28

pF.

@

Generallnformation-7L5

Service

Amplitude Characteristics

NOTE

If

digital

storage

is used, an

additional

quantization

error

of

0.5%

of

full

screen

should

be

added

to the

amplitude

characteristics.

Residual Response

Internally

generated

spurious

signalsare

-130

dBm

or

less referred

to

the

input

(harmonics

of

the

calibrator

are

-125

dBm)

with

L1

or

L2

plug-in

module

and

-143

dBV

with

the

L3

plug-in

module.

Sensitivity

The

following

tabulation

of

equivalent

input

noise

for

each

resolution

bandwidth

is measured

with;

the

INPUT

BUFFER off, the

VIDEO

PEAK/AVG

at

max

cw,

and

the

TIME/DIV

set

to

10 seconds.

Equivalent Input Noise

Resolution (equal

to

or

better than)

Bandwidth

L1

L2

L3

10 Hz

-135

dBm

-135

dBm

-148

dBV

30 Hz

-133

dBm

-133

dBm

-146

dBV

100 Hz

-130

dBm

-130

dBm

-143

dBV

300

Hz

-125

dBm

-125

dBm

-138

dBV

1

kHz

-120

dBm

-120

dBm

-133

dBV

3

kHz

-115

dBm

-115

dBm

-128

dBV

10 kHz

-110

dBm

-110dBm

-123

dBV

30

kHz

-105

dBm

-105

dBm

-118

dBV

NOTE

Sensitivity

is

degraded

an

additional

8

dB

when the

INPUT

BUFFER is on; e.g.,

at

3 kHz, the

equivalent

input

nOise

would

be

-107

dBm

instead

of

-115

dBm. Noise level

will

increase

by

ap-

proximately

10

dB

when

operation

is in video

peak

mode.

Intermodulation Distortion

Intermodulation

products

from

two

on-screen

signals,

within

any

frequency

span are

?75

dB

down

for

third

order

products

and

at

least 72

dB

down

for

second

order

products.

Second

and

third

order

intermodulation

products

from

two

on-screen

-53

dBV

or

less

signals

within

any

frequency

span are at least 80

dB

down.

1-3

Scans

by

O"tso",ce-Options =>

General

Information-7L5

Service

With the INPUT BUFFER switch on, the

third

order

intermodulation

products,

for

any

two

on-screen

signals,

within

any

frequency

span, are at least 80 dB

down.

Display Flatness

Peak

to

peak deviation, over any selected frequency

span: Quantization

error

must be added (see Note

under

Amplitude

Characteristics) if

digital

storage is used.

L1

L2

L3

0.5 dB;

Reference Level

Refers to top

graticule

line in Log mode. Calibrated in

1

dB

and 10

dB

steps

for

the L1 and L2 modules and

1

dB/2

dB

and

10

dB

for

L3

plug-in

module.

Range

L1

L2 L3

Log

-128

dBm

-128

dBm/

-128

dBm

to

2

dB/Div

to

+21

dBm

139

dBV

to

+21

dBm

(50

0),

+21

dBm/

-139

dBm

to

+10

dBV

+10dBm(600

0),

-141

dBV

to

+8

dBV (Hi Z)

Log

-70

dBm

-70

dBm/

-70

dBm

to

10

dB/Div

to

+21

dBm

-81

dBV

to

+21

dBm

(50

0),

+21

dBm/

-81

dBm

to

+10

dBV

+10dBm

(6000),

-83

dBV

to

+8

dBV (Hi Z)

Incremental

Accuracy

When calibrated at

-40

dBV in Log mode:

L

1,

L2

and L3: Within0.2

dB/dB

with cumulative

errorof

0.25

dB/10

dB.

Lin Mode Range:

20

mV/Div

to

200

mV/Divwithin

5%in

1-2-5 sequence.

NOTE

A

>sign

is

displayed

adjacent

to the reference level

readout

when the reference level

is

not

calibrated

due

to an

incompatible

selection

of

controls.

Display

Dynamic

Range/Accuracy

Log 10

dB/Div

Mode:

Dynamic

window

is

80

dB.

Accuracy

is

within

0.05

dB/dB

to

2

dB

maximum.

Log 2

dB/Div

Mode: Dynamic

window

is 16 dB.

Ac-

curacy

is

within

0.1

dB/dB

to

1

dB

maximum.

1-4

Sweep

Characteristics

Frequency Span. Provides calibrated

frequency

spans

from

50

Hz/div

to

maximum

500 kHz/div,

within

4%,

in

1-2-

5 sequence.

Horizontal linearity is

within

4%

over

the

entire 10 div

display.

A O-Hz/Div position is provided

for

time

domain

operation.

Sweep Rate.

Time

per div is selectable from 10

s/div

to

0.1

ms/div

in a 1-2-5sequence. An

AUTO

position permits

automatic selection of

optimum

time/div

for

the selected

resolution and span/div.

Sweep rate

accuracy

is

within

5%

of

the rate selected.

Triggering.

Provides

two

triggering

sources,

INT

(inter-

nal) and LINE, in

addition

to

a FREE-RUN position.

When

INT

is selected, ac

coupled

signal

components

from the mainframe

Trigger

Source (left

or

right vertical

amplifiers) are used.

When LINE is selected, ac

coupled

sample

of

main-

frame line voltage is used.

Three

triggering

modes are; NORM (normal), SGL

SWP/READY (single sweep), and

MNL

SWEEP (manual

sweep).

Trigger

level is

~1.0

div

of

internal signal

for

both

NORM

and

SGL

SWP modes over the approximate

frequency

range of

30

Hz

to

500 kHz.

Output

Connectors

Video Out. Front-panel pin jack

connector

suppliesthe

video (vertical)

output

signal at an

amplitude

of

50

mV/div

±5%

(about the

crt

vertical center) with

source

impedance

of

1 kO.

Horiz

Out. A front-panel pin

jack

connector

supplies

horizontal

output

signal (negative-going sawtooth that

varies from 0.0 V

dc

to

approximately

-6

V dc)

with

a

source impedance of 5

kO.

REV. A MAY 1978

Scans

bv

Ollbollrce-Options =>

General

Information-7L5

Service

With the INPUT BUFFER switch on, the

third

order

intermodulation

products,

for

any

two

on-screen

signals,

within

any

frequency

span, are at least 80 dB

down.

Display Flatness

Peak

to

peak deviation, over any selected frequency

span: Quantization

error

must be added (see Note

under

Amplitude

Characteristics) if

digital

storage is used.

L1

L2

L3

0.5 dB;

Reference Level

Refers to top

graticule

line in Log mode. Calibrated in

1

dB

and 10

dB

steps

for

the L1 and L2 modules and

1

dB/2

dB

and

10

dB

for

L3

plug-in

module.

Range

L1

L2 L3

Log

-128

dBm

-128

dBm/

-128

dBm

to

2

dB/Div

to

+21

dBm

139

dBV

to

+21

dBm

(50

0),

+21

dBm/

-139

dBm

to

+10

dBV

+10dBm(600

0),

-141

dBV

to

+8

dBV (Hi Z)

Log

-70

dBm

-70

dBm/

-70

dBm

to

10

dB/Div

to

+21

dBm

-81

dBV

to

+21

dBm

(50

0),

+21

dBm/

-81

dBm

to

+10

dBV

+10dBm

(6000),

-83

dBV

to

+8

dBV (Hi Z)

Incremental

Accuracy

When calibrated at

-40

dBV in Log mode:

L

1,

L2

and L3: Within0.2

dB/dB

with cumulative

errorof

0.25

dB/10

dB.

Lin Mode Range:

20

mV/Div

to

200

mV/Divwithin

5%in

1-2-5 sequence.

NOTE

A

>sign

is

displayed

adjacent

to the reference level

readout

when the reference level

is

not

calibrated

due

to an

incompatible

selection

of

controls.

Display

Dynamic

Range/Accuracy

Log 10

dB/Div

Mode:

Dynamic

window

is

80

dB.

Accuracy

is

within

0.05

dB/dB

to

2

dB

maximum.

Log 2

dB/Div

Mode: Dynamic

window

is 16 dB.

Ac-

curacy

is

within

0.1

dB/dB

to

1

dB

maximum.

1-4

Sweep

Characteristics

Frequency Span. Provides calibrated

frequency

spans

from

50

Hz/div

to

maximum

500 kHz/div,

within

4%,

in

1-2-

5 sequence.

Horizontal linearity is

within

4%

over

the

entire 10 div

display.

A O-Hz/Div position is provided

for

time

domain

operation.

Sweep Rate.

Time

per div is selectable from 10

s/div

to

0.1

ms/div

in a 1-2-5sequence. An

AUTO

position permits

automatic selection of

optimum

time/div

for

the selected

resolution and span/div.

Sweep rate

accuracy

is

within

5%

of

the rate selected.

Triggering.

Provides

two

triggering

sources,

INT

(inter-

nal) and LINE, in

addition

to

a FREE-RUN position.

When

INT

is selected, ac

coupled

signal

components

from the mainframe

Trigger

Source (left

or

right vertical

amplifiers) are used.

When LINE is selected, ac

coupled

sample

of

main-

frame line voltage is used.

Three

triggering

modes are; NORM (normal), SGL

SWP/READY (single sweep), and

MNL

SWEEP (manual

sweep).

Trigger

level is

~1.0

div

of

internal signal

for

both

NORM

and

SGL

SWP modes over the approximate

frequency

range of

30

Hz

to

500 kHz.

Output

Connectors

Video Out. Front-panel pin jack

connector

suppliesthe

video (vertical)

output

signal at an

amplitude

of

50

mV/div

±5%

(about the

crt

vertical center) with

source

impedance

of

1 kO.

Horiz

Out. A front-panel pin

jack

connector

supplies

horizontal

output

signal (negative-going sawtooth that

varies from 0.0 V

dc

to

approximately

-6

V dc)

with

a

source impedance of 5

kO.

REV. A MAY 1978

Scans

bv

Ollbollrce-Options =>

Calibrator. Front panel

BNC

connector

supplies a

calibrated 500 kHz squarewave

output

signal (derived

from

the

analyzer's

time

base).

Output

amplitude

is

within

±0.15

dB

of

-40

dBV

into

the impedance of the

plug-in

module.

Environmental

Characteristics

The

7L5 Spectrum Analyzer will meet the

foregoing

electrical characteristics

within

the environmental

limits

of

a 7000-Series oscilloscope.

Complete

details on

en-

vi

ronmental test procedures, includingfai

lure

criteriaetc.,

can be obtained from a local

Tektronix

Field

Office

or

representative.

Physical

Characteristics

Net

weight

(instrument

only): 8 pounds, 12 ounces.

ACCESSORIES AND

OPTIONS

Refer

to

the Replaceable Mechanical Parts List

for

a

complete

listing

of

thestandard and

optional

accessories.

Options

7L5 Option

21-(Log

Display)

7L5

Option

25-(Tracking

Generator)

7L5

Option

28-(Readout)

7L5

Option

30-(Option

21/25)

7L5

Option

31-(Option

21/28)

7L5

Option

32-(Option

25/28)

7L5

Option

33-(Options

21

/25/28)

REV. A MAY 1978

Generallnformatlon-7LS

Service

INSTALLATION

Initial

Inspection

This

instrument

was inspected both mechanically and

electrically

before shipment. It should be free

of

mars

or

scratches and electrically meet

or

exceed the specifica-

tion. Inspect the

instrument

for

physical damage and

check the electrical

performance

by

the Operational

Check

procedure

provided

within

the Operators

Instruc-

tion Manual. This

procedure

will verify thatthe

instrument

is operating

correctly

and

it

will satisfy most receiving

or

incoming

inspection requirements. If the instrument

specification

is to

be

verified, refer

to

the Performance

Check

procedure

in

this

manual.

If there is physical damage

or

performance

deficiency,

contact

your

local

Tektronix

Field

Office

or

represen-

tative.

Installation

Install in a 7000-Series mainframeand aftera

10minute

or

more

warm-up,

check

performance.

To

calibrate

or

service the 7L5,

connect

it

to

the

7000-Series mainframe

interface

through

flexible

plug-in

extenders (see Equip-

ment Required;

Calibration

section).

1-5

Scans

bv

Olluollrce-Options =>

Calibrator. Front panel

BNC

connector

supplies a

calibrated 500 kHz squarewave

output

signal (derived

from

the

analyzer's

time

base).

Output

amplitude

is

within

±0.15

dB

of

-40

dBV

into

the impedance of the

plug-in

module.

Environmental

Characteristics

The

7L5 Spectrum Analyzer will meet the

foregoing

electrical characteristics

within

the environmental

limits

of

a 7000-Series oscilloscope.

Complete

details on

en-

vi

ronmental test procedures, includingfai

lure

criteriaetc.,

can be obtained from a local

Tektronix

Field

Office

or

representative.

Physical

Characteristics

Net

weight

(instrument

only): 8 pounds, 12 ounces.

ACCESSORIES AND

OPTIONS

Refer

to

the Replaceable Mechanical Parts List

for

a

complete

listing

of

thestandard and

optional

accessories.

Options

7L5 Option

21-(Log

Display)

7L5

Option

25-(Tracking

Generator)

7L5

Option

28-(Readout)

7L5

Option

30-(Option

21/25)

7L5

Option

31-(Option

21/28)

7L5

Option

32-(Option

25/28)

7L5

Option

33-(Options

21

/25/28)

REV. A MAY 1978

Generallnformatlon-7LS

Service

INSTALLATION

Initial

Inspection

This

instrument

was inspected both mechanically and

electrically

before shipment. It should be free

of

mars

or

scratches and electrically meet

or

exceed the specifica-

tion. Inspect the

instrument

for

physical damage and

check the electrical

performance

by

the Operational

Check

procedure

provided

within

the Operators

Instruc-

tion Manual. This

procedure

will verify thatthe

instrument

is operating

correctly

and

it

will satisfy most receiving

or

incoming

inspection requirements. If the instrument

specification

is to

be

verified, refer

to

the Performance

Check

procedure

in

this

manual.

If there is physical damage

or

performance

deficiency,

contact

your

local

Tektronix

Field

Office

or

represen-

tative.

Installation

Install in a 7000-Series mainframeand aftera

10minute

or

more

warm-up,

check

performance.

To

calibrate

or

service the 7L5,

connect

it

to

the

7000-Series mainframe

interface

through

flexible

plug-in

extenders (see Equip-

ment Required;

Calibration

section).

1-5

Scans

bv

Olluollrce-Options =>

Section

2-7L5

Service

CIRCUIT

DESCRIPTION

Introduction

The 7L5 is a swept front-end spectrum analyzer with

selectable front-end

plug-in

modules

that

permitthe user

to

obtain

a calibrated display

for

a

number

of

different

impedance (i.e.,

50

ohm, 600 ohm, etc.). The plug-in

module contains: selectable attenuation, the first mixer,

input

low-pass filter, and an

input

buffer selector that

trades noise figure

for

1M

performance. Signalattenuation

in the plug-in and gain

of

the

IF

processing chain are

controlled

by a reference level logic

circuit

in the 7L5

which provides calibrated settings

in

1

dB

or

10

dB

steps

over a range

of

149 dB.

Functional

Block

Diagram

The

input

signal

to

the 7L5 is mixed with the frequency

of

the main

oscillator

and fed to the IF at 10.7 MHz and

amplified

by

the

10.7 MHzIF amplifier. Sincethe 7L5

input

frequency range is 0 to 5 MHz, the main

oscillator

istuned

and swept from 10.7

to

15.7 MHz. The frequency

of

the

main oscillator is controlled

by

two

secondary (A and

B)

oscillators that use a synthesizer technique

to

tune and

phase

lock

their

frequencies. The sweep frequency

con-

trol

circuit

drives the oscillators

according

to

the settings

of

front

panel

DOT

FREQUENCY and FREQUENCY

SPAN/DIV controls.

The signal

at

10.7 MHz is processed

through

a band-

pass

filter

and amplifier, then mixed with

the

output

from

a

10.450

oscillator

to

down-convert

the 10.7 MHz

to

an IF

of

250 kHz. Gain

of

the 250 kHz amplifieris

controlled

by

the

reference level

logic

circuit

which establishes the

amount

of

attenuation in the

plug-in

module and gain

for

the

250 kHz

IF

and Log amplifiers. The reference level is

selectable in 1

dB

and 10

dB

steps.

The 250 kHz IFsignal is processed

through

thevariable

resolution filter

circuits

for

bandwidth selections

of

10 Hz

to 30 kHz. Thesignal is again amplified, detected, and the

video is sent

through

amplifier

circuits

that provide the

10 dB/div, 2

dB/div,

and linear gain characteristics.

@

The video signal is then fed to the display processing

circuits

where the signal is eitherstored and displayed,

or

if

the storage mode is

not

selected, the signal is passed

directly

through

the vertical

output

amplifier

to

the

mainframe circuit. If either

or

both the DISPLAY A

or

DISPLAY B latches are enabled, the signal is converted

to

digital data, stored in A

or

Bmemory,then converted back

to analog data and processed

through

the

output

amplifiers

to

the circuit. The vertical information is

digitized and stored at 512 horizontal address locations

across the screen. Therefore, the horizontal sweep

infor-

mation is converted

to

digital data for storage, then

converted back

to

an analog signal

for

display. The

horizontal sweep ramp is processed the same

as

the

vertical signal. The vertical (video) information can be

averaged

or

peak detected.

IF Processing Chain

<Vb

This

block

diagram shows more detail

of

the

circuitry

involved with processing the IF signal

from

the 1st mixer.

Signal loss

through

the 1st

mixer

is

about

9 dB. The IF

output

of

10.7 MHz passes

through

an

input

and 30 kHz

filter

to

improve flatness, then a 30 kHz crystal filter

shapesthe response

to

the bandpasscharacteristics

of

the

instrument. A

-40

dBm

signal is required

at

this pOint

for

full screen deflection.

Signal level is increased

20

dB

by

the 10.7 MHz IF

amplifier;

it

is thenfed

through

the

300 kHz bandpassfilter

to

the

2nd mixer. The 2nd LO frequency

of

10.450 MHz

mixing with 10.7 MHz produces

an

IF

of

250 kHz which is

fed

through

a 500 kHz lowpass

filter

to the 250 kHz

amplifier. The loss

through

the350 kHzand 500 kHz filters

plus the 2nd

mixer

is

about

10 dB; thus a

-30

dBm

signal

level is required at the

input

of

the 250 kHz

amplifier

to

obtain full screen deflection.

\

2-1

Section

2-7L5

Service

CIRCUIT

DESCRIPTION

Introduction

The 7L5 is a swept front-end spectrum analyzer with

selectable front-end

plug-in

modules

that

permitthe user

to

obtain

a calibrated display

for

a

number

of

different

impedance (i.e.,

50

ohm, 600 ohm, etc.). The plug-in

module contains: selectable attenuation, the first mixer,

input

low-pass filter, and an

input

buffer selector that

trades noise figure

for

1M

performance. Signalattenuation

in the plug-in and gain

of

the

IF

processing chain are

controlled

by a reference level logic

circuit

in the 7L5

which provides calibrated settings

in

1

dB

or

10

dB

steps

over a range

of

149 dB.

Functional

Block

Diagram

The

input

signal

to

the 7L5 is mixed with the frequency

of

the main

oscillator

and fed to the IF at 10.7 MHz and

amplified

by

the

10.7 MHzIF amplifier. Sincethe 7L5

input

frequency range is 0 to 5 MHz, the main

oscillator

istuned

and swept from 10.7

to

15.7 MHz. The frequency

of

the

main oscillator is controlled

by

two

secondary (A and

B)

oscillators that use a synthesizer technique

to

tune and

phase

lock

their

frequencies. The sweep frequency

con-

trol

circuit

drives the oscillators

according

to

the settings

of

front

panel

DOT

FREQUENCY and FREQUENCY

SPAN/DIV controls.

The signal

at

10.7 MHz is processed

through

a band-

pass

filter

and amplifier, then mixed with

the

output

from

a

10.450

oscillator

to

down-convert

the 10.7 MHz

to

an IF

of

250 kHz. Gain

of

the 250 kHz amplifieris

controlled

by

the

reference level

logic

circuit

which establishes the

amount

of

attenuation in the

plug-in

module and gain

for

the

250 kHz

IF

and Log amplifiers. The reference level is

selectable in 1

dB

and 10

dB

steps.

The 250 kHz IFsignal is processed

through

thevariable

resolution filter

circuits

for

bandwidth selections

of

10 Hz

to 30 kHz. Thesignal is again amplified, detected, and the

video is sent

through

amplifier

circuits

that provide the

10 dB/div, 2

dB/div,

and linear gain characteristics.

@

The video signal is then fed to the display processing

circuits

where the signal is eitherstored and displayed,

or

if

the storage mode is

not

selected, the signal is passed

directly

through

the vertical

output

amplifier

to

the

mainframe circuit. If either

or

both the DISPLAY A

or

DISPLAY B latches are enabled, the signal is converted

to

digital data, stored in A

or

Bmemory,then converted back

to analog data and processed

through

the

output

amplifiers

to

the circuit. The vertical information is

digitized and stored at 512 horizontal address locations

across the screen. Therefore, the horizontal sweep

infor-

mation is converted

to

digital data for storage, then

converted back

to

an analog signal

for

display. The

horizontal sweep ramp is processed the same

as

the

vertical signal. The vertical (video) information can be

averaged

or

peak detected.

IF Processing Chain

<Vb

This

block

diagram shows more detail

of

the

circuitry

involved with processing the IF signal

from

the 1st mixer.

Signal loss

through

the 1st

mixer

is

about

9 dB. The IF

output

of

10.7 MHz passes

through

an

input

and 30 kHz

filter

to

improve flatness, then a 30 kHz crystal filter

shapesthe response

to

the bandpasscharacteristics

of

the

instrument. A

-40

dBm

signal is required

at

this pOint

for

full screen deflection.

Signal level is increased

20

dB

by

the 10.7 MHz IF

amplifier;

it

is thenfed

through

the

300 kHz bandpassfilter

to

the

2nd mixer. The 2nd LO frequency

of

10.450 MHz

mixing with 10.7 MHz produces

an

IF

of

250 kHz which is

fed

through

a 500 kHz lowpass

filter

to the 250 kHz

amplifier. The loss

through

the350 kHzand 500 kHz filters

plus the 2nd

mixer

is

about

10 dB; thus a

-30

dBm

signal

level is required at the

input

of

the 250 kHz

amplifier

to

obtain full screen deflection.

\

2-1

Circuit

Descrlptlon-7L5

Service

The 2nd LO frequency

is

controlled by a phase lock

loop

which uses 50 kHz and 100 kHz submultiples

of

a

master

10

MHz crystal controlled oscillator to drive

500

kHz and 100 kHz reference frequencies. The gain

of

the 250 kHz

IF

amplifier is controlled by the decoded

output

from the reference level counter. The reference

level counter in turn, is controlled by the

front

panel

REFERENCE LEVEL control. Gain

of

the amplifier

is

adjustable in

1,

2,

4,

8,

and

two

16

dB

steps. The

attenuators, in the plug-in module are 4 dB, 8 dB, and

32

dB. Combinations

of

attenuators and

IF

gain are

selected by the reference level

counter

and provide gain

changes

of

1 dB

or

10

dB

steps, dependingon the position

of

the REFERENCE LEVEL control. The crossover

point

(no attenuation and unity gain through the amplifier)

is

-30

dBm.

The REFERENCE LEVEL

control

is

a printed

circuit

switch

that

outputsatwo bitbinary codethat repeats every

four

times. The code indicates the direction the control is

rotated and an IC determines whether the

count

is

up

or

down. The

output

code

of

the control, clocks a

counter

which provides the reference level required

to

drive the

readout. Analog currents are provided bya ROM which is

reading the

output

of

the counter. When the REFERENCE

LEVEL control is pulled out,

for

10

dB

steps, the counter

countsintens instead ofdigits.When LIN modeis selected

or

the

dBm/dBV

switch on the plug-in moduleis changed,

the readout changes the Reference Level

Counter

so the

crt

reference level readout is inVolts/Div

or

dBV.Thevalue

of

the constant

to

the

counter

depends on the

input

impedance

of

the plug-in module. This establishes a

calibration reference level commensurate with the respec-

tive

input

impedance

of

the

"L"

plug-in module.

The inputs

to

the IF Gain and

RF

Attenuation Decoding

block

are the

output

from the Reference Level Counter

and the Log

10

or

Log 2 switch latches. The

output

supplies

four

gain change lines

to

the

IF

amplifierand the

attenuatorcodes

for

the plug-in module. An invalidcodeis

fed back

to

stop the

counter

when the reference level

reaches a lower limit.

The

output

of the 250 kHz IF

is

fed

to

the Variable

Resolution Filter. Bandwidths

of

10

Hz to 3 kHz are

selected by one filter block and

10

kHz and

30

kHz

bandwidths by a second block. Signal routing through the

filters,

is

controlled

by

the resolution code which in

turn

may

be

controlled by the RESOLUTION control. For

automatic

or

coupled operation, a ROM selects the

appropriate resolution bandwidth so the bandwidth and

frequency span are compatible. If the operator selects a

2-2

resolution that is

not

appropriate

for

the FREQUENCY

SPAN selected, the ROM activates a CAL

light

to in-

validate the reference level reading and the readout

presentsa<symbol in

front

of

the reference level readout.

The

output

signal from the Resolution Filters

is

fed

through a Post

VR

Amplifier

then a

Log/Lin

amplifier. The

response amplitude level is now either Log

10,

Log

2,

or

Linear depending on the setting

of

the

log/lin

latches.

These latches are activated

by

front

panel momentary

contact pushbuttons. Log

10

control

is

also fed

to

the IF

Gain and

RF

Attenuation Decoder.

The IF is then detected and the

output

video signal fed

to another

Log/Lin

amplifier

for

gain adjustment between

the

Log/Lin

displays. Part

of

the

output

is fed to U2005 to

provide push-pull

trigger

signals

(+

and

-)

to

the main-

frame and video signals

to

the VIDEO

OUT

jack on the

front

panel. The main video signal is fed

to

the display

processing circuits where it

is

processed either through

amplifiers

to

the mainframe

for

display, or,

if

the 7L5 is

operating in the store mode, the signal is stored in

memory, and then displayed

as

the memory is refreshed

or

updated.

Sweep Control and Frequency Reference

<!>

a

The Sweep Control

circuit

uses an IC that features;

sweep gating,

bright

baseline,

holdoff

timing, automatic

free run, lockout, single sweep and single sweep ready

light

control. The gate signal drives the sweep generator

which in

turn

sends a sweep through the Manual Sweep

switch to the Display Processing and

circuitry

related to

the sweep

for

the A and B oscillators. Inputs to the sweep

control IC include triggering source and mode signals.

Trigger modes are set bylatchesthatareactuated byfront

panel momentary contact pushbutton switches.

When SGL SWP is selected, the sweep is locked out

until the SGL SWP button is pushed again. The

circuit

is

now

armed and the sweep will run if the

trigger

source is

FREE RUN

or

when a triggersignal arrives. A

built

in delay

of

approximately

10

seconds allows the sweep

to

run

if

no

trigger arrives (not in 0 Hz span). This keeps the memory

capacitors

for

phase lock loop,

of

the A and B oscillators,

refreshed.

When MNL SWP

is

selected the Sweep Generator

is

used

as

a 100 second timer to refresh the memory

capacitors. The Sweep Control allows the Sweep

Generator

to

free run; however, the Manual Sweep switch

now selects the voltage

output

of

the LEVEL/SLOPE

control

for

the Sweep Horizontal Signal.

@

Circuit

Descrlptlon-7L5

Service

The 2nd LO frequency

is

controlled by a phase lock

loop

which uses 50 kHz and 100 kHz submultiples

of

a

master

10

MHz crystal controlled oscillator to drive

500

kHz and 100 kHz reference frequencies. The gain

of

the 250 kHz

IF

amplifier is controlled by the decoded

output

from the reference level counter. The reference

level counter in turn, is controlled by the

front

panel

REFERENCE LEVEL control. Gain

of

the amplifier

is

adjustable in

1,

2,

4,

8,

and

two

16

dB

steps. The

attenuators, in the plug-in module are 4 dB, 8 dB, and

32

dB. Combinations

of

attenuators and

IF

gain are

selected by the reference level

counter

and provide gain

changes

of

1 dB

or

10

dB

steps, dependingon the position

of

the REFERENCE LEVEL control. The crossover

point

(no attenuation and unity gain through the amplifier)

is

-30

dBm.

The REFERENCE LEVEL

control

is

a printed

circuit

switch

that

outputsatwo bitbinary codethat repeats every

four

times. The code indicates the direction the control is

rotated and an IC determines whether the

count

is

up

or

down. The

output

code

of

the control, clocks a

counter

which provides the reference level required

to

drive the

readout. Analog currents are provided bya ROM which is

reading the

output

of

the counter. When the REFERENCE

LEVEL control is pulled out,

for

10

dB

steps, the counter

countsintens instead ofdigits.When LIN modeis selected

or

the

dBm/dBV

switch on the plug-in moduleis changed,

the readout changes the Reference Level

Counter

so the

crt

reference level readout is inVolts/Div

or

dBV.Thevalue

of

the constant

to

the

counter

depends on the

input

impedance

of

the plug-in module. This establishes a

calibration reference level commensurate with the respec-

tive

input

impedance

of

the

"L"

plug-in module.

The inputs

to

the IF Gain and

RF

Attenuation Decoding

block

are the

output

from the Reference Level Counter

and the Log

10

or

Log 2 switch latches. The

output

supplies

four

gain change lines

to

the

IF

amplifierand the

attenuatorcodes

for

the plug-in module. An invalidcodeis

fed back

to

stop the

counter

when the reference level

reaches a lower limit.

The

output

of the 250 kHz IF

is

fed

to

the Variable

Resolution Filter. Bandwidths

of

10

Hz to 3 kHz are

selected by one filter block and

10

kHz and

30

kHz

bandwidths by a second block. Signal routing through the

filters,

is

controlled

by

the resolution code which in

turn

may

be

controlled by the RESOLUTION control. For

automatic

or

coupled operation, a ROM selects the

appropriate resolution bandwidth so the bandwidth and

frequency span are compatible. If the operator selects a

2-2

resolution that is

not

appropriate

for

the FREQUENCY

SPAN selected, the ROM activates a CAL

light

to in-

validate the reference level reading and the readout

presentsa<symbol in

front

of

the reference level readout.

The

output

signal from the Resolution Filters

is

fed

through a Post

VR

Amplifier

then a

Log/Lin

amplifier. The

response amplitude level is now either Log

10,

Log

2,

or

Linear depending on the setting

of

the

log/lin

latches.

These latches are activated

by

front

panel momentary

contact pushbuttons. Log

10

control

is

also fed

to

the IF

Gain and

RF

Attenuation Decoder.

The IF is then detected and the

output

video signal fed

to another

Log/Lin

amplifier

for

gain adjustment between

the

Log/Lin

displays. Part

of

the

output

is fed to U2005 to

provide push-pull

trigger

signals

(+

and

-)

to

the main-

frame and video signals

to

the VIDEO

OUT

jack on the

front

panel. The main video signal is fed

to

the display

processing circuits where it

is

processed either through

amplifiers

to

the mainframe

for

display, or,

if

the 7L5 is

operating in the store mode, the signal is stored in

memory, and then displayed

as

the memory is refreshed

or

updated.

Sweep Control and Frequency Reference

<!>

a

The Sweep Control

circuit

uses an IC that features;

sweep gating,

bright

baseline,

holdoff

timing, automatic

free run, lockout, single sweep and single sweep ready

light

control. The gate signal drives the sweep generator

which in

turn

sends a sweep through the Manual Sweep

switch to the Display Processing and

circuitry

related to

the sweep

for

the A and B oscillators. Inputs to the sweep

control IC include triggering source and mode signals.

Trigger modes are set bylatchesthatareactuated byfront

panel momentary contact pushbutton switches.

When SGL SWP is selected, the sweep is locked out

until the SGL SWP button is pushed again. The

circuit

is

now

armed and the sweep will run if the

trigger

source is

FREE RUN

or

when a triggersignal arrives. A

built

in delay

of

approximately

10

seconds allows the sweep

to

run

if

no

trigger arrives (not in 0 Hz span). This keeps the memory

capacitors

for

phase lock loop,

of

the A and B oscillators,

refreshed.

When MNL SWP

is

selected the Sweep Generator

is

used

as

a 100 second timer to refresh the memory

capacitors. The Sweep Control allows the Sweep

Generator

to

free run; however, the Manual Sweep switch

now selects the voltage

output

of

the LEVEL/SLOPE

control

for

the Sweep Horizontal Signal.

@

When the sweep mode is NORM, sweep operation is

conventional. The LEVEL/SLOPE

control

selects the

triggering

level and slope unless the mode is

MNL

SWP. It

then becomes a manual sweep

control.

The sweep generator

contains

an end

of

sweep

com-

parator

that

outputs

a pulse

which

is fed back to thesweep

control

IC to terminate the

output

gate and

inhibit

the

sweep. The end

of

sweep pulse is OR'd with an

output

line

from the phase lock

logic

circuit,

which

goes

high

at the

end

of

the

gate pulse period and

holds

this state until the

sweep

control

circuit

has stabilized about (50 ms) then

it

pulls the Ready line low.

The

state

of

the

land

Sense lines,

from the

dot

frequency

control

and phase

lock

loop

circuit

must also be

correct

beforethe phase

lock

logic

circuit

will

permit

the

sweep

control

and sweep

generator

to start

another sweep. Sweep lockout, by the

dot

frequency

and

phase

lock

loop

circuits, is ignored when the Frequency

Span/Div

is ZERO.

The sweep rate is

controlled

by the

TIME/DIV

selector

unless

AUTO

position

is selected. When

AUTO

is

selected, sweep rate is

controlled

bya ROM

which

looksat

the FREQUENCY

SPAN/DIV

and RESOLUTION selec-

tions

to

determine the sweep rate. The RESOLUTION and

FREQUENCY

SPAN/DIV

selectorsare both

printed

circuit

switches that feed

their

output

into ROMs. The ROMsthen

control

the

frequency

span and resolution

bandwidth

of

the

instrument

and provide readout datatothe circuit. The

RESOLUTION selector has a COUPLED

position

where a

ROM determines the

optimum

resolution

for

the selected

FREQUENCY SPAN/DIV. In the manual positions

of

the

RESOLUTION and

TIME/DIV

selectors, the uncal

com-

parator

monitors

the sweep rate versus resolution

bandwidth

and Frequency

Span/Div

setting. It lights an

UNCAL

indicator

when the display is

not

calibrated.

At

the

same

time

a >

symbol

precedes the Reference Level

readout

to

indicate that the readout is

not

calibrated.

Frequency Reference

The center

frequency

of

the span is programmed

into

...;.-N

counters

which

are part

of

a

frequency

and phase

lock

synthesizer loop.

Two

of

these

...;.-N

control

loops

set and

lock the

frequency

of

two

secondary (A &

8)

oscillators

which

are part

of

a

third

loop

that

controls

the 1st

LO

frequency. The 1st LO

center

frequency, therefore, is

dependent on the programmed data in the

...;.-N

counters.

The

frequency

span

of

the 1st LO depends on the ramp

amplitude

out

of

the sweep

attenuator

circuits.

During

retrace time, the secondary oscillators are locked to the

center frequency.

During

lock

the sweep reduces to a

@

Circuit

Description-7L5

Service

voltage

of

zero.

The

time shared

dot

position

is therefore,

derived

from

an equivalent sweep voltage

of

zero. Fre-

quency

of

the

dot

position

is displayed by the

crt

readout.

Accurate

frequency

measurements can be performed by

tuning

any desired segment

of

the display

under

the

frequency

dot

and read

out

on

the crt. In most cases

readout accuracy is

~1%

of

the

display

span

or

within

±50

Hz.

In

all

frequency

span positions

except

MAX span, the

frequency

dot

is at the

center

or

start

of

the display. In

MAX span the center

frequency

of

the span is 2.5 MHz.

The

frequency

dot

moves across the

display

as

the center

frequency

is tuned. The

frequency

readout accuracy

of

the

dot

remains constant.

A simplified

block

diagram

of

the Frequency Reference

circuitry

is shown in Fig. 2-1. The

frequency

to

be

measured (fm), is fed

to

the 1st

mixer

in the

plug-in

module, where it is mixed

with

the

output

from

the 1st LO.

The

output

IF

of

10.700 MHz is fed to the 2nd

mixer

where

it

is mixed with 10.45 MHz from the 2nd LO and converted

down

to

a250 kHz I

F.

The 2nd LO

frequency

is referenced

to 500 kHz, a

submultiple

of

a 10 MHz Master Oscillator.

Frequency Control Circuits

As previously described,

two

divide

by

"N"

(Nt and N2)

control

loops,

with

their

oscillators,

determine

the fre-

quency

of

the1st LO. A

11.1

MHz

to

16 MHz,

"A"

oscillator

mixes

with

the frequency

of

the 1st LO (10.7 to 15.7 MHz).

The difference is compared with the40th

sub-harmonic

of

a 12

to

16 MHz

"8"

oscillator

in a I::.f/I::.¢ detector.

Any

difference produces an

error

voltage

that

is fed back

though

a

summing

amplifier

to pull the 1st

LO

into

a

locked mode

with

both A and 8 oscillators.

The

frequency

of

both secondary (A and

8)

oscillators

is

controlled

by

...;.-N

loops. The value N is determined by

the

DOT

frequency

control. This

control

tunes the A

oscillator

in 100 kHz increments and the 8

oscillator

in

10 kHz steps. (100 kHz and 10 kHz increments originate

from the 10 MHz masteroscillator.) The

frequency

of

the 8

oscillator

is divided

down

by 40 so the

frequency

into the

comparator

steps in 250 Hz increments. If the DOT

frequency

Is

0 Hz, thefrequencies

of

the Aand 8

oscillator

are

11.1

MHz and 16.0 MHz. The

input

to

the phase lock

comparator

(I::.f/I::.¢ detector) from the

...;.-40

source is

400 kHz (16 MHz

...;.-

40). The difference

frequency

out

of

the A

oscillator

and the 1st LO

mixer

mustalso be 400 kHz

for

the system

to

lock. Since the A and 8 oscillators are

2-3

Scans

by

Olllsou,ce-Optiolls =>

When the sweep mode is NORM, sweep operation is

conventional. The LEVEL/SLOPE

control

selects the

triggering

level and slope unless the mode is

MNL

SWP. It

then becomes a manual sweep

control.

The sweep generator

contains

an end

of

sweep

com-

parator

that

outputs

a pulse

which

is fed back to thesweep

control

IC to terminate the

output

gate and

inhibit

the

sweep. The end

of

sweep pulse is OR'd with an

output

line

from the phase lock

logic

circuit,

which

goes

high

at the

end

of

the

gate pulse period and

holds

this state until the

sweep

control

circuit

has stabilized about (50 ms) then

it

pulls the Ready line low.

The

state

of

the

land

Sense lines,

from the

dot

frequency

control

and phase

lock

loop

circuit

must also be

correct

beforethe phase

lock

logic

circuit

will

permit

the

sweep

control

and sweep

generator

to start

another sweep. Sweep lockout, by the

dot

frequency

and

phase

lock

loop

circuits, is ignored when the Frequency

Span/Div

is ZERO.

The sweep rate is

controlled

by the

TIME/DIV

selector

unless

AUTO

position

is selected. When

AUTO

is

selected, sweep rate is

controlled

bya ROM

which

looksat

the FREQUENCY

SPAN/DIV

and RESOLUTION selec-

tions

to

determine the sweep rate. The RESOLUTION and

FREQUENCY

SPAN/DIV

selectorsare both

printed

circuit

switches that feed

their

output

into ROMs. The ROMsthen

control

the

frequency

span and resolution

bandwidth

of

the

instrument

and provide readout datatothe circuit. The

RESOLUTION selector has a COUPLED

position

where a

ROM determines the

optimum

resolution

for

the selected

FREQUENCY SPAN/DIV. In the manual positions

of

the

RESOLUTION and

TIME/DIV

selectors, the uncal

com-

parator

monitors

the sweep rate versus resolution

bandwidth

and Frequency

Span/Div

setting. It lights an

UNCAL

indicator

when the display is

not

calibrated.

At

the

same

time

a >

symbol

precedes the Reference Level

readout

to

indicate that the readout is

not

calibrated.

Frequency Reference

The center

frequency

of

the span is programmed

into

...;.-N

counters

which

are part

of

a

frequency

and phase

lock

synthesizer loop.

Two

of

these

...;.-N

control

loops

set and

lock the

frequency

of

two

secondary (A &

8)

oscillators

which

are part

of

a

third

loop

that

controls

the 1st

LO

frequency. The 1st LO

center

frequency, therefore, is

dependent on the programmed data in the

...;.-N

counters.

The

frequency

span

of

the 1st LO depends on the ramp

amplitude

out

of

the sweep

attenuator

circuits.

During

retrace time, the secondary oscillators are locked to the

center frequency.

During

lock

the sweep reduces to a

@

Circuit

Description-7L5

Service

voltage

of

zero.

The

time shared

dot

position

is therefore,

derived

from

an equivalent sweep voltage

of

zero. Fre-

quency

of

the

dot

position

is displayed by the

crt

readout.

Accurate

frequency

measurements can be performed by

tuning

any desired segment

of

the display

under

the

frequency

dot

and read

out

on

the crt. In most cases

readout accuracy is

~1%

of

the

display

span

or

within

±50

Hz.

In

all

frequency

span positions

except

MAX span, the

frequency

dot

is at the

center

or

start

of

the display. In

MAX span the center

frequency

of

the span is 2.5 MHz.

The

frequency

dot

moves across the

display

as

the center

frequency

is tuned. The

frequency

readout accuracy

of

the

dot

remains constant.

A simplified

block

diagram

of

the Frequency Reference

circuitry

is shown in Fig. 2-1. The

frequency

to

be

measured (fm), is fed

to

the 1st

mixer

in the

plug-in

module, where it is mixed

with

the

output

from

the 1st LO.

The

output

IF

of

10.700 MHz is fed to the 2nd

mixer

where

it

is mixed with 10.45 MHz from the 2nd LO and converted

down

to

a250 kHz I

F.

The 2nd LO

frequency

is referenced

to 500 kHz, a

submultiple

of

a 10 MHz Master Oscillator.

Frequency Control Circuits

As previously described,

two

divide

by

"N"

(Nt and N2)

control

loops,

with

their

oscillators,

determine

the fre-

quency

of

the1st LO. A

11.1

MHz

to

16 MHz,

"A"

oscillator

mixes

with

the frequency

of

the 1st LO (10.7 to 15.7 MHz).

The difference is compared with the40th

sub-harmonic

of

a 12

to

16 MHz

"8"

oscillator

in a I::.f/I::.¢ detector.

Any

difference produces an

error

voltage

that

is fed back

though

a

summing

amplifier

to pull the 1st

LO

into

a

locked mode

with

both A and 8 oscillators.

The

frequency

of

both secondary (A and

8)

oscillators

is

controlled

by

...;.-N

loops. The value N is determined by

the

DOT

frequency

control. This

control

tunes the A

oscillator

in 100 kHz increments and the 8

oscillator

in

10 kHz steps. (100 kHz and 10 kHz increments originate

from the 10 MHz masteroscillator.) The

frequency

of

the 8

oscillator

is divided

down

by 40 so the

frequency

into the

comparator

steps in 250 Hz increments. If the DOT

frequency

Is

0 Hz, thefrequencies

of

the Aand 8

oscillator

are

11.1

MHz and 16.0 MHz. The

input

to

the phase lock

comparator

(I::.f/I::.¢ detector) from the

...;.-40

source is

400 kHz (16 MHz

...;.-

40). The difference

frequency

out

of

the A

oscillator

and the 1st LO

mixer

mustalso be 400 kHz

for

the system

to

lock. Since the A and 8 oscillators are

2-3

Scans

by

Olllsou,ce-Optiolls =>

Circuit

Description-7L5

Service

referenced

to

the same reference (10 MHz master

os-

cillator) the 1st LO is locked to 10.7 MHz

(11.1

MHz-

400 kHz). Frequency changes to

either

A

or

B oscillators

require a change in the value

of

"N"

that is loaded

into

up/down

counters

for

the respective

control

loops.

The

DOT

FREQUENCY will tune

either

the B

oscillator

in 10 kHz steps

or

the A

oscillator

in 100 kHz steps. The

frequency

of

the 1st LO (and the

dot)

can therefore be

tuned in 250 Hz

or

100 kHz steps depending on

which

latch is enabled.

A

more

detailed

block

diagram

of

the Frequency

Reference

circuit

is provided by the Sweep

Control

and

Frequency Reference

Block

Diagram

(1

a)

in the Diagrams

section.

The 10 MHz

of

the crystal

oscillator

or

Master

Oscillator

frequency is divided

down

to

100 kHz and

500 kHz by

two

counters. 100 kHz is fed

to

one

input

of

a

phase

comparator

for

the A

oscillator

loop. It is also

divided

down

to

10 kHz

for

application

to

one

input

of

a

phase

comparator

for

the B

oscillator

loop. The

output

voltages

of

the

comparators

are applied

through

logic

circuitry

to

memorycapacitorsin each

oscillator

loop. The

logic

circuitry

gates the

comparator

reference voltage

to

this

memory

circuit

during

retrace

or

the

Lock

portion

of

the sweep cycle.

This

charge

or

reference voltage on the

memory

capacitor

is summed with the sweep ramp from

the frequency span (Sweep

Control)

circuit.

The

resultant

voltage is applied

through

amplifiers

to

the A

or

B

oscillator

to

control

their

frequencies.

The A

oscillator

output

is mixed

with

the

1st LO

frequency and

the

difference

frequency

applied

to

one

input

of

a phase

comparator

and

loop

filter. The other

input,

to

the phase comparator, is

the

40

sub-frequency

of

the B oscillator.

Any

difference between

the

two

frequen-

cies produces an

error

voltage

which

is applied

to

the

1st

LO

to

correct

and

control

the

1st LO frequency. The

oscillator

frequencies can be expressed

as:

f(l,tLO)

=

f(A

o,c)

-f(~).

40

FREQUENCY REFERENCE BLOCK

FIRST

MIXER

f

in

(fm)

10.700

MHz

IF

1ST

LO

10.7

MHz

TO

15.69975

MHz

I

r------------

J

MIXER

~

PHASE

LOCK

COMPARATOR

0

AOSC

11.1

MHz

TO

16.0

MHz

N1

SECOND

MIXER

2ND

LO

10.45

MHz

10MHz

250

kHz

IF

500

kHz

REF

~

MASTER

OSC

100

kHz

REF

0 0

BOSC

16

MHz

TO

12

MHz

CAL

(100

kHz)

10

kHz

REF

2184-1

Fig.

2-1.

Frequency

reference

block

diagram.

2-4 REV. A MAY 1978

Scans

by

O"tso",ce-Options

=>

Circuit

Description-7L5

Service

referenced

to

the same reference (10 MHz master

os-

cillator) the 1st LO is locked to 10.7 MHz

(11.1

MHz-

400 kHz). Frequency changes to

either

A

or

B oscillators

require a change in the value

of

"N"

that is loaded

into

up/down

counters

for

the respective

control

loops.

The

DOT

FREQUENCY will tune

either

the B

oscillator

in 10 kHz steps

or

the A

oscillator

in 100 kHz steps. The

frequency

of

the 1st LO (and the

dot)

can therefore be

tuned in 250 Hz

or

100 kHz steps depending on

which

latch is enabled.

A

more

detailed

block

diagram

of

the Frequency

Reference

circuit

is provided by the Sweep

Control

and

Frequency Reference

Block

Diagram

(1

a)

in the Diagrams

section.

The 10 MHz

of

the crystal

oscillator

or

Master

Oscillator

frequency is divided

down

to

100 kHz and

500 kHz by

two

counters. 100 kHz is fed

to

one

input

of

a

phase

comparator

for

the A

oscillator

loop. It is also

divided

down

to

10 kHz

for

application

to

one

input

of

a

phase

comparator

for

the B

oscillator

loop. The

output

voltages

of

the

comparators

are applied

through

logic

circuitry

to

memorycapacitorsin each

oscillator

loop. The

logic

circuitry

gates the

comparator

reference voltage

to

this

memory

circuit

during

retrace

or

the

Lock

portion

of

the sweep cycle.

This

charge

or

reference voltage on the

memory

capacitor

is summed with the sweep ramp from

the frequency span (Sweep

Control)

circuit.

The

resultant

voltage is applied

through

amplifiers

to

the A

or

B

oscillator

to

control

their

frequencies.

The A

oscillator

output

is mixed

with

the

1st LO

frequency and

the

difference

frequency

applied

to

one

input

of

a phase

comparator

and

loop

filter. The other

input,

to

the phase comparator, is

the

40

sub-frequency

of

the B oscillator.

Any

difference between

the

two

frequen-

cies produces an

error

voltage

which

is applied

to

the

1st

LO

to

correct

and

control

the

1st LO frequency. The

oscillator

frequencies can be expressed

as:

f(l,tLO)

=

f(A

o,c)

-f(~).

40

FREQUENCY REFERENCE BLOCK

FIRST

MIXER

f

in

(fm)

10.700

MHz

IF

1ST

LO

10.7

MHz

TO

15.69975

MHz

I

r------------

J

MIXER

PHASE

LOCK

COMPARATOR

AOSC

11.1

MHz

TO

16.0

MHz

SECOND

MIXER

2ND

LO

10.45

MHz

250

kHz

IF

500

kHz

REF

10MHz

MASTER

OSC

100

kHz

REF

BOSC

16

MHz

TO

12

MHz

10

kHz

REF

CAL

(100

kHz)

2184-1

Fig.

2-1.

Frequency

reference

block

diagram.

2-4 REV. A MAY

1978

Scans

by

O"tso",ce-Options

=>

Output

frequencies

of

the A

oscillator

and B

oscillator

are fed back

to

A

-7-

Nand

B

-7-

N circuits. The value

"N"

assumes depends on the setting

of

the

dot

frequency

control

circuit. Forexample, a

frequency

of

16 MHz

out

of

the A

oscillator

requires an

"N"

factor

of

160

to

divide

16 MHz

down

to

100 kHz, so the frequency into the phase

comparator

equals the 100 kHz at the

other

input

to

the

comparator. As the

dot

frequency

is changed, the

"N"

factor

into

either

the A

-7-

N

or

B

-7-

N

circuit

changes to

increase

or

decreasethe A

or

B

oscillator

frequency. Since

" the 1st LO is slaved to these oscillators, its

frequency

must

also change.

The Frequency

Span/Div

circuit

determines the

amount

the A

or

B

oscillator

frequency

is swept. The

sweep horizontal voltage is applied

through

an

attenuator

and

binary

switch

to a

summing

point,

either

in the A

memory

or

B

memory

reference voltage line. The FRE-

QUENCY

SPAN/DIV

selector sets the

amount

of

sweep

attenuation and

thus

the

frequency

span. The

output

of

the

SPAN/DIV

selector is also fed toa ROM

which

looksat

the selected span andchooses one

of

three sweep

outputs

from the

binary

controlled

switch. These ramps are used

for

different

span/div

frequencies (50 Hz

to

2 kHz,

for

the

Circuit

Description-7L5

Service

B

oscillator

frequency loop, 5 kHz

to

200 kHz and 500 kHz

or

MAX span

for

the A

oscillator

loop). Since the loop

sensitivity

of

the

two

oscillator

loops

differ

by a factor

of

100, the

attenuator

settings are used

twice

to

coverthefull

range (50 Hz to 500 kHz)

of

the FREQUENCY SPAN/DIV.

When the FREQUENCY

SPAN/DIV

is

not

in the MAX

span position, the MAXswitch closes

to

allow

a

dot

marker

voltage

to

be summed in

with

the A

oscillator

control

loop

so the

dot

can be positioned along the left

portion

of

the

5 MHz display.

A

turn-on

circuit

(on the left side

of

thediagram)forces

a free run and normal selection

of

the

trigger

circuits, a

dot

frequency

of

000, reference level

of

+17

dBm, and Display

A,

Display B store modes when

power

is applied.

Readout

A

block

diagram

of

the Readout

circuits

is shown in Fig.

2-2.

Along

the left side are the

front

panel selectors. The

DOT

FREQUENCY

control

drivesa

TEKTRONIX

IC

which

provides the

column

data

for

the

top

horizontal readout

location on the crt.

Current

for

the Hz and kHz readout is

supplied by a resistor matrix. Row data also comes from a

fixed resistor matrix.

FROM

FIXED

@

DOT

FREQUENCY

REFERENCE

LEVEL

dBm/dBV

OFFSET

FREQUENCY

SPAN

RESOLUTION

TIME/DIV

U830

REF

LEVEL

ROM

U2235

j j

ROROM

U800

RESISTOR

MATRIX

RESISTOR

MATRIX.

COLUMN

DATA

FROM

FIXED

ROW

DATA

RESISTOR

MATRIX

COLUMN

DATA

j j

UNCAL

VAR

LIN

LATCH

ROW

DATA

COLUMN

DATA

A37

~

, TOP

A

HORIZONTAL

:>

B37

~

,

A37

TOP

RIGHT

VERTICAL

),

B37

~----------------------------------~

A38

BOTTOM

A

HORIZONTAL

FROM

FIXED

ROW

DATA

CI.

RESISTOR

MATRIX

-------------------7~

B38

LOG/LIN

COLUMN

DATA

ROW

DATA

2184-2

Fig. 2-2.

Function

block

of

readout

circuits.

2-5

Scans

bp

Outsource-Ootions

=>

Output

frequencies

of

the A

oscillator

and B

oscillator

are fed back

to

A

-7-

Nand

B

-7-

N circuits. The value

"N"

assumes depends on the setting

of

the

dot

frequency

control

circuit. Forexample, a

frequency

of

16 MHz

out

of

the A

oscillator

requires an

"N"

factor

of

160

to

divide

16 MHz

down

to

100 kHz, so the frequency into the phase

comparator

equals the 100 kHz at the

other

input

to

the

comparator. As the

dot

frequency

is changed, the

"N"

factor

into

either

the A

-7-

N

or

B

-7-

N

circuit

changes to

increase

or

decreasethe A

or

B

oscillator

frequency. Since

" the 1st LO is slaved to these oscillators, its

frequency

must

also change.

The Frequency

Span/Div

circuit

determines the

amount

the A

or

B

oscillator

frequency

is swept. The

sweep horizontal voltage is applied

through

an

attenuator

and

binary

switch

to a

summing

point,

either

in the A

memory

or

B

memory

reference voltage line. The FRE-

QUENCY

SPAN/DIV

selector sets the

amount

of

sweep

attenuation and

thus

the

frequency

span. The

output

of

the

SPAN/DIV

selector is also fed toa ROM

which

looksat

the selected span andchooses one

of

three sweep

outputs

from the

binary

controlled

switch. These ramps are used

for

different

span/div

frequencies (50 Hz

to

2 kHz,

for

the

Circuit

Description-7L5

Service

B

oscillator

frequency loop, 5 kHz

to

200 kHz and 500 kHz

or

MAX span

for

the A

oscillator

loop). Since the loop

sensitivity

of

the

two

oscillator

loops

differ

by a factor

of

100, the

attenuator

settings are used

twice

to

coverthefull

range (50 Hz to 500 kHz)

of

the FREQUENCY SPAN/DIV.

When the FREQUENCY

SPAN/DIV

is

not

in the MAX

span position, the MAXswitch closes

to

allow

a

dot

marker

voltage

to

be summed in

with

the A

oscillator

control

loop

so the

dot

can be positioned along the left

portion

of

the

5 MHz display.

A

turn-on

circuit

(on the left side

of

thediagram)forces

a free run and normal selection

of

the

trigger

circuits, a

dot

frequency

of

000, reference level

of

+17

dBm, and Display

A,

Display B store modes when

power

is applied.

Readout

A

block

diagram

of

the Readout

circuits

is shown in Fig.

2-2.

Along

the left side are the

front

panel selectors. The

DOT

FREQUENCY

control

drivesa

TEKTRONIX

IC

which

provides the

column

data

for

the

top

horizontal readout

location on the crt.

Current

for

the Hz and kHz readout is

supplied by a resistor matrix. Row data also comes from a

fixed resistor matrix.

FROM

FIXED

DOT

U830

RESISTOR

MATRIX.

FREQUENCY

FROM

FIXED

RESISTOR

MATRIX

REF

LEVEL

REFERENCE

LEVEL

ROM f

U2235

UNCAL

f ,

VAR

dBm/dBV

LIN

LATCH

OFFSET

I

FREQUENCY

I

ROROM

SPAN I

U800

FROM

FIXED

RESISTOR

MATRIX

I

RESOLUTION

.~

LOG/LIN

,

I

J--

....

RESISTOR

TIME/DIV

MATRIX

Fig. 2-2.

Function

block

of

readout

circuits.

@

A37

COLUMN

DATA

"'

, TOP

A

HORIZONTAL

ROW

DATA

)

B37

COLUMN

DATA

...,

A37

ROW

DATA

COLUMN

DATA

ROW

DATA

COLUMN

DATA

ROW

DATA

/

TOP

RIGHT

VERTICAL

).

B37

"

,

)

"

,

~

,

A38

BOTTOM

A

HORIZONTAL

B38

A38

BOTTOM

RiGHT

VERTICAL

B38

2184-2

2-5

Scans

bp

Outsource-Ootions

=>

Circuit Description-7L5 Service

The REFERENCE LEVEL drives U2235

which

provides

.f

column

data

current

for

the

top

right

vertical readout

-...:

position. The

output

of

the

U2235 is influenced by the

~

o

setting

of

the

dBm/dBV

selector and the offset set by the -

input

impedance

of

the

plug-in

module

and the reference

'-

level selected. The LIN

switch

latch changes the row data...f

so the readout is in nV,

JiV,

and mV instead

of

dBm

ordBV.

__

(The

column

data is also changed so the

correct

numbers

~

are read out.) :?-

The

address is derived

from

the

horizontal

sweep ramp.

This

is a 10 volt negative-going ramp centered around the

Dot

frequency.

The

ramp is offset (up

to

plus

or

minus

10

volts) as the

dot

frequency

is tuned so the sweep ramp

range can run

from

-10

V

to

+10

V

(-10

V

to

0 V at one

end and 0 V

to

+10

V at the other). The sweep is

converted, by the horizontal

AID

converter, to address

data

for

memory.

Memory

consists

of

a 4096 (512 x 8)

bit

RAM and a 1024 (1024 x 1)

bit

overflow

or

offset RAM. The

4096

bit

RAM has 512 horizontal access lines.

Memory

is

, divided

into

an A and B section with 256 lines assigned to

The FREQUENCY

SPAN/DIV

drives ROM U800

which-

each. Address locations are determined by the LSB (least

provides the

column

data

for

the

bottom

A horizontal

significant

bit)

of

the horizontal address word. Since the

position. Row data is from a fixed resistor matrix. If zero

-:

LSB

of

this

word

alternates with

any

count,

the

A and B

span is selected,

it

reads in time/division.

...A

locations in

memory

are adjacent with the odd bit

The RESOLUTION selectordrives a resistor matrixthat

provides both

column

and row data

to

the

bottom

right

vertical part

of

the display.

The

column

data also gets the

10 dB, 2 dB, or; if LIN

mode

is selected, that

portion

of

the

display

is a space.

Display Processing Block Diagram

0c

$ assigned

to

A

memory

and the even bit

to

B memory

~

sections.

The horizontal address is a

10

bit

word. The first 9 bits

(2

9) are derived from the sweep ramp and stored in the first

RAM. Thetenth

bit

(MSB) is stored in the

overflow

or

offset

RAM.

This

tenth bit signifies the offset (to the

right

or

left

of

center

screen)

of

a given address and since the offset

can

be

up

to

±10

V,

a 20

volt

ramp

capability

is provided.

The video signal from the IF processing chain is fed

,oo/eI,>

~

lOVMe

~{

through

switch U735B

to

an

AID

converter.

The

digital

-:

s;;.

Z

~

-'

1

~

21./i(

~'I

20(:>::0 -

data from theconverter is then placed in memory. It is read

'/

from

memory

and displayed at the

command

of

Display A

At

the slowersweep speeds, there are

numerous

words

and

Display B selectors. Before the vertical data is placed

of

vertical data

for

each

horizontal

address location.These

in memory,

it

may be

either

averaged

or

peak detected.

numerous

words

of

vertical data are averaged, by the

Vertical data is placed at an address in

memory

derived average calculator, so with a 10 second sweep rate, up

to

from the sweep horizontal waveform.

How

the address is 20,000 words are averaged at a horizontal address.

At

the

derived will be described later. C2 ms sweep rate,

only

four

words

would

be averaged.

~~s

/0'":

"'0"',

lv~

-:

512

/U("

i)/Ih'\..

Referring

to

the

lower

left side

of

the diagram, the 1st

~

1=

'12.

~

'I S''f'l.,/",,-1,;"

LO tune voltage ramp is fed

to

an

absolute value

circuit,

At

the

end

of

an

8

bit

vertical

word

a sync pulse is sent

which

looks at the ramp excursion, If the ramp exceeds

out

on the EOC (end of conversion) line

to

the

display

certain limits, the

output

from the

comparator

is an control

timing

block

and

through

the synchronizer

to

the

overspan signal

which

opens the video path

through

average calculator. When the sweep horizontal Signal has

switch U735B, A

dc

level is placed on the line

to

provide a traversed far

enough

to

generate a new horizontal ad-

baseline

for

the display, Unless overspan is detected, the dress,

the

EOC starts a three

cycle

sequence that

writes

a

video signal is fed

to

display

switch U735Cand thevertical vertical

word

in

memory at that address, This process

analog-to-digital

(AID) converter. The video information requires

27

JiS

(3

x 9 Jis). The rest

of

the

time

is utilized in

is converted

to

an 8 bit data

word

that appears in serial the display mode

to

read

from

memory. At

the

beginning

form on the Data

Out

line. The

clock

for

this

converter

is of the three

cycle

process

the

first cycle generates Start

1 MHz, derived

from

the 10 MHz master oscillator, so the Divide

to

the average calculator. The average

circuit

vertical data bits are 1

JiS

apart. Since there are 8 bits

per

divides

the

accumulated vertical data by

the

number

of

word

plus a sync pulse, each

word

takes 9

JiS

or

the

word

words

during

that period, and

the

resultant

or

quotient

is

rate is

111

kHz, The vertical data out, in serial form, then gated

into

memory

on the Math line, when the second

goes

to

an average

calculator

where it is

either

averaged

or

cycle

or

Write Cycle arrives. Write

Cycle

signal is

peak detected. The

output

(on the Math line) is then stored generated

only

when Valid

is

present. Valid is not present

at some address in memory.

during

retrace

or

when

the

dot

frequency

is changing-:-

2-6 REV. A MAY 1978

Scans

by

O"lso",ce.Options =>

Circuit Description-7L5 Service

The REFERENCE LEVEL drives U2235

which

provides

.f

column

data

current

for

the

top

right

vertical readout

-...:

position. The

output

of

the

U2235 is influenced by the

~

o

setting

of

the

dBm/dBV

selector and the offset set by the -

input

impedance

of

the

plug-in

module

and the reference

'-

level selected. The LIN

switch

latch changes the row data...f

so the readout is in nV,

JiV,

and mV instead

of

dBm

ordBV.

__

(The

column

data is also changed so the

correct

numbers

~

are read out.) :?-

The

address is derived

from

the

horizontal

sweep ramp.

This

is a 10 volt negative-going ramp centered around the

Dot

frequency.

The

ramp is offset (up

to

plus

or

minus

10

volts) as the

dot

frequency

is tuned so the sweep ramp

range can run

from

-10

V

to

+10

V

(-10

V

to

0 V at one

end and 0 V

to

+10

V at the other). The sweep is

converted, by the horizontal

AID

converter, to address

data

for

memory.

Memory

consists

of

a 4096 (512 x 8)

bit

RAM and a 1024 (1024 x 1)

bit

overflow

or

offset RAM. The

4096

bit

RAM has 512 horizontal access lines.

Memory

is

, divided

into

an A and B section with 256 lines assigned to

The FREQUENCY

SPAN/DIV

drives ROM U800

which-

each. Address locations are determined by the LSB (least

provides the

column

data

for

the

bottom

A horizontal

significant

bit)

of

the horizontal address word. Since the

position. Row data is from a fixed resistor matrix. If zero

-:

LSB

of

this

word

alternates with

any

count,

the

A and B

span is selected,

it

reads in time/division.

...A

locations in

memory

are adjacent with the odd bit

The RESOLUTION selectordrives a resistor matrixthat

provides both

column

and row data

to

the

bottom

right

vertical part

of

the display.

The

column

data also gets the

10 dB, 2 dB, or; if LIN

mode

is selected, that

portion

of

the

display

is a space.

Display Processing Block Diagram

0c

$ assigned

to

A

memory

and the even bit

to

B memory

~

sections.

The horizontal address is a

10

bit

word. The first 9 bits

(2

9) are derived from the sweep ramp and stored in the first

RAM. Thetenth

bit

(MSB) is stored in the

overflow

or

offset

RAM.

This

tenth bit signifies the offset (to the

right

or

left

of

center

screen)

of

a given address and since the offset

can

be

up

to

±10

V,

a 20

volt

ramp

capability

is provided.

The video signal from the IF processing chain is fed

,oo/eI,>

~

lOVMe

~{

through

switch U735B

to

an

AID

converter.

The

digital

-:

s;;.

Z

~

-'

1

~

21./i(

~'I

20(:>::0 -

data from theconverter is then placed in memory. It is read

'/

from

memory

and displayed at the

command

of

Display A

At

the slowersweep speeds, there are

numerous

words

and

Display B selectors. Before the vertical data is placed

of

vertical data

for

each

horizontal

address location.These

in memory,

it

may be

either

averaged

or

peak detected.

numerous

words

of

vertical data are averaged, by the

Vertical data is placed at an address in

memory

derived average calculator, so with a 10 second sweep rate, up

to

from the sweep horizontal waveform.

How

the address is 20,000 words are averaged at a horizontal address.

At

the

derived will be described later. C2 ms sweep rate,

only

four

words

would

be averaged.

~~s

/0'":

"'0"',

lv~

-:

512

/U("

i)/Ih'\..

Referring

to

the

lower

left side

of

the diagram, the 1st

~

1=

'12.

~

'I S''f'l.,/",,-1,;"

LO tune voltage ramp is fed

to

an

absolute value

circuit,

At

the

end

of

an

8

bit

vertical

word

a sync pulse is sent

which

looks at the ramp excursion, If the ramp exceeds

out

on the EOC (end of conversion) line

to

the

display

certain limits, the

output

from the

comparator

is an control

timing

block

and

through

the synchronizer

to

the

overspan signal

which

opens the video path

through

average calculator. When the sweep horizontal Signal has

switch U735B, A

dc

level is placed on the line

to

provide a traversed far

enough

to

generate a new horizontal ad-

baseline

for

the display, Unless overspan is detected, the dress,

the

EOC starts a three

cycle

sequence that

writes

a

video signal is fed

to

display

switch U735Cand thevertical vertical

word

in

memory at that address, This process

analog-to-digital

(AID) converter. The video information requires

27

JiS

(3

x 9 Jis). The rest

of

the

time

is utilized in

is converted

to

an 8 bit data

word

that appears in serial the display mode

to

read

from

memory. At

the

beginning

form on the Data

Out

line. The

clock

for

this

converter

is of the three

cycle

process

the

first cycle generates Start

1 MHz, derived

from

the 10 MHz master oscillator, so the Divide

to

the average calculator. The average

circuit

vertical data bits are 1

JiS

apart. Since there are 8 bits

per

divides

the

accumulated vertical data by

the

number

of

word

plus a sync pulse, each

word

takes 9

JiS

or

the

word

words

during

that period, and

the

resultant

or

quotient

is

rate is

111

kHz, The vertical data out, in serial form, then gated

into

memory

on the Math line, when the second

goes

to

an average

calculator

where it is

either

averaged

or

cycle

or

Write Cycle arrives. Write

Cycle

signal is

peak detected. The

output

(on the Math line) is then stored generated

only

when Valid

is

present. Valid is not present

at some address in memory.

during

retrace

or

when

the

dot

frequency

is changing-:-

2-6 REV. A MAY 1978

Scans

by

O"lso",ce.Options =>

The

output

of

the

horizontal

display

generator

consists

of

readout addresses

to

memory

and a synthesized

horizontal

sweep ramp

for

the

Store

horizontal

line.

Therefore, as

the

vertical data is read from memory, a

corresponding

change

occurs

in

the

horizontal

sweep

voltageso

the

vertical data written in

memory

is

duplicated

and

displayed

appropriately

when

it

is read out. Data

is

stored in

memory

at

the

rate set

by

the

Time/Div

selector;

however,

it

is

read from

memory

at a

constant

rate.

If

Display A is selected,

the

LSB

for

the address

out

of

the

horizontal

display

generator

remains a

1.

The

counter

counts

in odd

number

sequence so

only

data in A section

of

memory

is read. If Display B is selected, then the

counter

counts

in even

number

sequence and data in B

memory, is read out.

If

Display A and Display

Bare

selected then the LSB

for

the

address alternates and data

is read

first

from

A then

from

B memory.

If

Save A is

selected, A

memory

is

not

updated

during

Write Cycle. If

Display A is selected

along

with

Save A, then the data

stored in A, when Save A was pushed,

is

read out.

Vertical data

out

of

memory

goes

to

the vertical

display

generator

on

the

Memory

Data line. It is converted

to

analog data then processed

to

the

display

circuits.

A

timing

signal,

from

the vertical analog

to

digital

converter

block,

controls

when data

is

read

from

memory. Data can

only

be read

during

the

Read Cycle. When

either

Display A

or

Display B is selected,

the

display

control

block

sends a

Store signal

to

both

the

vertical and

horizontal

display

switches (U735A, U375C). Both

switches

then select

only

data

from

the

vertical

display

generator

and

the

synthesiz-

ed

sweep,

from

the

horizontal

display

generator

for

the

vertical and

horizontal

output

stages.

The inverted sweep

containing

dot

marker position is

summed

with

the

"dot

position"

when Q735 is on, at the

input

to the

horizontal

output

stage.

The

summation

of

minus sweep

with

dot

position

plus

"dot

position"

is

minus

sweep.

This

is

amplified

by the

output

amplifier

and

applied

to

the

crt

deflection

plates. When Q735

is

off,

only

the

"dot

position"

isapplied

to

the

output

amplifier

and the

crt

deflection

plates.

The

dot

is therefore displayed

independent

of

sweep. Sweep

horizontal

is

also applied

through

a separate

amplifier

to

the

front

panel

HORIZ

OUT

jack

and pin A3

of

the

mainframe

interface.

The

Z axis and

dot

logic

block

determine

when the

dot

is

to

be displayed. An

output

called

Dot

is

fed

to

multiplexer

switches

in

the

vertical and

horizontal

lines.

This

low

disconnects

the vertical and

horizontal

drive

to

the

mainframe

and

positions

the

dot

appropriately.

The

@

Circuit Description-7LS Service

logic

also provides

blanking

and un

blanking

to

the Z axis

by

blanking

just

before

the

dot

transition

and

unblanking

during

dot

presentation. It also blanks

during

the transi-

tion

back

to

normal

vertical and

horizontal

positioning.

Data

into

Z axis and

dot

logic

are Zero Span, Display Valid,

and the mainframe data such as Channel and Mode

information.

Peak/Average reference level

originates

with

the

PEAK/AVERAGE

front

panel

control.

This

reference is

compared

with

an analog signal

out

of

thevertical

analog-

to-digital

converter.

If

the vertical signal exceeds the

reference level set by the

control,

the

average

calculator

selects peak value. Signals

below

this reference are

averaged. The

control

functions

as

a Peak/Average selec-

tor

only

in the Store mode. Division between average and

peak

display

is

indicated

by

a

cursor

on screen. In

the

non-

store

mode

the

control

operates

as

a baseline clipper.

Vertical

information

below

the level set by the

control

is

blanked.

This

completes

the

block

diagram

description

for

the

7L5

circuitry.

DETAILED

CIRCUIT

DESCRIPTION

Sweep Control 0 0

<e>

This

portion

of

the

circuit

description

covers the

Auto

Sweep, Frequency Span and its Readout, and

Trigger

circuits.

Diagrams

3

through

6

cover

these

circuits.

The

Auto

Sweep

circuit

sets the sweep rate

according

to the

TIME/DIV

selections; or,

if

the

TIME/DIV

selector is

set

to

the

AUTO

position, the

circuit

automatically

adjusts

the sweep rate

as

a

function

of

the FREQUENCY

SPAN/DIV

and

RESOLUTION

selector

settings. If the

RESOLUTION

is

at

the

COUPLED

position,

with

the

TIME/DIV

at

AUTO,

the sweep rate and resolution are

automatically

computed

as

a

function

of

the

selected

frequency

span

to

keep

the

display

calibrated. When the

sweep rate is

not

compatible

to

the resolution and

frequency

span, the

circuit

activates a

front

panel

UNCAL

indicator.

The

TIME/DIV

selector

assembly

outputs

a 5

bit

address,

as

shown

in

the

truth

table.

Four

bits

of

this

address are fed

to

one

side

of

four

section

multiplexer

U525.

The

B

inputs

to the

multiplexer

are selected when

the Select (pin 1) line is high, so

the

TIME/DIV

assembly

output

is

switched

through

to

the sweep

generator

circuit

2-7

Scam

by

Outsource-Options =>

The

output

of

the

horizontal

display

generator

consists

of

readout addresses

to

memory

and a synthesized

horizontal

sweep ramp

for

the

Store

horizontal

line.

Therefore, as

the

vertical data is read from memory, a

corresponding

change

occurs

in

the

horizontal

sweep

voltageso

the

vertical data written in

memory

is

duplicated

and

displayed

appropriately

when

it

is read out. Data

is

stored in

memory

at

the

rate set

by

the

Time/Div

selector;

however,

it

is

read from

memory

at a

constant

rate.

If

Display A is selected,

the

LSB

for

the address

out

of

the

horizontal

display

generator

remains a

1.

The

counter

counts

in odd

number

sequence so

only

data in A section

of

memory

is read. If Display B is selected, then the

counter

counts

in even

number

sequence and data in B

memory, is read out.

If

Display A and Display

Bare

selected then the LSB

for

the

address alternates and data

is read

first

from

A then

from

B memory.

If

Save A is

selected, A

memory

is

not

updated

during

Write Cycle. If

Display A is selected

along

with

Save A, then the data

stored in A, when Save A was pushed,

is

read out.

Vertical data

out

of

memory

goes

to

the vertical

display

generator

on

the

Memory

Data line. It is converted

to

analog data then processed

to

the

display

circuits.

A

timing

signal,

from

the vertical analog

to

digital

converter

block,

controls

when data

is

read

from

memory. Data can

only

be read

during

the

Read Cycle. When

either

Display A

or

Display B is selected,

the

display

control

block

sends a

Store signal

to

both

the

vertical and

horizontal

display

switches (U735A, U375C). Both

switches

then select

only

data

from

the

vertical

display

generator

and

the

synthesiz-

ed

sweep,

from

the

horizontal

display

generator

for

the

vertical and

horizontal

output

stages.

The inverted sweep

containing

dot

marker position is

summed

with

the

"dot

position"

when Q735 is on, at the

input

to the

horizontal

output

stage.

The

summation

of

minus sweep

with

dot

position

plus

"dot

position"

is

minus

sweep.

This

is

amplified

by the

output

amplifier

and

applied

to

the

crt

deflection

plates. When Q735

is

off,

only

the

"dot

position"

isapplied

to

the

output

amplifier

and the

crt

deflection

plates.

The

dot

is therefore displayed

independent

of

sweep. Sweep

horizontal

is

also applied

through

a separate

amplifier

to

the

front

panel

HORIZ

OUT

jack

and pin A3

of

the

mainframe

interface.

The

Z axis and

dot

logic

block

determine

when the

dot

is

to

be displayed. An

output

called

Dot

is

fed

to

multiplexer

switches

in

the

vertical and

horizontal

lines.

This

low

disconnects

the vertical and

horizontal

drive

to

the

mainframe

and

positions

the

dot

appropriately.

The

@

Circuit Description-7LS Service

logic

also provides

blanking

and un

blanking

to

the Z axis

by

blanking

just

before

the

dot

transition

and

unblanking

during

dot

presentation. It also blanks

during

the transi-

tion

back

to

normal

vertical and

horizontal

positioning.

Data

into

Z axis and

dot

logic

are Zero Span, Display Valid,

and the mainframe data such as Channel and Mode

information.

Peak/Average reference level

originates

with

the

PEAK/AVERAGE

front

panel

control.

This

reference is

compared

with

an analog signal

out

of

thevertical

analog-

to-digital

converter.

If

the vertical signal exceeds the

reference level set by the

control,

the

average

calculator

selects peak value. Signals

below

this reference are

averaged. The

control

functions

as

a Peak/Average selec-

tor

only

in the Store mode. Division between average and

peak

display

is

indicated

by

a

cursor

on screen. In

the

non-

store

mode

the

control

operates

as

a baseline clipper.

Vertical

information

below

the level set by the

control

is

blanked.

This

completes

the

block

diagram

description

for

the

7L5

circuitry.

DETAILED

CIRCUIT

DESCRIPTION

Sweep Control 0 0

<e>

This

portion

of

the

circuit

description

covers the

Auto

Sweep, Frequency Span and its Readout, and

Trigger

circuits.

Diagrams

3

through

6

cover

these

circuits.

The

Auto

Sweep

circuit

sets the sweep rate

according

to the

TIME/DIV

selections; or,

if

the

TIME/DIV

selector is

set

to

the

AUTO

position, the

circuit

automatically

adjusts

the sweep rate

as

a

function

of

the FREQUENCY

SPAN/DIV

and

RESOLUTION

selector

settings. If the

RESOLUTION

is

at

the

COUPLED

position,

with

the

TIME/DIV

at

AUTO,

the sweep rate and resolution are

automatically

computed

as

a

function

of

the

selected

frequency

span

to

keep

the

display

calibrated. When the

sweep rate is

not

compatible

to

the resolution and

frequency

span, the

circuit

activates a

front

panel

UNCAL

indicator.

The

TIME/DIV

selector

assembly

outputs

a 5

bit

address,

as

shown

in

the

truth

table.

Four

bits

of

this

address are fed

to

one

side

of

four

section

multiplexer

U525.

The

B

inputs

to the

multiplexer

are selected when

the Select (pin 1) line is high, so

the

TIME/DIV

assembly

output

is

switched

through

to

the sweep

generator

circuit

2-7

Scam

by

Outsource-Options =>

Circuit

Description-7L5

Service

(Diagram 6). If the

AUTO

position

is selected, U530D is

enabled.

This

pulls

pin 1

of

U525

low

and

switches

the

multiplexer

to

its A inputs.

The

sweep rate is

now

a

function

of

the address

out

of

ROM U515.

The

output

address

of

ROM U515 is a

function

of

the

FREQUENCY

SPAN/DIV

and

RESOLUTION

control

set-

tings.

This

address is also fed

to

the

B

inputs

of

com-

parator

U540 where

it

is

compared

with

the

TIME/DIV

setting.

If

the

code

from

the

TIME/DIV

selector

is less than

the

code

out

of

ROM U515,

the

output

of

comparator

U540

goes

high

and,

when

inverted

by

U520E,

pulls

the

Uncal

line

low

to

activate the

UNCAL

light

and

generate

a

(»

symbol

as a prefex

to

the reference level readout.

When the

RESOLUTION

selector

is in

the

COUPLED

position,

ROM U515 selects

resolution

that

is

compatible

for

the

frequency

span selected.

The

CMOS

outputs

for

the FREQUENCY

SPAN/DIV

assembly are

converted

to

TTL

by

the

buffers

(U510A,

B,

D,

E,

and

F)

to

accom-

modate

ROM (U650) in

the

Frequency

Span

circuit.

The

outputs

of

the

TIME/DIV

and FREQUENCY

SPAN/DIV

selectors, are

Darlington

pairs

which

pull

down

to

about

1.0 volt.

The

low

state

is

offset

two

junctions

below

ground,

by

CR64

and

CR66

through

R512,

to

-15

V;

so a

logic

low

at

the

output

is

about

ground

potential.

Logic

high

is

pulled

up

through

resistors in

resistor

pack

R60.

The

arm

of

the

RESOLUTION

switch

is

connected

to

the

collector

of

Q70.

With

resistor

pack

R60A in the

circuit,

the

transistor

is saturated

and

ground

return is

furnished

to

the

switch.

With

the

resistor

pack

removed the base

of

the

transistor

is

connected

to

the

remote

prog

ram lineand

the

output

is

dependent

on

the external

program.

Diodes

CR74

through

CR76

provide

isolation.

There

are five lines

that

determine

the sweep speed;

four

from

multiplexer

U525 and the

fifth

from

the

output

of

NAND

gate

U535C.

The

sweep

generator

(Diagram

6)

consists

of

Miller

integrator

U700

with

timing

capacitors

C712A and C712B.

Capacitor

C712B is

switched

into

the

timing

circuit

when

the

input

line

to

pin 9

of

multiplexer,

(U80C) is low. C712 is in

the

circuit

for

sweep rates

of

10 ms

or

slower. When

the

level

at

pin 9 is

high,

the

switch

opens,

and

C712B is

out

of

the

timing

circuit.

Timing

resistors are selected

by

multiplexer

U695.

Control

lines A,

B,

and C

(pins

11, 10, and 9) select the

2-8

timing

resistors as

indicated

by

the address

table

within

the

symbol

for

U695. Voltage reference

for

the selected

timing

resistor

is

the

output

of

operational

amplifier

U690A. When Q680 is

turned

on,

timing

voltage

is

increased

by

a

factor

of

two

which

increases the sweep

speed

proportionately.

Table

2-1

lists the

Time/Div

selec-

tions

with

the

output

addresses and the

corresponding

addresses

for

U695, Q680 gate, and pin 9

of

U680C.

For

example; 50 ms

connects

timing

resistor

R694,

connects

timing

capacitor

C712B, and

turns

off

Q680

to

add R686 as

part

of

Ri

(input

resistor)

for

operational

amplifier

U680A.

The

Miller

integrator

is gated

on

by

the

+Gate

signal

into

the base

of

Q705.

This

gate

switches

Q700

off

and

allows

the

Miller

integrator

output

to

ramp up.

The

output

of

the sweep

generator

is fed

to

one

input

of

comparator

U575A

whose

output

switches

high

when

the

input

ramp

reaches

the

reference level, set

by

the

divider

network

on

the

other

input

of

the

comparator

or

about

8.9 volts.

This

Sweep

Inhibit

signal is fed

back

to

the

sweep

controllC

to

terminate

the sweep gate. Unless Manual sweep has been

selected,

the

sweep ramp is also fed

through

multiplexer

U680B

to

operational

amplifier

U685A. Gain

of

U685A is

about

1.2

producing

an

output

ramp

of

approximately

10.4

volt.

This

ramp is fed

to

the

frequency

span

attenuator

circuit,

containing

R660-U665, and

to

the

horizontal

sweep

processing

circuit.

TABLE

2-1

Truth

Table

for

TIME/DIV

Selections

TIME/DIV

SWEEP

CONTROL

ST ST ST ST ST U695 Q680

5 4 3 2 1 A B C

GATE

U680C-9

ms

.1

a a a a a a a 1 1 1

.2

a a a a 1 a a 1 a 1

.5

a a a 1 1 a a a a 1

1 a a 1 a a a 1 1 1 1

2 a a 1 a 1 a 1 1 a 1

5 a a 1 1 1 a 1 a a 1

10 a 1 a a a a a 1 1 a

20 a 1 a a 1 a a 1 a a

50 a 1 a 1 1 a a a a a

-sec

.1

a 1 1 a a a 1 1 1 a

.2

a 1 1 a 1 a 1 1 a a

.5

a 1 1 1 1 a 1 a a a

1 1 a a a a 1 a 1 1 a

2 1 a a a 1 1 a 1 a a

3 1 a a 1 1 1 a a a a

10 1 a 1 a a 1 1 1 1 a

AUTO'

1 1 1 1 a 1 1 a 1 a

@

Scans by Outsource.Optio"s

=>

Circuit

Description-7L5

Service

(Diagram 6). If the

AUTO

position

is selected, U530D is

enabled.

This

pulls

pin 1

of

U525

low

and

switches

the

multiplexer

to

its A inputs.

The

sweep rate is

now

a

function

of

the address

out

of

ROM U515.

The

output

address

of

ROM U515 is a

function

of

the

FREQUENCY

SPAN/DIV

and

RESOLUTION

control

set-

tings.

This

address is also fed

to

the

B

inputs

of

com-

parator

U540 where

it

is

compared

with

the

TIME/DIV

setting.

If

the

code

from

the

TIME/DIV

selector

is less than

the

code

out

of

ROM U515,

the

output

of

comparator

U540

goes

high

and,

when

inverted

by

U520E,

pulls

the

Uncal

line

low

to

activate the

UNCAL

light

and

generate

a

(»

symbol

as a prefex

to

the reference level readout.

When the

RESOLUTION

selector

is in

the

COUPLED

position,

ROM U515 selects

resolution

that

is

compatible

for

the

frequency

span selected.

The

CMOS

outputs

for

the FREQUENCY

SPAN/DIV

assembly are

converted

to

TTL

by

the

buffers

(U510A,

B,

D,

E,

and

F)

to

accom-

modate

ROM (U650) in

the

Frequency

Span

circuit.

The

outputs

of

the

TIME/DIV

and FREQUENCY

SPAN/DIV

selectors, are

Darlington

pairs

which

pull

down

to

about

1.0 volt.

The

low

state

is

offset

two

junctions

below

ground,

by

CR64

and

CR66

through

R512,

to

-15

V;

so a

logic

low

at

the

output

is

about

ground

potential.

Logic

high

is

pulled

up

through

resistors in

resistor

pack

R60.

The

arm

of

the

RESOLUTION

switch

is

connected

to

the

collector

of

Q70.

With

resistor

pack

R60A in the

circuit,

the

transistor

is saturated

and

ground

return is

furnished

to

the

switch.

With

the

resistor

pack

removed the base

of

the

transistor

is

connected

to

the

remote

prog

ram lineand

the

output

is

dependent

on

the external

program.

Diodes

CR74

through

CR76

provide

isolation.

There

are five lines

that

determine

the sweep speed;

four

from

multiplexer

U525 and the

fifth

from

the

output

of

NAND

gate

U535C.

The

sweep

generator

(Diagram

6)

consists

of

Miller

integrator

U700

with

timing

capacitors

C712A and C712B.

Capacitor

C712B is

switched

into

the

timing

circuit

when

the

input

line

to

pin 9

of

multiplexer,

(U80C) is low. C712 is in

the

circuit

for

sweep rates

of

10 ms

or

slower. When

the

level

at

pin 9 is

high,

the

switch

opens,

and

C712B is

out

of

the

timing

circuit.

Timing

resistors are selected

by

multiplexer

U695.

Control

lines A,

B,

and C

(pins

11, 10, and 9) select the

2-8

timing

resistors as

indicated

by

the address

table

within

the

symbol

for

U695. Voltage reference

for

the selected

timing

resistor

is

the

output

of

operational

amplifier

U690A. When Q680 is

turned

on,

timing

voltage

is

increased

by

a

factor

of

two

which

increases the sweep

speed

proportionately.

Table

2-1

lists the

Time/Div

selec-

tions

with

the

output

addresses and the

corresponding

addresses

for

U695, Q680 gate, and pin 9

of

U680C.

For

example; 50 ms

connects

timing

resistor

R694,

connects

timing

capacitor

C712B, and

turns

off

Q680

to

add R686 as

part

of

Ri

(input

resistor)

for

operational

amplifier

U680A.

The

Miller

integrator

is gated

on

by

the

+Gate

signal

into

the base

of

Q705.

This

gate

switches

Q700

off

and

allows

the

Miller

integrator

output

to

ramp up.

The

output

of

the sweep

generator

is fed

to

one

input

of

comparator

U575A

whose

output

switches

high

when

the

input

ramp

reaches

the

reference level, set

by

the

divider

network

on

the

other

input

of

the

comparator

or

about

8.9 volts.

This

Sweep

Inhibit

signal is fed

back

to

the

sweep

controllC

to

terminate

the sweep gate. Unless Manual sweep has been

selected,

the

sweep ramp is also fed

through

multiplexer

U680B

to

operational

amplifier

U685A. Gain

of

U685A is

about

1.2

producing

an

output

ramp

of

approximately

10.4

volt.

This

ramp is fed

to

the

frequency

span

attenuator

circuit,

containing

R660-U665, and

to

the

horizontal

sweep

processing

circuit.

TABLE

2-1

Truth

Table

for

TIME/DIV

Selections

TIME/DIV

SWEEP

CONTROL

ST ST ST ST ST U695 Q680

5 4 3 2 1 A B C

GATE

U680C-9

ms

.1

a a a a a a a 1 1 1

.2

a a a a 1 a a 1 a 1

.5

a a a 1 1 a a a a 1

1 a a 1 a a a 1 1 1 1

2 a a 1 a 1 a 1 1 a 1

5 a a 1 1 1 a 1 a a 1

10 a 1 a a a a a 1 1 a

20 a 1 a a 1 a a 1 a a

50 a 1 a 1 1 a a a a a

-sec

.1

a 1 1 a a a 1 1 1 a

.2

a 1 1 a 1 a 1 1 a a

.5

a 1 1 1 1 a 1 a a a

1 1 a a a a 1 a 1 1 a

2 1 a a a 1 1 a 1 a a

3 1 a a 1 1 1 a a a a

10 1 a 1 a a 1 1 1 1 a

AUTO

1 1 1 1 a 1 1 a 1 a

@

Scans by Outsource.Optio"s

=>

Holdoff

timing

capacitors,

for

the

sweep

control

IC

(U580

on

Diagram

5), are C728 and C726. When the

logic

input

(pin 11) to

multiplexer

U680A is

low,

C726 parallels

C728

to

increase

the

time

constant.

The

other

output

of

U680A

(pin 13) drives the base

of

the

transistor

in U585C

to

provide

intensity

limiting

to

the

mainframe

at

the

slower

sweep speeds

(below

10

ms/div).

At

faster speeds, the

input

line

is

high

and pin 13 is

grounded,

so U585C

is

biased

off

to

remove

intensity

limiting.

In manual

modeor,

when

operating

with

spans

other

than

0 Hz, the

low

state

into

U595D

turns

U585C

on

to

provide

intensity

limiting.

Intensity

limiting

is

therefore

provided

for

manual sweep

operation,

sweep rates

below

10

ms/div,

and 0 Hz span

operation.

Multiplexer

U665 selects

the

attenuation

ratio

for

the

10.4

volt

sweep

ramp

through

resistor pack R660.

The

attenuation

address (in at

A,

B,

and C

of

U665)

determines

the

attenuation.

The

sweep

out

of

U665

is

then fed

through

multiplexer

U670

to

one

of

four

output

lines.

Three

of

these (1A, 1

B,

and #2) drive the A and B

oscillators

which

establish

the

frequency

span.

The

fourth

line

is

for

optional

use if desired.

the

address

within

the

IC

symbols

indicate

the

sweep

ramp

path

through

R660 and U670.

For

example;

when

the

input

address

to

U665 is 110,

2

of

U665 is

connected

to

the

output.

The

sweep

is

attenuated

through

R660

by

the

combination

of

the 4.00 k and 1.33 k

resistors.

Table

2-2 and 2-3

show

the

input

and

output

data

for

ROM U650 and

multiplexers

U665 and U670.

Table

2-2

shows

the

Data

Out

of

U650

with

the

corresponding

sweep

Circuil

Descriplion-7L5

Service

output

line.

For

example;

with

a

FREQUENCY

SPAN/DIV

of

50 kHz,

input

lines A and B

to

U670 are low. Address 00

(into

U670)

switches

the

sweep

output

of

U665

to

pin 12

of

U670

to

drive

the B

oscillator.

Table

2-4 lists the sweep

for

each

SPAN/DIV

setting.

The

table

bypasses ROMs U510

and U650.

The

Max

Span

Dot

Position

adjustment

(R655) offsets

the

dc

level

of

the

memory

voltage

so a

voltage

of

0

corresponds

to

center

screen (2.5 MHz).

It

also offsetsthe

dc level

of

the

1st La

tune

voltage

soa

center

frequency

of

2.5

MHz

corresponds

to

0

Vat

the

output

(pin 3)

of

U675B

for

centering

the overspan

clipping.

The

1st

La

tune

voltage

is a

positive-going

ramp,

centered

around

some

dc

level set

by

the

DOT

FRE-

QUENCY

control.

The

amplitude

of

this

sweep

voltage

depends

on

the

setting

of

the

FREQUENCY

SPAN/DIV

selector. U675A, U575C, and U575A

limit

the

excursion

of

the

waveform. U675B, a

non-inverting

amplifier,

drivesthe

negative

input

of

operational

amplifier

U675A. As the

sweep ramp crosses its

center

point,

diode

CR660

dis-

connects

and the

polarity

of

the

input

signal to the

comparator

U575C reverses.

The

input

waveform

to pin 7

of

U575C is

therefore

V shaped.

This

input

is referenced

(by a

voltage

divider)

to

about

4.5 volts.

If

either

excursion

of

the V shaped

waveform

exceeds

this

reference, a

positive

output

signal is

produced

which

represents an

overspan.

This

overspan

voltage

is

fed to a

multiplexer

(U735B), in

the

video

processing

chain, and the

output

of

TABLE 2-2

Input and Output Data

for

U650 (8223 ROM)

FREQ

INPUT

OCTAL DATA OCTAL

SPAN/DIV

ADDRESS(BINARY} EQUIV OUTPUT(BINARY} EQUIV SWP

A4 A3

A2

Al

Ao

B7

B6

B5 B4 B3 B2

Bl

Bo

MAX

SPAN 1 1 0 1 1 33 1 1 0 1 0 1 0 1 325 1A

200

kHz

1 1 1 1 1 37 0 0 1 1 0 1 0 1 065 1B

100 kHz 1 1 1 1 0 36 1 0 0 1 0 1 0 1 225

1B

50

kHz

1 1 0 0 1

31

1 0 1 1 0 1 0 1 265 1B

20 kHz 1 1 1 0 1 35 0 0 1 1 0 1 0 1 065

1B

10 kHz 1 1 1 0 0 34 1 0 0 1 0 1 0 1 225 1B

5

kHz

1 0 0 1 1 23 1 0 1 1 0 1 0 1 265 1B

2 kHz 1 0 1 1 1 27 0 1 1 1 0 1 1 0 166 #2

1 kHz 1 0 1 1 0 26 1 1 0 1 0 1 1 0 326 #2

.5

kHz

1 0 0 0 1

21

1 1 1 1 0 1 1 0 366 #2

.2

kHz 1 0 1 0 1 25 0 1 1 1 0 1 1 0 166 #2

.1

kHz 1 0 1 0 0 24 1 1 0 1 0 1 1 0 326 #2

50 Hz 0 1 0 1 1 13 1 1 1 1 0 1 1 0 366 #2

o

Hz

0 0 1 0 0 04 1 0 1 0 1 1 1 1 257 0

B A

Control

Line

U670

Line

U670

@ 2-9

Scans bp Outsource-Options

=>

Holdoff

timing

capacitors,

for

the

sweep

control

IC

(U580

on

Diagram

5), are C728 and C726. When the

logic

input

(pin 11) to

multiplexer

U680A is

low,

C726 parallels

C728

to

increase

the

time

constant.

The

other

output

of

U680A

(pin 13) drives the base

of

the

transistor

in U585C

to

provide

intensity

limiting

to

the

mainframe

at

the

slower

sweep speeds

(below

10

ms/div).

At

faster speeds, the

input

line

is

high

and pin 13 is

grounded,

so U585C

is

biased

off

to

remove

intensity

limiting.

In manual

modeor,

when

operating

with

spans

other

than

0 Hz, the

low

state

into

U595D

turns

U585C

on

to

provide

intensity

limiting.

Intensity

limiting

is

therefore

provided

for

manual sweep

operation,

sweep rates

below

10

ms/div,

and 0 Hz span

operation.

Multiplexer

U665 selects

the

attenuation

ratio

for

the

10.4

volt

sweep

ramp

through

resistor pack R660.

The

attenuation

address (in at

A,

B,

and C

of

U665)

determines

the

attenuation.

The

sweep

out

of

U665

is

then fed

through

multiplexer

U670

to

one

of

four

output

lines.

Three

of

these (1A, 1

B,

and #2) drive the A and B

oscillators

which

establish

the

frequency

span.

The

fourth

line

is

for

optional

use if desired.

the

address

within

the

IC

symbols

indicate

the

sweep

ramp

path

through

R660 and U670.

For

example;

when

the

input

address

to

U665 is 110,

2

of

U665 is

connected

to

the

output.

The

sweep

is

attenuated

through

R660

by

the

combination

of

the 4.00 k and 1.33 k

resistors.

Table

2-2 and 2-3

show

the

input

and

output

data

for

ROM U650 and

multiplexers

U665 and U670.

Table

2-2

shows

the

Data

Out

of

U650

with

the

corresponding

sweep

Circuil

Descriplion-7L5

Service

output

line.

For

example;

with

a

FREQUENCY

SPAN/DIV

of

50 kHz,

input

lines A and B

to

U670 are low. Address 00

(into

U670)

switches

the

sweep

output

of

U665

to

pin 12

of

U670

to

drive

the B

oscillator.

Table

2-4 lists the sweep

for

each

SPAN/DIV

setting.

The

table

bypasses ROMs U510

and U650.

The

Max

Span

Dot

Position

adjustment

(R655) offsets

the

dc

level

of

the

memory

voltage

so a

voltage

of

0

corresponds

to

center

screen (2.5 MHz).

It

also offsetsthe

dc level

of

the

1st La

tune

voltage

soa

center

frequency

of

2.5

MHz

corresponds

to

0

Vat

the

output

(pin 3)

of

U675B

for

centering

the overspan

clipping.

The

1st

La

tune

voltage

is a

positive-going

ramp,

centered

around

some

dc

level set

by

the

DOT

FRE-

QUENCY

control.

The

amplitude

of

this

sweep

voltage

depends

on

the

setting

of

the

FREQUENCY

SPAN/DIV

selector. U675A, U575C, and U575A

limit

the

excursion

of

the

waveform. U675B, a

non-inverting

amplifier,

drivesthe

negative

input

of

operational

amplifier

U675A. As the

sweep ramp crosses its

center

point,

diode

CR660

dis-

connects

and the

polarity

of

the

input

signal to the

comparator

U575C reverses.

The

input

waveform

to pin 7

of

U575C is

therefore

V shaped.

This

input

is referenced

(by a

voltage

divider)

to

about

4.5 volts.

If

either

excursion

of

the V shaped

waveform

exceeds

this

reference, a

positive

output

signal is

produced

which

represents an

overspan.

This

overspan

voltage

is

fed to a

multiplexer

(U735B), in

the

video

processing

chain, and the

output

of

TABLE 2-2

Input and Output Data

for

U650 (8223 ROM)

FREQ

INPUT

OCTAL DATA OCTAL

SPAN/DIV

ADDRESS(BINARY} EQUIV OUTPUT(BINARY} EQUIV SWP

A4 A3

A2

Al

Ao

B7

B6

B5 B4 B3 B2

Bl

Bo

MAX

SPAN 1 1 0 1 1 33 1 1 0 1 0 1 0 1 325 1A

200

kHz

1 1 1 1 1 37 0 0 1 1 0 1 0 1 065 1B

100 kHz 1 1 1 1 0 36 1 0 0 1 0 1 0 1 225

1B

50

kHz

1 1 0 0 1

31

1 0 1 1 0 1 0 1 265 1B

20 kHz 1 1 1 0 1 35 0 0 1 1 0 1 0 1 065

1B

10 kHz 1 1 1 0 0 34 1 0 0 1 0 1 0 1 225 1B

5

kHz

1 0 0 1 1 23 1 0 1 1 0 1 0 1 265 1B

2 kHz 1 0 1 1 1 27 0 1 1 1 0 1 1 0 166 #2

1 kHz 1 0 1 1 0 26 1 1 0 1 0 1 1 0 326 #2

.5

kHz

1 0 0 0 1

21

1 1 1 1 0 1 1 0 366 #2

.2

kHz 1 0 1 0 1 25 0 1 1 1 0 1 1 0 166 #2

.1

kHz 1 0 1 0 0 24 1 1 0 1 0 1 1 0 326 #2

50 Hz 0 1 0 1 1 13 1 1 1 1 0 1 1 0 366 #2

o

Hz

0 0 1 0 0 04 1 0 1 0 1 1 1 1 257 0

B A

Control

Line

U670

Line

U670

@ 2-9

Scans bp Outsource-Options

=>

Circuit

Description-7L5

Service

the

detector

is

disconnected

from

the

vertical

output

amplifier.

The

vertical

display

now

becomes

a

dc

voltage

which

produces

a

trace

at

the

bottom

of

the

screen. In

non-

store

mode

the

overspan

portion

is blanked.

The

lower

half

of

multiplexer

U670

provides

a

dc

offset

to

the

sweep ramp. In

the

MAX

span

position,

the

DOT

FREQUENCY

control

moves

the

dot

(readout)

frequency

across

the

screen. In

other

SPAN/DIV

positions,

the

dot

is

at

center

screen unless

it

is moved

by

the

DOT

MKR

control.

The

dot

always

represents

readout

frequency.

The

dc

level, set

by

the

DOT

MKR

control

(RSO)

feeds

three

of

the

inputs

for

the

bottom

half

of

U670.

If

the

control

address

to

U670

(from

ROM U6S0) is

anything

except

10,

the

dc

level

of

the

DOT

MKR

control

is

switched

through

U670

to

the

input

of

operational

amplifier

U68SB.

Address

code

10

occurs

only

when

the

FREQUENCY

SPAN/DIV

selector

is in

MAX

span

position.

The

offset

voltage

now

comes

from

the

synthesizer

memory

circuits.

The

dc

output

of

U68SB sets

the

input

dc

level

of

the

sweep

amplifier

U68SA

to

provide

offset

to

the

Sweep

Horizontal

ramp.

TABLE

2-3

Input

Data

to

the

Frequency

Span

"ROMS"

U515 U650

FREQ

SPAN/DIY

FREQ

SPAN/DIY

SWITCH

INPUTS INPUTS

TC

TJ

TB

TK

TD

A8 A7 A6

AS

A4 A4 A3 A2

A1

AO

MAX

0 0 0 0 0 1 1 1 1 0 1 1 0 1 1

.2

MHz

0 0 0 1 0 1 1 1 1 1 1 1 1 1 1

.1

MHz

0 0 0 1 1 1 1 1 0 1 1 1 1 1 0

SO

kHz

0 0 1 0 0 0 1 1 1 0 1 1 0 0 1

20 kHz 0 0 1 1 0 0 1 1 1 1 1 1 1 0 1

10

kHz

0 0 1 1 1 0 1 1 0 1 1 1 1 0 0

S

kHz

0 1 0 0 0 1 0 1 1 0 1 0 0 1 1

2

kHz

0 1 0 1 0 1 0 1 1 1 1 0 1 1 1

1

kHz

0 1 0 1 1 1 0 1 0 1 1 0 1 1 0

.S

kHz

0 1 1 0 0 0 0 1 1 0 1 0 0 0 1

.2

kHz

0 1 1 1 0 0 0 1 1 1 1 0 1 0 1

.1

kHz

0 1 1 1 1 0 0 1 0 1 1 0 1 0 0

SO

Hz 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1

o

Hz

1 1 1 1 1 0 0 0 0 1 0 0 1 0 0

TABLE

2-4

Input

and

Output

Data

for

FREQ

SPAN

Multiplexers,

Bypassing

U510

and

U650

FREQ

SPAN/DIY

FREQ

SPAN/DIY

SWITCH

U670 U665

TC

TJ

TB

TK

TD

(FSS) (FS4) (FS3) (FS2) (FS1) B A SWP C B A

MAX

0 0 0 0 0 1 0

1A

0 1 1

.2

MHz

0 0 0 1 0 0 0

1B

0 0 0

.1

MHz

0 0 0 1 1 0 0

1B

0 0 1

SO

kHz

0 0 1 0 0 0 0 1B 1 1 0

20

kHz

0 0 1 1 0 0 0 1B 1 0 0

10 kHz 0 0 1 1 1 0 0

1B

1 0 1

S kHz 0 1 0 0 0 0 0

1B

0 1 0

2 kHz 0 1 0 1 0 1 1 #2 0 0 0

1

kHz

0 1 0 1 1 1 1 #2 0 0 1

.S

kHz

0 1 1 0 0 1 1 #2 1 1 0

.2 kHz 0 1 1 1 0 1 1 #2 1 0 0

.1

kHz

0 1 1 1 1 1 1 #2 1 0 1

SO

Hz

1 0 0 0 0 1 1 #2 0 1 0

o

Hz

1 1 1 1 1 0 1 0 1 0 0

2-10 @

Scans

by

O.bo.ree-Options =>

Circuit

Description-7L5

Service

the

detector

is

disconnected

from

the

vertical

output

amplifier.

The

vertical

display

now

becomes

a

dc

voltage

which

produces

a

trace

at

the

bottom

of

the

screen. In

non-

store

mode

the

overspan

portion

is blanked.

The

lower

half

of

multiplexer

U670

provides

a

dc

offset

to

the

sweep ramp. In

the

MAX

span

position,

the

DOT

FREQUENCY

control

moves

the

dot

(readout)

frequency

across

the

screen. In

other

SPAN/DIV

positions,

the

dot

is

at

center

screen unless

it

is moved

by

the

DOT

MKR

control.

The

dot

always

represents

readout

frequency.

The

dc

level, set

by

the

DOT

MKR

control

(RSO)

feeds

three

of

the

inputs

for

the

bottom

half

of

U670.

If

the

control

address

to

U670

(from

ROM U6S0) is

anything

except

10,

the

dc

level

of

the

DOT

MKR

control

is

switched

through

U670

to

the

input

of

operational

amplifier

U68SB.

Address

code

10

occurs

only

when

the

FREQUENCY

SPAN/DIV

selector

is in

MAX

span

position.

The

offset

voltage

now

comes

from

the

synthesizer

memory

circuits.

The

dc

output

of

U68SB sets

the

input

dc

level

of

the

sweep

amplifier

U68SA

to

provide

offset

to

the

Sweep

Horizontal

ramp.

TABLE

2-3

Input

Data

to

the

Frequency

Span

"ROMS"

U515 U650

FREQ

SPAN/DIY

FREQ

SPAN/DIY

SWITCH

INPUTS INPUTS

TC

TJ

TB

TK

TD

A8 A7 A6

AS

A4 A4 A3 A2

A1

AO

MAX

0 0 0 0 0 1 1 1 1 0 1 1 0 1 1

.2

MHz

0 0 0 1 0 1 1 1 1 1 1 1 1 1 1

.1

MHz

0 0 0 1 1 1 1 1 0 1 1 1 1 1 0

SO

kHz

0 0 1 0 0 0 1 1 1 0 1 1 0 0 1

20 kHz 0 0 1 1 0 0 1 1 1 1 1 1 1 0 1

10

kHz

0 0 1 1 1 0 1 1 0 1 1 1 1 0 0

S

kHz

0 1 0 0 0 1 0 1 1 0 1 0 0 1 1

2

kHz

0 1 0 1 0 1 0 1 1 1 1 0 1 1 1

1

kHz

0 1 0 1 1 1 0 1 0 1 1 0 1 1 0

.S

kHz

0 1 1 0 0 0 0 1 1 0 1 0 0 0 1

.2

kHz

0 1 1 1 0 0 0 1 1 1 1 0 1 0 1

.1

kHz

0 1 1 1 1 0 0 1 0 1 1 0 1 0 0

SO

Hz 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1

o

Hz

1 1 1 1 1 0 0 0 0 1 0 0 1 0 0

TABLE

2-4

Input

and

Output

Data

for

FREQ

SPAN

Multiplexers,

Bypassing

U510

and

U650

FREQ

SPAN/DIY

FREQ

SPAN/DIY

SWITCH

U670 U665

TC

TJ

TB

TK

TD

(FSS) (FS4) (FS3) (FS2) (FS1) B A SWP C B A

MAX

0 0 0 0 0 1 0

1A

0 1 1

.2

MHz

0 0 0 1 0 0 0

1B

0 0 0

.1

MHz

0 0 0 1 1 0 0

1B

0 0 1

SO

kHz

0 0 1 0 0 0 0 1B 1 1 0

20

kHz

0 0 1 1 0 0 0 1B 1 0 0

10 kHz 0 0 1 1 1 0 0

1B

1 0 1

S kHz 0 1 0 0 0 0 0

1B

0 1 0

2 kHz 0 1 0 1 0 1 1 #2 0 0 0

1

kHz

0 1 0 1 1 1 1 #2 0 0 1

.S

kHz

0 1 1 0 0 1 1 #2 1 1 0

.2 kHz 0 1 1 1 0 1 1 #2 1 0 0

.1

kHz

0 1 1 1 1 1 1 #2 1 0 1

SO

Hz

1 0 0 0 0 1 1 #2 0 1 0

o

Hz

1 1 1 1 1 0 1 0 1 0 0

2-10 @

Scans

by

O.bo.ree-Options =>

Tektronix 7L5 User manual

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