ARM ARM7TDMI Operating and maintenance manual

Open Access
Beta Draft
ENGLAND
ARM
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Cambridge CB1 4JN
UK
Telephone: [phone]
Facsimile: [phone]
Email: [email protected]
GERMANY
ARM
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Telephone: [phone]
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Email: inf[email protected]
JAPAN
ARM
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Telephone: [phone]
Facsimile: [phone]
Email: [email protected]
USA
ARM
Suite 5
985 University Avenue
Los Gatos
CA 95030 USA
Telephone: [phone]
Facsimile: [phone]
Email: inf[email protected]
World Wide Web address: http://www.arm.com
ARM Development Board
ARM7TDMI Version
Hardware Reference Guide
Document number: ARM DUI 0017C
Issued: March 1997
Copyright ARM Limited 1997
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ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
ii
Beta Draft
Proprietary Notice
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars
of the product and its use contained in this document are given by ARM in good faith. However, all
warranties implied or expressed, including but not limited to implied warranties or merchantability, or fitness for
purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM Ltd shall not be liable for any
loss or damage arising from the use of any information in this document, or any error or omission in such
information, or any incorrect use of the product.
Trademarks
ARM, and the ARM Powered logo are registered trademarks of ARM Ltd.
EmbeddedICE is a trademark of ARM Limited.
Windows 95 is a registered trademark of Microsoft Corporation.
Windows NT is a trademark of Microsoft Corporation.
Key
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This document has a number which identifies it uniquely. It is displayed on every page.
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This describes the document’s confidentiality and information status, and is shown at the bottom of each page.
Confidentiality status is one of:
ARM Confidential Distributable to ARM staff and NDA signatories only
Named Partner Confidential Distributable to the above and to the staff of named partner companies only
Partner Confidential Distributable within ARM and to staff of all partner companies
Open Access No restriction on distribution
Information status is one of:
Advance Information on a potential product
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Change Log
Issue Date By Change
ARM
XXX 0000 X - 00
Two-digit draft number (on review drafts only)
Release code in the range A-Z
Unique four-digit number
Document typeL
A June 96 KTB Created
B Nov 96 LG Updated
C March 97 BJH Updated to reflect creation
of TDS User Guide
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iii
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
1 Introduction 1-1
1.1 Using this Manual 1-2
1.2 Conventions 1-2
1.3 Useful Contacts 1-3
1.4 Glossary 1-4
2 Board Overview 2-1
2.1 Overview of the ARM Development Board 2-2
2.2 An Overview of the Board 2-3
3 Circuit Descriptions 3-1
3.1 Overview of Schematics 3-2
3.2 ARM Development Board 3-4
3.3 ARM7TDMI Processor Daughter Board 3-26
4 Expanding and Monitoring the ASB 4-1
4.1 Expanding the ASB 4-2
4.2 Building an ASB Master Expansion Board 4-6
4.3 Building an ASB Slave Expansion Board 4-7
4.4 ASB Timing on the ARM Development Board 4-8
Contents
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Contents
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iv ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
5 Expanding and Monitoring the APB 5-1
5.1 APB Expansion Interface 5-2
5.2 Building an APB Slave Expansion Board 5-5
5.3 APB Timing on the ARM Development Board 5-6
6 The EmbeddedICE Interface 6-1
6.1 EmbeddedICE Interface 6-2
7 The Logic Analyser Interface 7-1
7.1 ARM HP Inverse Assembler 7-2
8 The Test Interface 8-1
8.1 Introducing the Test Interface 8-2
8.2 Connecting External Equipment to the Test Bus 8-3
8.3 Test Interface Interconnections 8-4
9 Programming the APB FPGA 9-1
9.1 Introduction 9-2
9.2 Interrupt Controller 9-3
9.3 Using the APB FPGA in Your Own Designs 9-4
10 Programming the MACH and PAL Devices 10-1
10.1 Reprogramming a Device 10-2
A Board Schematics A-1
A.1 Card Outline Drawing A-2
A.2 Top-level Diagram A-3
A.3 Power Supply A-4
A.4 Crystal Oscillator and Clock Distribution A-5
A.5 ASB Slaves A-6
A.6 “On-chip” Memory (Synchronous SRAM) A-7
A.7 EPROM/FLASH ASB Slave A-8
A.8 DRAM ASB Slave A-9
A.9 SRAM ASB Slave A-10
A.10 APB and NISA Bridge A-11
A.11 NISA Bus Peripherals A-12
A.12 Serial and Parallel Ports A-13
A.13 PC Card Interface A-14
A.14 PC Card Connecters and Power Supply A-15
A.15 APB Slaves A-16
A.16 APB Expansion Connecters A-17
A.17 APB Buffers A-18
A.18 Memory Address and Data Buffers A-19
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A.19 Test Interface Controller and Connecters A-20
A.20 Master Header Connecters and Level Converters A-21
A.21 System Modules (Arbiter and Decoder) A-22
A.22 ASB Expansion Connecters A-23
B Daughter Board Schematics B-1
B.1 Card Outline Drawing B-2
B.2 Top-level Diagram B-3
B.3 Header Connecters B-4
B.4 Logic Analyser Connecters B-5
B.5 AMBA Bus Master Veneer B-6
B.6 Processor in QFP Package B-7
B.7 Processor in PGA Package B-8
B.8 EmbeddedICE Interface B-9
C Summary of Programmable Devices C-1
C.1 Programmable Devices C-2
D Summary of Jumpers and Links D-1
D.1 Overview D-2
D.2 Surface Mount Links D-2
D.3 Standard 2-pin Links D-3
D.4 Link Fields D-4
D.5 DIP Switches D-5
E Mechanical Information E-1
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1-1
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
This manual provides hardware reference information on the ARM Development Board.
For information on connecting the board to a host computer and using the software
developmenttools,pleaserefertothecompanionmanual
TargetDevelopmentSystemUser
Guide (ARM DUI 0061)
.
1.1 Using this Manual 1-2
1.2 Conventions 1-2
1.3 Useful Contacts 1-3
1.4 Glossary 1-4
Introduction
1
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Introduction
1-2 ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
1.1 Using this Manual
Chapter 1 is this introduction
Chapter 2 introduces the ARM Development Card
Chapter 3 describes the circuits of the ARM Development Card
Chapter 4 describes how to expand the ASB
Chapter 5 describes how to expand the APB
Chapter 6 describes the EmbeddedICE interface
Chapter 7 describes the logic analyser interface
Chapter 8 describes the test interface
Chapter 9 describes how to program the APB FPGA
Chapter 10 describes how to program the MACH and PAL devices
Appendix A provides detailed circuit schematics of the board
Appendix B provides detailed circuit schematics of the daughter board
Appendix C is an index of the programmable devices
Appendix D is a summary of the switches, jumpers and links
Appendix E is a mechanical drawing of the ARM Development Card
1.1.1 Related Documentation
You may find it useful to refer to the following documents:
ARM IHI-0001 AMBA Specification
ARM DUI 0014 HP ARM Inverse Assembler User Guide
ARM DDI-0041 AMBA Arbiter
ARM DDI-0042 AMBA Decoder
ARM DDI-0043 AMBA Test Interface Controller
ARM DDI-0047 AMBA Interrupt Controller
ARM DDI-0048 AMBA Reset and Pause
ARM DDI-0049 AMBA Timer APB Peripheral
ARM DDI-0051 AMBA Reset Controller
ARM DUI 0061 Target Development System user Guide
ARM DDI 0062 Reference Peripherals Specification
1.2 Conventions
This manual employs typographic conventions intended to improve its ease of use.
code code which you need to enter, or which is provided as an example
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ARM DUI 0017C
1.3 Useful Contacts
1.3.1 Contacting ARM
Further information is available from ARM.
All schematics (ORCAD), PLD and VHDL binary files and latest release notes are available
from our world wide web servers at:
http://www.arm.com
If you require PDL descriptions or have difficulty accessing our web page, please email:
[email protected]
1.3.2 Component data sheets
Contact points for component data sheets are as follows:
XR16C552 Exar (Startech) serial and parallel port chip
UK distributor:
Farnell Electronic Components Ltd. Tel: [phone]
http://www.exar.com
MACH and PALCE AMD programmable logic devices
UK distributors:
Kudos Thame Ltd. Tel: [phone]
Avnet Access Ltd. Tel: [phone]
http://www.amd.com
XC4005 Xilinx FPGA
UK distributor:
Microcall Ltd. Tel: [phone]
Avnet Access Ltd. Tel: [phone]
http://www.xilinx.com
VG-468 Vadem PC card controller
UK distributor:
MMD Tel: [phone]
http://www.vadem.com
1.3.3 Information on chips
A useful site for chip information is:
http://www.xs4all.nl/~ganswijk/chipdir
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Introduction
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1.4 Glossary Some of the terms used in this manual may be unfamiliar to you. This section explains some
of the more important ones.
ARM7TDMI The ARM7TDMI test chip is an example of an ARM processor
macrocellthatissuitableforuseon theARMDevelopmentCard.
See the
ARM7TDMI Data Sheet (ARM DDI 0029) for more
information.
CPLD A
complex programmable logic device ( CPLD ) is usually
a collection of PAL-type devices in a single package.
The AMD MACH device is an example of a CPLD.
EmbeddedICE This is the additional hardware that is provided by debuggable
ARM processors to aid debugging. The EmbeddedICE
macrocell is fully described in the
ARM7TDMI Data Sheet (ARM
DDI 0029). The EmbeddedICE macrocell is controlled via the
JTAGtest access port, using an EmbeddedICE interface. This is
an extra piece of hardware that allows software tools to debug
code running on a target processor.
FPGA A
field-programmable gate array ( FPGA ) is a type of
programmable logic device ( PLD ). The ARM Development Card
is fittedwith one FPGA manufactured byXilinx. You can change
the functionality of thisdevice if the appropriate design tools are
available. Xilinx sells an appropriate tool set which interfaces to
a variety of front-end systems which may be based on
schematics or hardware description languages such as VHDL.
See also
LCA .
ICE An in-circuit emulator ( ICE ), is a device that aids debugging of
hardware and software. ARM debuggable processors such as
the ARM7TDMI have extra hardware called
EmbeddedICE to
assist this process.
JTAG This is a serial-like test port provided on many large silicon chips
such as the ARM7TDMI.
LCA A
logic cell array ( LCA ) is a type of programmable logic device
(
PLD ) also known as a field-programmable gate array ( FPGA ).
MACH A MACH device is a example of a complex programmable logic
device
( CPLD ). The ARM Development Card uses a number of
MACH210 and MACH230 devices. Based on electrically
erasable (
EE ) technology, they are reprogrammable. Using
appropriate software (such as PALASM), the function of these
devices may be changed by reprogramming in a standard
programmer.
NISA
NISA ( not-ISA ) is ARM’s descriptionof the bus thatconnects the
Advanced System Bus ( ASB ) to some standard peripheral
devices such as the serial/parallel ports and PC card controller.
It is a subset of the
Industry Standard Architecture ( ISA ) bus
found in most IBM compatible PCs.
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ARM DUI 0017C
PAL A programmable array logic ( PAL ) device is a example of
a
programmable logic device ( PLD ). The PAL used on the ARM
Development Card is a PALCE22V10. This has up to 22 inputs,
ten outputs and ten programmable macrocells. As it is based on
electrically erasable (EE) technology, it is reprogrammable.
Using appropriate software (such as PALASM), the function of
this device may be changed by reprogramming in a standard
programmer.
PCMCIA The
Personal Computer Memory Card Association ( PCMCIA )
produces a specification that details an interface suitable for
connecting small boards (the size of credit cards) to larger host
systems.ThenamePCMCIAis generallyusedtodescribethese
cards, but its use has been superseded by the term PC card.
PLD A
programmable logic device . See also PAL and FPGA.
PALASM A
programmable array logic assembler ( PALASM ) is a low-cost,
proprietary logic description language produced by Advanced
Micro Devices
( AMD ) for their range of PLDs and CPLDs. It has
been used extensively in the design of the ARM Development
Card.
PLL A
phase-locked loop ( PLL ) usually comprises a voltage
controller oscillator, programmable divider, frequency
comparator, and an integrator. These components allow a
programmable frequency clock to be generated. This is locked
to and stabilised by a reference clock input.
On the ARM Development Card, a single component performs
this function. A reference crystal at 14.318MHz isused, and with
three programmable inputs, the device is able to generate 8
output frequencies from about 4–50MHz.
VHDL VHDL is a hardware description language suitable for the
simulation and synthesis of logic circuits. The design for the
FPGA on the ARM Development Card was completed using
VHDL andsynthesis toolsfrom Compass. Xilinx toolswere used
to place and route the design.
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2-1
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This chapter describes each of the main blocks of the ARM Development Board.
2.1 Overview of the ARM Development Board 2-2
2.2 An Overview of the Board 2-3
Board Overview
2
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Board Overview
2-2 ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
2.1 Overview of the ARM Development Board
The ARM Development Board is a platform that is suitable for code development and
exploration of embedded ARM processors. It is a convenient means of evaluating the
Advanced RISC Machines’ Thumb-aware (ARM7T) family of RISC processors.
The ARM Development Board has been designed to conform to the
Advanced
Microcontroller Bus Architecture
( AMBA ) specification. This specification defines an on-chip
communications standard for designing high performance 32- and 16-bit embedded
microcontrollers. A convenient way to view the ARM Development Board is as a
microcontroller design in discrete components.This means that it is possible to observe bus
transactions and peripheral accesses using standard test equipment. Thus, a typical
microcontroller design can be easily observed and prototyped.
Because the processor in the system is little more than ARM core it is possible to use an in-
circuit emulator (ICE). This enables a system design to be tested and debugged at the
processor level. In addition processors with EmbeddedICE capabilities can be debugged
directly using the EmbeddedICE interface. The ARM Development Board also has a parallel
port and two serial ports that allow it to be connected to a variety of hosts. Using a monitor
program supplied with the board, the user can download and run code in collaboration with
the ARM Software Development Toolkit.
The ARM Development Board shows how to design a system based on the AMBA
specification, comprising a multi-master system bus (ASB) and a low-power peripheral bus
(APB). While on-chip techniquesmay differ, themain system modules and their interconnect
have been preserved.
The following are useful reference documents. You should refer to these to understand the
functionality of AMBA modules.
• AMBA Specification(ARM IHI 0001)
• Reference Peripherals Specification(ARM DDI 0062)
2.1.1 Using ARM resources in your design
This manual contains boththe circuitdescription(and schematics) of the ARM Development
Board and a description of programmable logic devices used.
The programmable logic equations and schematics can be obtained from ARM for use in
your own designs. These are provided to help you design your prototype target hardware
systems.
Bothhardwareandsoftwareareprovidedastutorialaidsanddemonstratetechniquesrather
than an optimal implementation. Please feel free to use the schematics and programmable
logic equations provided as a basis for your own system designs.
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Board Overview
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2.2 An Overview of the Board
A typical AMBA system comprises a processor connected to an Advanced System Bus
(
ASB ) with a bridge to the slower, low-power Advanced Peripheral Bus ( APB ). The main
system blocks are shown in
Figure 2-1: Overview of the ARM Development Board on
page 2-4:
• AMBA bus master comprising an ARM processor and PLD
• AMBA system modules, arbiter and decoder
• On-chip (synchronous SRAM) memory
•SRAMblock
• EPROM or FLASH block
• DRAM block
• Test interface
• APB bridge
• APB slaves, timer, interrupt controller
• ASB expansion connectors
• APB expansion connectors
• NISA bus bridge
• PC card (PCMCIA) block
• Serial and parallel port block
2.2.1 Board architecture
A convenient way to view the ARM Development Board is as a sample microcontroller with
its support peripherals constructedfrom discrete devices. The bus master, system modules,
APB bridge and peripherals, on-chip RAM and external bus interfaces form the heart of a
microcontroller. Additional peripherals such as PC card (PCMCIA) and serial and parallel
ports may also be incorporated or interfaced to externally.
Each functional block is constructed from separate programmable logic devices (PLDs).
This enables you to observe the system interactions using standard test equipment such as
a logic analyser. The expansion connectors provide a way of interfacing additional circuitry
to the ARM Development Board and also provide convenient hook-up points for a logic
analyser.
Refer to
Chapter 4, Expanding and Monitoring the ASB and Chapter 5, Expanding and
Monitoring the APB
for further information.
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Board Overview
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ARM DUI 0017C
Memory types
A typical system might provide some of the following memory types:
•SRAM
• EPROM
• FLASH
• DRAM
Examples of all of these can be found on the board.
Each memory type has its own controller. An ideal system might have a single external bus
interface (EBI). In this implementation the EBI is distributed into separate memory
controllers.
Figure 2-1: Overview of the ARM Development Board
External Bus I/F
ASB
Expansion
AMBA Bus Master
ARM
PLD
Arbiter
Decoder
“On-chip”
SRAM
32K x 32
ROM SRAM DRAM I/O
Test
I/F
3V-5V Level Shift
APB
Bridge
Timer
Interrupt
Controller
APB
Expansion
512K
x 8 128K x 32 0-8 M
SIMM
PCMCIA
Parallel +
Serial Port
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3-1
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
This chapter describes the circuits of the ARM Development Board.
3.1 Overview of Schematics 3-2
3.2 ARM Development Board 3-4
3.3 ARM7TDMI Processor Daughter Board 3-26
Circuit Descriptions
3
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Circuit Descriptions
3-2 ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
3.1 Overview of Schematics
The board has been designed to allow an AMBA bus master (such as an ARM7TDMI test
chip) to be mounted on daughter board. The daughter board is an integral part of the ARM
Development Board, although the daughter board supplied could be replaced with another
AMBA master, such as an in-circuit emulator.
3.1.1 Master board circuits
The master board design comprises 22 schematics as listed below.
1 Board outline drawing DRAWING.SCH
2 Top-level diagram CHAMP.SCH
3 Power supply POWER.SCH
4 Crystal oscillator and clock distribution OSC.SCH
5 ASB slaves ASBSLAVE.SCH
6“On-chip” memory (synchronous SRAM) ONCHIP.SCH
7 EPROM/FLASH ASB slave EPROM.SCH
8 DRAM ASB slave DRAM.SCH
9 SRAM ASB slave SRAM.SCH
10 APB and NISA bridge ASBNISA.SCH
11 NISA bus peripherals NISABUS.SCH
12 Serial and parallel ports SUPERIO.SCH
13 PC card interface PCMCIA.SCH
14 PC card connectors and power supply CARDCON.SCH
15 APB slaves APBSLAVE.SCH
16 APB expansion connectors APBEXP.SCH
17 APB buffers APBBUF.SCH
18 Memory address and data buffers MEMBUF.SCH
19 Test interface controller and connectors TIC.SCH
20 Master header connectors and level convertors MASTER.SCH
21 System modules (arbiter and decoder) SYSMODS.SCH
22 ASB expansion connector ASBEXP.SCH
3.1.2 Configuring the board
The board is configurable through the use of links, jumpers and switches. Each of these is
described in detail in the following subsections. In addition, there is a summary of links and
switches in Appendix D, Summary of Jumpers and Links . Also, the Target Development
System User Guide (ARM DUI 0061)
contains information on configuring the ARM
Development Board.
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Circuit Descriptions
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3.1.3 Daughter board circuits
The daughter board schematics for the supplied system are included in Appendix B,
Daughter Board Schematics
.
Thedaughterboard(orheader)isconnectedtotheARMDevelopmentBoard byfour60-way
connectors.Thisallowsdifferentbusmasterstobeconnected,includingin-circuitemulators.
The design comprises seven schematics as listed below.
Note
There are two versions of the processor schematic depending upon whether you have
a QFP or PGA packaged part on the board.
1 Board outline drawing DRAWING.SCH
2 Top-level diagram CHAMPQFP.SCH
3 Header connectors CPUHEAD.SCH
4 Logic analyser connectors LAPODS.SCH
5 AMBA bus master veneer AMBAPLD.SCH
6 Processor in QFP package PROCQFP.SCH
7 Processor in PGA package PROCPGA.SCH
8 EmbeddedICE interface EICE.SCH
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ARM DUI 0017C
3.2 ARM Development Board
The top-level schematic is illustrated in A.1 Card Outline Drawing on page A-2, and shows
the main blocks of the design. The blocks are interconnected by the ASB signals prefixed
B_, such as B_A[31:0], B_D[31:0] and B_WAIT. There are two ASB bus masters, the ARM
chip mounted on a header card and the test interface controller (TIC).
The ASB system modules (the system arbiter and decoder) can also be seen.
There isa block called ASB expansionwhich details thephysical connectors. Thisallows the
ASB to be monitored by a logic analyser, or allows external circuitry to be attached
The oscillator block describes the system clock generation and distribution, and the power
supply block describes the power input and regulation.
There are a number of ASB slaves which are described in
3.2.3 ASB Slaves on page 3-7.
3.2.1 Power Supply
This schematic is shown in A.3 Power Supply on page A-4.
Two green LEDs marked (5V) and (3V3) light up when power is connected to the board.
Note
Take care when connecting up power to this board as there is no protection for incorrectly
wired supplies. If the LEDs fail to light, switch off immediately and check the connections.
The board is designed to function at 5V so that high-speed programmable logic devices can
be used. The ARM processor is a 3.3V component and so needs to be protected from high
logic levels. This is accomplished through use of level-convertor ICs. A 3.3V supply is
generated on board from a 5V supply for use by the ARM processor and the synchronous
SRAM (a 3.3V part with 5V tolerant I/O).
Power to the board is supplied through a PC-style 12-way connector. This allows a PC power
supply to be connected directly, and this will provide all the requirements of the board. The
board consumes 2–5A at 5V depending upon the amount of DRAM fitted and the clock
frequency used. If preferred a bench power supply can be used instead.
Note
Some PC power supplies can trip out if very low current is taken, so you can insert a load
acrossthe +12Vsupplyhas beenmade. If thisis a requirement, connect aresistanceacross
the pads marked (JP2).
The connector (J1) contacts are rated at 2A, so if current consumption is low, it is only
necessary to connect to pin 2 (+5V) and pin 5 (GND). Pin 3 (+12V) need only be connected
if the PC card (PCMCIA) interface is to be used.
An LM317 voltage regulator (U1) is used to generate the 3.3V supply required by the ARM
processor. You can decouple this from the regulator by removing a wire link (JP1) if required.
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