Fujitsu MB96300 series User manual

FUJITSU SEMICONDUCTOR
PRELIMINARY
CONTROLLER MANUAL
F2MC-16FX
16-BIT MICROCONTROLLER
MB96300 Super series
HARDWARE MANUAL
FME-MB96300rev14,
2007-12-18

FUJITSU LIMITED
PRELIMINARY
F2MC-16FX
16-BIT MICROCONTROLLER
MB96300 Super series
HARDWARE MANUAL

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MB96300 Super Series Hardware Manual
PRELIMINARY
PREFACE
■Objectives and intended reader
Thank you very much for your continued patronage of Fujitsu semiconductor products.
The MB96300 Super series has been developed as a general-purpose version of the F2MC-16FX
series, which is an original 16-bit single-chip microcontroller compatible with the Application
Specific IC (ASIC).
This manual explains the functions and operation of the MB96300 Super series for designers who
actually use the MB96300 Super series to design products. Please read this manual first.
■Trademark
F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
Other system and product names in this manual are trademarks of respective companies or
organizations.
The symbols ™ and ® are sometimes omitted in this manual.
■Structure of this manual
CHAPTER 1 "OVERVIEW"
The MB96300 Super series is a family member of the F2MC-16FX micro controllers. It consist of
many different series of microcontrollers, which are targetting different applications.
Programming between all members of the Super series is common.
CHAPTER 2 "CPU"
This chapter explains the CPU.
CHAPTER 3 "INTERRUPTS"
This chapter explains the interrupt functions and operations.
CHAPTER 4 "DMA"
This chapter explains the DMA functions and operations.
CHAPTER 5 "DELAYED INTERRUPT"
This chapter explains the functions and operations of the delayed interrupt.
CHAPTER 6 "CLOCKS"
This chapter describes the clocks used by F2MC-16FX family micro controllers.
CHAPTER 7 "CLOCK MODULATOR"
ThischapterprovidesanoverviewoftheClockModulatoranditsfeatures.Itdescribestheregister
structure and operation of the Clock Modulator. The clock modulator is currently being
evaluated and should not be used for other purpose than testing.
CHAPTER 8 "RESETS AND STARTUP"
This chapter describes the resets and the startup of for the F2MC-16FX family microcontrollers.

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MB96300 Super Series Hardware Manual
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CHAPTER 9 "STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT"
This chapter explains the functions and operations of the standby mode control circuit and the
control of the internal voltage regulator. The regulator control can be used to optimize
power consumption, especially in standby modes.
CHAPTER 10 "SOURCE CLOCK TIMERS"
This chapter explains the functions and operations of the three source clock timers (RC clock
timer, Main clock timer and Sub clock timer).
CHAPTER 11 "WATCHDOG TIMER AND WATCHDOG RESET"
This chapter explains the functions and operations of the Watchdog timer and reset.
CHAPTER 12 "EXTERNAL BUS INTERFACE"
This chapter explains the functions and operations of the external bus interface.
CHAPTER 13 "I/O PORTS"
This chapter explains the functions and operations of the I/O ports.
CHAPTER 14 "16-BIT I/O TIMER"
This chapter explains the functions and operations of the 16-bit I/O Timer.
CHAPTER 15 "16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)"
This chapter explains the functions and operations of the 16-bit Reload Timer (with the Event
Count Function).
CHAPTER 16 "PROGRAMMABLE PULSE GENERATOR"
This chapter explains the functions and operations of the Programmable Pulse Generator.
CHAPTER 17 "EXTERNAL INTERRUPTS"
This chapter explains the functions and operations of the External Interrupts.
CHAPTER 18 "A/D CONVERTER"
This chapter explains the function and operation of the A/D converter.
CHAPTER 19 "ALARM COMPARATOR"
This chapter explains the functions and operations of the Alarm Comparator.
CHAPTER 20 "USART"
This chapter explains the functions and operation of the LIN USART.
CHAPTER 21 "400 kHz I2C INTERFACE"
This section describes the functions and operation of the fast I2C interface.
CHAPTER 22 "CAN CONTROLLER"
This chapter explains the functions and operations of the CAN controller.
CHAPTER 23 "CLOCK OUTPUT FUNCTION"
This chapter describes the functions and operations of the clock output function.
CHAPTER 24 "REAL TIME CLOCK"
This chapter explains the functions and operations of the Real Time Clock.

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MB96300 Super Series Hardware Manual
PRELIMINARY
CHAPTER 25 "CLOCK CALIBRATION UNIT"
This chapter explains the functions and operation of the Clock Calibration Unit
CHAPTER 26 "LCD CONTROLLER/DRIVER"
This chapter describes the functions and operations of the LCD Controller/Driver.
CHAPTER 27 "STEPPER MOTOR CONTROLLER"
This chapter explains the functions and operations of the stepper motor controller.
CHAPTER 28 "SOUND GENERATOR"
This chapter explains the functions and operations of the sound generator.
CHAPTER 29 "USB FUNCTION"
This chapter describes the functions and operations of the USB Function.
CHAPTER 30 "USB Mini-host"
This chapter describes the functions and operations of USB Mini-host.
CHAPTER 31 "MEMORY PATCH FUNCTION"
This chapter explains the memory patch function and how the data patch or a debug function can
be realised with that.
CHAPTER 32 "ROM/RAM MIRRORING MODULE"
This chapter explains the ROM mirroring module.
CHAPTER 33 "FLASH MEMORY"
This chapter explains the functions and operation of the flash memory.
CHAPTER 34 "MASK-ROM MEMORY INTERFACE"
This chapter explains the functions and operation of the rom memory interface.
CHAPTER 35 "ROM/FLASH SECURITY"
This chapter explains the functions and operation of the ROM/Flash security.
CHAPTER 36 "EXAMPLES OF SERIAL PROGRAMMING CONNECTION"
This chapter describes how to connect the MCU for in-circuit serial programming of the Flash
memory.

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MB96300 Super Series Hardware Manual
PRELIMINARY
©2007 FUJITSU LIMITED Printed in Japan
• The contents of this document are subject to change without notice. Customers are advised to consult
with FUJITSU sales representatives before ordering.
• The information and circuit diagrams in this document are presented as examples of semiconductor
device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is
unable to assume responsibility for infringement of any patent rights or other rights of third parties arising
from the use of this information or circuit diagrams.
• The products described in this document are designed, developed and manufactured as contemplated
for general use, including without limitation, ordinary industrial use, general office use, personal use, and
household use, but are not designed, developed and manufactured as contemplated (1) for use
accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious
effect to the public, and could lead directly to death, personal injury, severe physical damage or other
loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass
transport control, medical life support system, missile launch control in weapon system), or (2) for use
requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages
arising in connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage
or loss from such failures by incorporating safety design measures into your facility and equipment such
as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
• If any products described in this document represent goods or technologies subject to certain restrictions
on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by
Japanese government will be required for export of those products from Japan.

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MB96300 Super Series Hardware Manual
PRELIMINARY
CONTENTS
OVERVIEW 7
Features 8
Super series lineup 10
Block Diagram of MB96V300 12
General note on using this document 16
16-bit I/O-Timer Configuration 19
Input Capture Unit source select for LIN-USART 23
Peripheral resource pin relocation 30
CPU 47
Outline of the CPU 48
Hardware Structure 50
Memory Space 54
Special Registers 63
General-Purpose Registers 76
Prefix Codes 80
INTERRUPTS 89
Outline of Interrupts 90
Interrupt Vector 92
Interrupt Control Registers (ICR) 95
Non Maskable Interrupt (NMI) 97
Interrupt Flow 99
Hardware Interrupts 101
Software Interrupts 104
Multiple interrupts 106
Exceptions 110
DMA 115
Overview 116
DMA Registers 119
DMA Descriptor 125
DMA Controller Operation 133
Examples of DMA transfers 136
DELAYED INTERRUPT 139
Outline of Delayed Interrupt Module 140
Delayed Interrupt Register 141
Delayed Interrupt Operation 142
CLOCKS 143
Clocks 144

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MB96300 Super Series Hardware Manual
PRELIMINARY
Clock Control Registers 148
Clock Modes 169
Configuration of the PLL 172
Oscillation Stabilization Wait Time 175
Connection of an Oscillator or an External Clock to the Microcontroller 177
CLOCK MODULATOR 179
Overview 180
Register Description 181
Application Note 188
RESETS AND STARTUP 191
Resets 192
Reset, System clock and Stabilization Wait Times 195
Startup after Power and External reset 197
Boot ROM program execution and Operation mode and ROM Configuration Block 200
Reset Control Registers 208
Operation of the Clock stop detection function and reset 220
Operation of the low voltage reset function 224
STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT 227
Overview of the CPU Operating Modes 228
Standby Mode Control Register (SMCR) 234
Voltage Regulator Control Register (VRCR) 237
Standby Modes 240
Mode Change Table and operation status 251
Usage Notes on Standby Mode 253
Voltage Regulator Operation 255
SOURCE CLOCK TIMERS 261
Overview 262
RC Clock Timer 263
Main Clock Timer 268
Sub Clock Timer 273
WATCHDOG TIMER AND WATCHDOG RESET 279
Outline of Watchdog Timer and Reset 280
Watchdog Timer Control Registers 281
Watchdog Timer Operation 287
EXTERNAL BUS INTERFACE 291
Outline of External Bus 292
External bus configuration registers 298
External Memory Access Control Signal Operation 322
Notes on using the external bus 340
External Boot Vector fetch 344
Pin status in different MCU states 346

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MB96300 Super Series Hardware Manual
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I/O PORTS 349
I/O Ports 350
I/O Port Registers 351
Register usage 362
16-BIT I/O TIMER 363
Outline of 16-bit I/O Timer 364
16-Bit I/O Timer Registers 366
16-bit Free-Running Timer 368
Output Compare Unit 375
Input Capture Unit 388
16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 395
Outline of 16-Bit Reload Timer (with Event Count Function) 396
16-Bit Reload Timer (with Event Count Function) 398
Internal Clock and External Event Counter Operations of 16-bit Reload Timer 403
Underflow Operation of 16-bit Reload Timer 405
Output Pin Functions of 16-bit Reload Timer 406
Counter Operation State 407
Cascading of 16-bit Reload Timers 408
PROGRAMMABLE PULSE GENERATOR 411
Outline of Programmable Pulse Generator 412
Registers 415
Operation of Programmable Pulse Generator 422
Cautions 425
EXTERNAL INTERRUPTS 427
Outline of External Interrupts 428
External Interrupt Registers 430
Notes on using the External Interrupt functions 432
A/D CONVERTER 433
Outline of A/D Converter 434
Registers for A/D Converter 436
Operation of A/D Converter 452
Conversion using DMA 453
Conversion Data Protection Function 454
ALARM COMPARATOR 457
Outline of Alarm Comparator 458
Alarm Comparator Registers 460
Alarm Comparator operating modes 463
USART 465
Overview of USART 466

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MB96300 Super Series Hardware Manual
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Configuration of USART 469
USART Pins 474
USART Registers 475
USART Interrupts 496
USART Baud Rates 503
Operation of USART 511
Notes on Using USART 535
400 kHz I2C INTERFACE 541
I2C Interface Overview 542
I2C Interface Registers 544
I2C Interface Operation 567
Programming Flow Charts 570
CAN CONTROLLER 573
Overview 574
Functional Description 575
Register Description 579
CAN Device Related Registers 584
CAN Protocol Related Registers 586
Message Interface Register Sets 597
Message Object in the Message Memory 607
Message Handler Registers 611
CAN Application 620
CLOCK OUTPUT FUNCTION 629
Overview of the Clock Output Function 630
Clock Output Configuration and Activation Registers 631
Operation of the Clock Output Function 637
REAL TIME CLOCK 639
Outline of Real Time Clock 640
Real Time Clock Registers 642
Operation 651
Cautions 654
CLOCK CALIBRATION UNIT 657
Outline 658
Register Description 661
Application Notes 665
LCD CONTROLLER/DRIVER 667
Configuration of LCD Controller/Driver 668
LCD Controller Registers 674
LCD Enable Registers (LCDER, LCDVER) 678
LCD Controller/Driver Display RAM 681
Operation of LCD Controller/Driver 682

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MB96300 Super Series Hardware Manual
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Cautions 688
STEPPER MOTOR CONTROLLER 691
Outline of Stepper Motor Controller 692
Stepper Motor Controller Registers 693
PWM Control register (PWCn) 695
PWM Extended Control register (PWECn) 697
PWM1 and PWM2 Compare Registers (PWC1n, PWC2n) 698
PWM1 and PWM2 Selection registers (PWS1n, PWS2n) 701
Operation of Stepper Motor Controller 703
Notes on Using Stepper Motor Controller 706
SOUND GENERATOR 707
Outline of Sound Generator 708
Sound Generator Registers 709
USB FUNCTION 719
USB Function Overview 720
USB Function Block Diagram 721
USB Function Registers Description 722
USB Function Operation 753
USB Mini-host 767
USB Mini-host features 768
Differences with USB host 769
USB Mini-host Block Diagram 770
USB Mini-host Registers 771
USB Mini-host operation 795
Token Flow Chart 812
MEMORY PATCH FUNCTION 815
Outline of the Memory Patch Function 816
Registers of the Memory Patch Function 818
Operation of the Memory Patch Function 829
ROM/RAM MIRRORING MODULE 831
Outline of ROM Mirroring Module 832
ROM Mirroring Register (ROMM) 833
FLASH MEMORY 837
Overview of the Flash Memory 838
Block Diagram of the Flash Memory and Sector Configuration of the Flash Memory 840
Write/Erase Modes 843
Flash Memory Control Registers 844
Starting the Flash Memory Automatic Algorithm 858
Confirming the Automatic Algorithm Execution State 860
Detailed Explanation of Writing to and Erasing Flash Memory 870

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MB96300 Super Series Hardware Manual
PRELIMINARY
Notes on using Flash Memory 881
Flash memory programming example 882
MASK-ROM MEMORY INTERFACE 889
Overview 890
ROM interface registers 891
Read buffers 896
ROM/FLASH SECURITY 897
Overview of the ROM/Flash Security 898
Usage of the ROM/Flash Security 899
EXAMPLES OF SERIAL PROGRAMMING CONNECTION 903
Basic Configuration of Serial Programming Connection 904
Example of connecting a PC for programming the Flash Microcontroller 907
Example of connecting a programming tool for programming the Flash Microcontroller 908

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PRELIMINARY
CHAPTER 1
OVERVIEW
The MB96300 Super series is a family member of the
F2MC-16FX micro controllers. It consist of many different
series of microcontrollers, which are targetting different
applications. Programming between all members of the
Super series is common.
1.1 "Features"
1.2 "Super series lineup"
1.3 "Block Diagram of MB96V300"
1.4 "General note on using this document"
1.5 "16-bit I/O-Timer Configuration"
1.6 "Input Capture Unit source select for LIN-USART"
1.7 "Peripheral resource pin relocation"

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CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual
PRELIMINARY
1.1 Features
The feature set of F2MC-16FX family’s MB96300 Super series makes it especially well
suited for automotive applications.

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MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW
PRELIMINARY
■Features • 16-bit core CPU, 64 MHz internal, 15.6 ns instruction cycle time
• 0.18µm CMOS Process Technology
• Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23
different addressing modes; barrel shift; variety of pointers)
• 8-byte instruction execution queue
• Signed multiply (16 bit ×16 bit) and divide (32 bit/16 bit) instructions available
• Internal voltage regulator supports reduced internal MCU voltage, offering low EMI and low power
consumption figures
• Code Security Feature
• Up to 5 FULL-CAN interfaces; conforming to Version 2.0 Part A and Part B, ISO16845 certified
• Powerful interrupt functions (8 progr. priority levels; up to 16 external interrupts)
• Fast Interrupt processing
• Up to 16 channels DMA - Automatic transfer function independent of CPU, can be assigned freely to
resources
• Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer)
• Watchdog Timer
• Up to 10 channels full duplex USARTs (SCI/LIN)
• Up to 2 channels I2C with 400 kbit/s
• Up to 40 channels analog inputs for A/D Converter (Resolution 10 bits or 8 bits)
• Up to 6 channels16-bit reload timer
• Up to 12 channels ICU (Input capture unit) 16 bit
• Up to 12 channels OCU (Output compare unit) 16 bit
• Up to 4 channels 16-bit free running timer
• Up to 20 channels ×16-bit Programmable Pulse Generator
• Up to 6 channels Stepper Motor Controller with integrated high current output drivers
• LCD controller with up to 4 COM ×72 SEG, internal or external voltage generation
• Memory Patch Function, can also be used to implement embedded debug support
• Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes, Stop mode)
• 3-32 MHz external clock, on-chip PLL with programmable multiplication factor 1 ... 16
• 32 kHz Subsystem Clock
• 100kHz/2MHz internal RC clock
• External bus interface with up to 6 Chip select signals, 8bit or 16bit data, 24bit address, multiplexed or
non-multiplexed, programmable timing
• Up to 2 channels Alarm comparators
• Programmable input levels (Automotive / CMOS-Schmitt trigger / TTL) for all ports
• Programmable Pull-up resistors for all ports
• Programmable output driving strength for EMI optimization
• Package : 48-pin / 64-pin / 80-pin / 100-pin / 120-pin / 144-pin plastic QFP and LQFP
• Controller Area Network (CAN) - License of Robert Bosch GmbH

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CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual
PRELIMINARY
1.2 Super series lineup
Table 1.2-1 "MB96300 super series lineup" provides an overview of the MB96300 Super
series.

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MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW
PRELIMINARY
■Super series lineup
The F2MC-16FX MB96300 Super series covers the F2MC-16FX series as shown in table 1.2-1.
Table 1.2-1 MB96300 super series lineup
Series Flash
Products Mask ROM Products Packages
MB96320 MB96F32x MB9632x FPT-80P-M21
MB96330 MB96F33x MB9633x FPT-144P-M08
FPT-144P-M12
MB96340 MB96F34x MB9634x FPT-100P-M20
FPT-100P-M22
MB96350 MB96F35x MB9635x FPT-64P-M23
FPT-64P-M24
MB96360 MB96F36x MB9636x FPT-48P-M26
MB96370 MB96F37x MB9637x FPT-144P-M08
FPT-144P-M12
MB96380 MB96F38x MB9638x FPT-120P-M21

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CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual
PRELIMINARY
1.3 Block Diagram of MB96V300
Figure 1.3-1 shows the block diagram of MB96V300.