Terasic MAX10-Plus User manual

MAX 10 Plus User
Manual
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May 31, 2019

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Manual
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May 31, 2019
CONTENTS
Chapter 1 MAX 10 Plus Development Kit..................................................................4
1.1 Package Contents........................................................................................................................4
1.2 MAX 10 Plus System CD...........................................................................................................5
1.3 Getting Help...............................................................................................................................5
Chapter 2 Introduction of the MAX 10 Plus...............................................................6
2.1 Layout and Components.............................................................................................................6
2.2 Block Diagram of the MAX 10 Plus..........................................................................................7
Chapter 3 Using the MAX 10 Plus.............................................................................10
3.1 Configuration of MAX 10 FPGAon MAX 10 Plus.................................................................10
3.2 Board Status Elements..............................................................................................................14
3.3 Clock Circuitry.........................................................................................................................15
3.4 Peripherals Connected to the FPGA.........................................................................................16
3.4.1 User Push-buttons, Switches, LEDs ......................................................................................16
3.4.2 7-segment Displays................................................................................................................19
3.4.3 Power Monitor.......................................................................................................................20
3.4.4 2x6 TMD Expansion Header .................................................................................................21
3.4.5 24-bit Audio CODEC ............................................................................................................22
3.4.6 Two Analog Input SMA Connectors .....................................................................................23
3.4.7 DDR3 Memory ......................................................................................................................23
3.4.8 QSPI Flash.............................................................................................................................25
3.4.9 Ethernet..................................................................................................................................26
3.4.10 HDMI RX..............................................................................................................................28
3.4.11 2x10 ADC Header .................................................................................................................29
3.4.12 Potentiometer.........................................................................................................................30
3.4.13 On-board Microphone............................................................................................................30
3.4.14 PS/2 Serial Port......................................................................................................................30

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3.4.15 Digital-to-Analog Converter (DAC)......................................................................................31
3.4.16 UART to USB........................................................................................................................32
3.4.17 Ambient Light Sensor............................................................................................................33
3.4.18 Humidity and Temperature Sensor ........................................................................................33
3.4.19 Accelerometer Sensor............................................................................................................34
3.4.20 Micro SD Card Socket...........................................................................................................35
3.4.21 Power Distribution System ....................................................................................................35
Chapter 4 The MAX 10 Plus System Builder ...........................................................37
4.1 Introduction..............................................................................................................................37
4.2 General Design Flow................................................................................................................37
4.3 Using MAX 10 Plus System Builder........................................................................................38
Chapter 5 RTL Example Codes .................................................................................44
5.1 PS/2 Mouse Demonstration......................................................................................................44
5.2 ADC Potentiometer ..................................................................................................................46
5.3 DAC Demonstration.................................................................................................................48
5.4 ADC/MIC/LED Demonstration................................................................................................51
Chapter 6 NIOS Based Example Codes ....................................................................54
6.1 Power Monitor..........................................................................................................................54
6.2 UART to USB Control LED.....................................................................................................58
6.3 SD Card Audio Demonstration.................................................................................................61
6.4 DDR3 SDRAM Test by Nios II................................................................................................65
6.5 Ethernet Socket server..............................................................................................................68
6.6 Digital Accelerometer Demonstration......................................................................................75
6.7 Humidity/Temperature Sensor..................................................................................................77
Chapter 7 Programming the Configuration Flash Memory ...................................79
7.1 Internal Configuration..............................................................................................................79
7.2 Using Dual Compressed Images...............................................................................................81
7.3 Nios II Load In Single Boot Image ..........................................................................................84

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Chapter 1
MAX 10 Plus Development Kit
The MAX 10 Plus board from Terasic is a full featured embedded evaluation kit based upon the
MAX10 family of Intel FPGAs. It offers a comprehensive design environment with everything
embedded developers need to create a processing-based system.
The MAX 10 Plus board delivers an integrated platform that includes hardware, design tools,
intellectual property and reference designs for developing a wide range of audio, video and many
other exciting applications.
The fully integrated kit allows developers to rapidly customize their processor and IP to suit their
specific needs, rather than constraining their software around the fixed feature set of the processor.
The all-in-one embedded solution, the MAX 10 Plus, making the best use of the parallel nature of
FPGAs.
1.1 Package Contents
Figure 1-1 shows a photograph of the MAX 10 Plus board package.
Figure 1-1 The MAX 10 Plus Board Package Contents
The MAX 10 Plus board package includes:
1. MAX 10 Plus board
2. MAX 10 Plus Quick Start Guide
3. 5V DC power adapter

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4. One USB cables (Type A to Mini-B) for USB control and FPGA programming and control
1.2 MAX 10 Plus System CD
The MAX 10 Plus System CD contains all the documents and supporting materials associated with
MAX 10 Plus, including the user manual, system builder, reference designs, and device datasheets.
Users can download this system CD from the link: http:// max10-plus.terasic.com/cd.
1.3 Getting Help
Here are the addresses where you can get help if you encounter any problems:
•Terasic Technologies
•9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
Email: [email protected]
Tel.: [phone]
Website: max10-plus.terasic.com

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Chapter 2
Introduction of the MAX 10 Plus
2.1 Layout and Components
Figure 2-1 shows a photograph of the board. It depicts the layout of the board and indicates the
location of the connectors and key components.
Figure 2-1 MAX 10 Plus Development Board (top view)
The MAX 10 Plus board has many features that allow users to implement a wide range of designed
circuits, from simple circuits to various multimedia projects.
The following hardware is provided on the board:
•Intel MAX® 10 10M50DAF484C6G device
•USB-Blaster II onboard for programming; JTAG Mode
•256MB DDR3 SDRAM (64Mx16 and 128Mx8)
•64MB QSPI Flash
•Micro SD card socket
•Five push-buttons
•Ten slide switches

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•Ten red user LEDs
•Two 7-segment displays
•Three 50MHz clock sources from the clock generator
•24-bit CD-quality audio CODEC with line-in, line-out jacks
•On-board microphone
•HDMI RX, incorporates HDM v1.4a features, including 3D video supporting
•Gigabit Ethernet PHY with RJ45 connector
•UART to USB, USB Mini-B connector
•One ambient light sensor
•One humidity and temperature sensor
•One accelerometer
•One external 16bit digital-to-analog converter (DAC) device with SMAoutput
•Potentiometer input to ADC
•Two MAX 10 FPGAADC SMA inputs
•One 2x10 ADC header with 16 analog inputs connected to MAX10 ADCs
2.2 Block Diagram of the MAX 10 Plus
Figure 2-2 is the block diagram of the board. All the connections are established through the MAX
10 FPGA device to provide maximum flexibility for users. Users can configure the FPGA to
implement any system design.
Figure 2-2 Block Diagram of MAX 10 Plus Board

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FPGA Device
•MAX 10 10M50DAF484C6G Device
•Integrated dualADCs, eachADC supports 1 dedicated analog input and 8 dual function pins
•50K programmable logic elements
•1,638Kbits embedded memory
•5,888Kbits user flash memory
•4 PLLs
Configuration and Debug
•On-board USB-Blaster II (Mini USB type B connector)
•Optional JTAG direct via 10-pin header
•One slide switch for dual boot image selection
Memory Device
•256MB DDR3 SDRAM (64Mx16 and 128Mx8)
•512MB QSPI Flash
•Micro SD card socket
Communication and Expansion Header
•Gigabit Ethernet PHY with RJ45 connector
•UART to USB, USB Mini-B connector
•PS/2 mouse/keyboard connector
•2x6 TMD (Terasic Mini Digital) Expansion Header
Audio
•24-bit CD-quality audio CODEC with line-in, line-out jacks
Video Input
•HDMI RX, incorporates HDM v1.4a features, including 3D video supporting
Analog
•Two MAX 10 FPGAADC SMA inputs
•Potentiometer input to ADC
•On-Board MIC input to ADC
•2x10 ADC header with 16 analog inputs connected to MAX10 ADCs
•One DAC SMA output
Switches, Buttons, and Indicators
•Five push-buttons
•Ten slide switches

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•Ten red user LEDs
•Two 7-segment displays
Sensors
•Ambient light sensor
•Humidity and temperature sensor
•Accelerometer
•Power monitor
Power
•5V/3A DC input

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Chapter 3
Using the MAX 10 Plus
This chapter provides an instruction to use the board and describes the peripherals.
3.1 Configuration of MAX 10 FPGA on MAX 10 Plus
There are two types of configuration method supported by MAX 10 Plus:
1. JTAG configuration: configuration using JTAG port.
JTAG configuration scheme allows you to directly configure the device core through JTAG pins -
TDI, TDO, TMS, and TCK pins. The Quartus II software automatically generates .sof that is used
for JTAG configuration with a download cable in the Quartus II software programmer.
2. Internal configuration: configuration using internal flash.
Before internal configuration, you need to program the configuration data into the configuration
flash memory (CFM) which provides non-volatile storage for the bit stream. The information is
retained within CFM even if the MAX 10 Plus is turned off. When the board is powered on, the
configuration data in the CFM is automatically loaded into the MAX 10 FPGA.
◼JTAG Chain on MAX 10 Plus
The FPGA device can be configured through JTAG interface on MAX 10 Plus board, but the JTAG
chain must form a closed loop, which allows Quartus II programmer to the detect FPGA device.
Figure 3-1 illustrates the JTAG chain on MAX 10 Plus.
Figure 3-1 Path of the JTAG Chain
◼Configure the FPGA in JTAG Mode
The following shows how the FPGA is programmed in JTAG mode step by step.
1. Open the Quartus II programmer and click Auto Detect, as circled in Figure 3-2.

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Figure 3-2 Detect FPGA Device in JTAG Mode
2. Select detected device associated with the board, as circled in Figure 3-3.
Figure 3-3 Select 10M50DAES Device
3. FPGA is detected, as shown in Figure 3-4.

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Figure 3-4 FPGA Detected in Quartus Programmer
4. Right click on the FPGA device and open the .sof file to be programmed, as highlighted in
Figure 3-5.
Figure 3-5 Open the .sof File to be Programmed into the FPGA Device

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5. Select the .sof file to be programmed, as shown in Figure 3-6.
Figure 3-6 Select the .sof File to be Programmed into the FPGA Device
6. Click Program/Configure check box and then click Start button to download the .sof file
into the FPGA device, as shown in Figure 3-7.
Figure 3-7 Program. sof File into the FPGA Device

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◼Internal Configuration
•The configuration data to be written to CFM will be part of the programmer object file (.pof).
This configuration data is automatically loaded from the CFM into the MAX 10 devices when
the board is powered up.
•Please refer to Chapter 7 Programming the Configuration Flash Memory for the basic
programming instruction on the configuration flash memory (CFM).
Figure 3-8 High-Level Overview of Internal Configuration for MAX 10 Devices
3.2 Board Status Elements
In addition to the 10 LEDs that FPGA device can control, there are 4 indicators which can indicate
the board status (See Figure 3-9), please refer the details in Table 3-1.
Figure 3-9 LED Indicators on MAX 10 Plus

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Table 3-1 LED Indicators
Board Reference
LED Name
Description
D13
5V Power
Illuminate when 5V power is active.
D14
2.5V Power
Illuminate when 2.5V power is active.
D16
1.2V Power
Illuminate when 1.2V power is active.
D6
CONF_DONE
Illuminate when configuration data is loaded into MAX 10 device
without error.
D7
JTAG_RX
Illuminate during data is uploaded from MAX 10 device to PC through
UB2.
D8
JTAG_TX
Illuminate during configuration data is loaded into MAX 10 device
from UB2.
TXD
TXD
Illuminate during transmitting data via USB.
RXD
RXD
Illuminate during receiving data via USB.
3.3 Clock Circuitry
Figure 3-10 shows the default frequency of all external clocks to the MAX 10 FPGA. A clock
generator is used to distribute clock signals with low jitter. The three 50MHz clock signals
connected to the FPGA are used as clock sources for user logic. One 25MHz clock signal is
connected to the clock input of Gigabit Ethernet Transceiver. One 24MHz clock signal is connected
to the clock inputs of USB microcontroller of USB Blaster II. One 28.63636MHz clock signal is
connected to the clock input of HDMI Receiver chip. The other 50MHz clock signal is connected to
MAX CPLD of USB Blaster II. One 10MHz clock signal is connected to the PLL1 and PLL3 of
FPGA, the outputs of these two PLLs can drive ADC clock. The associated pin assignment for
clock inputs to FPGA I/O pins is listed in Table 3-2.

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Figure 3-10 Block Diagram of the Clock Distribution on MAX 10 Plus
Table 3-2 PinAssignment of Clock Inputs
Signal Name
FPGA Pin No.
Description
I/O Standard
MAX10_CLK1_50
PIN_N5
50MHz clock input
2.5V
MAX10_CLK2_50
PIN_V9
50MHz clock input
3.3V
MAX10_CLK3_50
PIN_N14
50MHz clock input
1.5V
ADC_CLK_10
PIN_M9
10MHz clock input
3.3V
3.4 Peripherals Connected to the FPGA
This section describes the interfaces connected to the FPGA. User can control or monitor different
interfaces with user logic from the FPGA.
3.4.1 User Push-buttons, Switches, LEDs
The board has five push-buttons connected to the FPGA, as shown in Figure 3-11.MAX 10 devices
support Schmitt trigger input on all I/O pins. A Schmitt trigger feature introduces hysteresis to the
input signal for improved noise immunity, especially for signal with slow edge rate and act as
switch debounce in Figure 3-12 for the push-buttons connected.

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Figure 3-11 Connections between the Push-buttons and the MAX 10 FPGA
Figure 3-12 Switch Debouncing
There are two ten switches connected to the FPGA, as shown in Figure 3-13. These switches are
used as level-sensitive data inputs to a circuit. Each switch is connected directly and individually to
the FPGA. When the switch is set to the DOWN position (towards the edge of the board), it
generates a low logic level to the FPGA. When the switch is set to the UP position, a high logic
level is generated to the FPGA.
Pushbutton releasedPushbutton depressed
Before
Debouncing
Schmitt Trigger
Debounced

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Figure 3-13 Connections between the Slide Switches and the MAX 10 FPGA
There are also ten user-controllable LEDs connected to the FPGA. Each LED is driven directly and
individually by the MAX 10 FPGA; driving its associated pin to a high logic level or low level to
turn the LED on or off, respectively. Figure 3-14 shows the connections between LEDs and MAX
10 FPGA. Table 3-3,Table 3-4 and Table 3-5 list the pin assignment of user push-buttons, switches,
and LEDs.
Figure 3-14 Connections between the LEDs and the MAX 10 FPGA
Table 3-3 PinAssignment of Push-buttons
Signal Name
FPGA Pin No.
Description
I/O Standard
KEY[0]
PIN_T22
Push-button[0]
1.5V
KEY[1]
PIN_U22
Push-button[1]
1.5V
KEY[2]
PIN_AA22
Push-button[2]
1.5V
KEY[3]
PIN_AA21
Push-button[3]
1.5V

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KEY[4]
PIN_R22
Push-button[4]
1.5V
Table 3-4 PinAssignment of Slide Switches
Signal Name
FPGA Pin No.
Description
I/O Standard
SW[0]
PIN_N22
Slide Switch[0]
1.5V
SW[1]
PIN_M22
Slide Switch[1]
1.5V
SW[2]
PIN_N21
Slide Switch[2]
1.5V
SW[3]
PIN_L22
Slide Switch[3]
1.5V
SW[4]
PIN_J22
Slide Switch[4]
1.5V
SW[5]
PIN_H22
Slide Switch[5]
1.5V
SW[6]
PIN_J21
Slide Switch[6]
1.5V
SW[7]
PIN_C21
Slide Switch[7]
1.5V
SW[8]
PIN_G19
Slide Switch[8]
1.5V
SW[9]
PIN_H21
Slide Switch[9]
1.5V
Table 3-5 PinAssignment of LEDs
Signal Name
FPGA Pin No.
Description
I/O Standard
LEDR[0]
PIN_C2
LEDR [0]
3.3V
LEDR[1]
PIN_B3
LEDR [1]
3.3V
LEDR[2]
PIN_A3
LEDR [2]
3.3V
LEDR[3]
PIN_C3
LEDR [3]
3.3V
LEDR[4]
PIN_A4
LEDR [4]
3.3V
LEDR[5]
PIN_B4
LEDR [5]
3.3V
LEDR[6]
PIN_C4
LEDR [6]
3.3V
LEDR[7]
PIN_B5
LEDR [7]
3.3V
LEDR[8]
PIN_C5
LEDR [8]
3.3V
LEDR[9]
PIN_D5
LEDR [9]
3.3V
3.4.2 7-segment Displays
The MAX 10 Plus has two 7-segment displays. These displays are paired to display numbers in
various sizes. Figure 3-15 shows the connection of seven segments (common anode) to pins on
MAX 10 FPGA. The segment can be turned on or off by applying a low logic level or high logic
level from the FPGA, respectively.
Each segment in a display is indexed from 0 to 6, with corresponding positions given in Figure
3-15. Table 3-6 shows the pin assignment of FPGA to the 7-segment displays.

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Figure 3-15 Connections between the 7-segment Display HEX0 and the MAX 10 FPGA
Table 3-6 PinAssignment of 7-segment Displays
Signal Name
FPGA Pin No.
Description
I/O Standard
HEX0[0]
PIN_D6
Seven Segment Digit 0[0]
3.3V
HEX0[1]
PIN_A5
Seven Segment Digit 0[1]
3.3V
HEX0[2]
PIN_C6
Seven Segment Digit 0[2]
3.3V
HEX0[3]
PIN_A6
Seven Segment Digit 0[3]
3.3V
HEX0[4]
PIN_F7
Seven Segment Digit 0[4]
3.3V
HEX0[5]
PIN_D7
Seven Segment Digit 0[5]
3.3V
HEX0[6]
PIN_B7
Seven Segment Digit 0[6]
3.3V
HEX1[0]
PIN_C7
Seven Segment Digit 1[0]
3.3V
HEX1[1]
PIN_C8
Seven Segment Digit 1[1]
3.3V
HEX1[2]
PIN_D8
Seven Segment Digit 1[2]
3.3V
HEX1[3]
PIN_D10
Seven Segment Digit 1[3]
3.3V
HEX1[4]
PIN_E10
Seven Segment Digit 1[4]
3.3V
HEX1[5]
PIN_H11
Seven Segment Digit 1[5]
3.3V
HEX1[6]
PIN_E6
Seven Segment Digit 1[6]
3.3V
3.4.3 Power Monitor
The MAX 10 Plus has implemented three power monitor chips to monitor the FPGA core power
and VCCIO power voltage and current. Figure 3-16 shows the connection between the power
monitor chip and the MAX 10 FPGA. Through the I2C serial interface, the power monitor can be
configured to measure remote voltage and remote current. Programmable calibration value,
conversion times, and averaging, combined with an internal multiplier, enable direct readouts of
current in amperes and power in watts. Table 3-7 shows the pin assignment of power monitor I2C
bus.