Tews Technologies TPMC321 User manual

The Embedded I/O Company
TPMC321
Conducion cooled 64 Digital TTL I/O / 32 Differential I/O
Version 1.0
User Manual
Issue 1.0.0
April 2022
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7 25469 Halstenbek, Germany
Phone: [phone] Fax: [phone]
e-mail: [email protected] www.tews.com

TPMC321 User Manual Issue 1.0.0 Page 2 of 33
TPMC321-10R
Conduction Cooled, 64-bit TTL I/O, Bit I/O,
Interrupts, P14 I/O
(RoHS compliant)
TPMC321-11R
Conduction Cooled, 32-bit EIA-422 / EIA-485 I/O,
Bit I/O, Interrupts, P14 I/O
(RoHS compliant)
TPMC321-12R
Conduction Cooled, 32-bit M-LVDS I/O, Bit I/O,
Interrupts, P14 I/O
(RoHS compliant)
This document contains information, which is
proprietary to TEWS TECHNOLOGIES GmbH. Any
reproduction without written permission is forbidden.
TEWS TECHNOLOGIES GmbH has made any
effort to ensure that this manual is accurate and
complete. However, TEWS TECHNOLOGIES
GmbH reserves the right to change the product
described in this document at any time without
notice.
TEWS TECHNOLOGIES GmbH is not liable for any
damage arising out of the application or use of the
device described herein.
2022 by TEWS TECHNOLOGIES GmbH
All trademarks mentioned are property of their respective owners.

TPMC321 User Manual Issue 1.0.0 Page 3 of 33
Issue Description Date
1.0.0 Initial issue April 2022

TPMC321 User Manual Issue 1.0.0 Page 4 of 33
Table of Contents
1 PRODUCT DESCRIPTION ........................................................................................... 6
2 TECHNICAL SPECIFICATION ..................................................................................... 7
3 HANDLING AND OPERATION INSTRUCTIONS ......................................................... 8
ESD Protection ................................................................................................................................8
4 TERMS AND DEFINITIONS.......................................................................................... 9
Register Bit Access Types.............................................................................................................9
Style Conventions...........................................................................................................................9
5 PCI INTERFACE ......................................................................................................... 10
PCI Identifiers ................................................................................................................................10
PCI Base Address Register Configuration .................................................................................10
Configuration Register Space .....................................................................................................10
5.3.1 Register Map...........................................................................................................................11
5.3.2 Register Description................................................................................................................11
5.3.2.1 Functional Register Space Descriptor (LAS0BRD) ...........................................................11
5.3.2.2 Interrupt Control/Status (INTCSR).....................................................................................12
5.3.2.3 Serial EEPROM and Initialization Control (CNTRL) ..........................................................13
5.3.2.4 General Purpose I/O Control (GPIOC) ..............................................................................14
5.3.2.5 Configuration Space Revision Register (CREVREG) .......................................................15
Serial EEPROM..............................................................................................................................15
Functional Register Space ...........................................................................................................16
5.5.1 Register Map...........................................................................................................................16
5.5.2 Register Description................................................................................................................17
5.5.2.1 Output Register 0 (OUT_REG0)........................................................................................17
5.5.2.2 Output Register 1 (OUT_REG1)........................................................................................18
5.5.2.3 Input Register 0 (IN_REG0) ..............................................................................................19
5.5.2.4 Input Register 1 (IN_REG1) ..............................................................................................20
5.5.2.5 Output Enable Register 0 (OE_REG0)..............................................................................21
5.5.2.6 Output Enable Register 1 (OE_REG1)..............................................................................22
5.5.2.7 Interrupt Status Register 0 (ISR0) .....................................................................................23
5.5.2.8 Interrupt Status Register 1 (ISR1) .....................................................................................24
5.5.2.9 Positive Edge Interrupt Enable Register 0 (PIER0)...........................................................25
5.5.2.10 Positive Edge Interrupt Enable Register 1 (PIER1)...........................................................26
5.5.2.11 Negative Edge Interrupt Enable Register 0 (NIER0).........................................................27
5.5.2.12 Negative Edge Interrupt Enable Register 1 (NIER1).........................................................28
5.5.2.13 Functional Space Revision Register (FREVREG).............................................................29
6 FUNCTIONAL DESCRIPTION.................................................................................... 30
TTL I/O Interface............................................................................................................................30
6.1.1 Output Line Switching .............................................................................................................30
6.1.2 TTL Buffer Pull Up Voltage .....................................................................................................31
Differential I/O-Interface ...............................................................................................................31
Optional P14 Ground Connections .............................................................................................32
7 PIN ASSIGNMENT – I/O CONNECTOR ..................................................................... 33
P14 Back I/O Connector ...............................................................................................................33

TPMC321 User Manual Issue 1.0.0 Page 5 of 33
List of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................6
FIGURE 9-1 : TTL I/O INTERFACE ................................................................................................................30
FIGURE 9-2 : PULL UP VOLTAGE JUMPER SETTING ................................................................................31
FIGURE 9-3 : DIFFERENTIAL I/O INTERFACE.............................................................................................31
FIGURE 6-4 : DEFAULT 0Ω BRIDGES ON PCB TOP SIDE (MARKED IN RED) ......................................... 32
FIGURE 6-5 : OPTIONAL GND CONNECTION ON PCB BOTTOM SIDE (PADS MARKED IN RED) .........32
List of Tables
TABLE 2-1 : TECHNICAL SPECIFICATION.....................................................................................................7
TABLE 3-5 : PCI IDENTIFIERS ......................................................................................................................10
TABLE 3-6 : PCI BASE ADDRESS REGISTERS ...........................................................................................10
TABLE 7-2 : CONFIGURATION REGISTER SPACE.....................................................................................11
TABLE 8-1 : FUNCTIONAL REGISTER SPACE DESCRIPTOR (LAS0BRD) ...............................................11
TABLE 8-2 : INTERRUPT CONTROL/STATUS (INTCSR) ............................................................................12
TABLE 8-3 : SERIAL EEPROM AND INITIALIZATION CONTROL (CNTRL) ................................................13
TABLE 8-4 : GENERAL PURPOSE I/O CONTROL (GPIOC) ........................................................................14
TABLE 8-5 : REVISION REGISTER (CREVREG) ..........................................................................................15
TABLE 8-19: SERIAL EEPROM CONTENT ...................................................................................................15
TABLE 7-3 : FUNCTIONAL REGISTER SPACE ............................................................................................16
TABLE 8-6 : OUTPUT REGISTER 0 (OUT_REG0)........................................................................................17
TABLE 8-7 : OUTPUT REGISTER 1 (OUT_REG1)........................................................................................18
TABLE 8-8 : INPUT REGISTER 0 (IN_REG0)................................................................................................19
TABLE 8-9 : INPUT REGISTER 1 (IN_REG1)................................................................................................20
TABLE 8-10: OUTPUT ENABLE REGISTER 0 (OE_REG0)..........................................................................21
TABLE 8-11: OUTPUT ENABLE REGISTER 1 (OE_REG1)..........................................................................22
TABLE 8-12: INTERRUPT STATUS REGISTER 0 (ISR0) .............................................................................23
TABLE 8-13: INTERRUPT STATUS REGISTER 1 (ISR1) .............................................................................24
TABLE 8-14: POSITIVE EDGE INTERRUPT ENABLE REGISTER 0 (PIER0)..............................................25
TABLE 8-15: POSITIVE EDGE INTERRUPT ENABLE REGISTER 1 (PIER1)..............................................26
TABLE 8-16: NEGATIVE EDGE INTERRUPT ENABLE REGISTER 0 (NIER0)............................................27
TABLE 8-17: NEGATIVE EDGE INTERRUPT ENABLE REGISTER 1 (NIER1)............................................28
TABLE 8-18: REVISION REGISTER (FREVREG) .........................................................................................29
TABLE 5-1 : P14 BACK I/O CONNECTOR.....................................................................................................33

TPMC321 User Manual Issue 1.0.0 Page 6 of 33
1 Product Description
The TPMC321 is a conduction cooled single-width 32 bit PMC module offering 64 ESD-protected 5V-tolerant
TTL lines or 32 differential I/O lines using ESD-protected EIA-422 / EIA-485 compatible line transceivers or
Multipoint-LVDS transceivers.
Each line is individually programmable as input, output or tri-state. The receivers are always enabled, which
allows determining the state of each I/O line at any time. This can be used as read back function for lines
configured as outputs. Each TTL I/O line has a pull-up resistor. The pull-up voltage is selectable to be either
+3.3V or +5V. Differential I/O lines are terminated, EIA-422 / EIA-485 lines with 120 Ω, M-LVDS lines with
100 Ω.
Each input can generate an interrupt. Signal edge handling is programmable to interrupt on rising and/or
falling edge of an input signal. Interrupts can be enabled and disabled for each bit. For interrupt source
detection the status of each bit can be read from interrupt status registers.
The TPMC321 provides rear I/O via P14.
Figure 1-1 : Block Diagram

TPMC321 User Manual Issue 1.0.0 Page 7 of 33
2 Technical Specification
PMC Interface
Mechanical Interface
Conduction Cooled PCI Mezzanine Card (PMC) Interface
confirming to ANSI/VITA 20-2001 (R2005)
Single Size (143.75 mm x 74 mm)
Electrical Interface
PCI Rev. 3.0 compatible
33 MHz / 32 bit PCI
3.3V and 5V PCI Signaling Voltage
On Board Devices
PCI Target Chip and
Local Control Logic MachXO2 LCMXO2-4000HC (Lattice)
TTL Line Transceivers 74LVT126
EIA-485 Transceivers MAX3078E
M-LVDS Transceivers SN65MLVD206D
I/O Interface
Number of Channels 64 TTL or 32 Differential Bit I/O Lines
I/O Standards
TTL signaling voltage level (maximum current: +/- 24 mA)
EIA-485 with 120 Ω Termination
M-LVDS with 100 Ω Termination
I/O Connector PMC P14 I/O (64 pin Mezzanine Connector)
Physical Data
Power Requirements
TPMC321-10R:
40 mA typical @ +5V (transceiver disabled, no load)
200 mA typical @ +5V (transceiver enabled, no load)
TPMC321-11R:
50 mA typical @ +5V DC (transceiver disabled, no load)
700 mA typical @ +5V DC (transceiver enabled, no load)
Temperature Range Operating
Storage
-40°C to +85°C
-40°C to +85°C
MTBF
TPMC321-10R: 350 000 h
TPMC321-11R: 891 000 h
TPMC321-12R: 845 000 h
MTBF values shown are based on calculation according to MIL-HDBK-217F and
MIL-HDBK-217F Notice 2; Environment: GB20°C.
The MTBF calculation is based on component FIT rates provided by the
component suppliers. If FIT rates are not available, MIL-HDBK-217F and
MIL-HDBK-217F Notice 2 formulas are used for FIT rate calculation.
Humidity 5 – 95 % non-condensing
Weight 53 g
Table 2-1 : Technical Specification

TPMC321 User Manual Issue 1.0.0 Page 8 of 33
3 Handling and Operation Instructions
ESD Protection
This PMC module is sensitive to static electricity.
Packing, unpacking and all other module handling has to be done
with appropriate care.

TPMC321 User Manual Issue 1.0.0 Page 9 of 33
4 Terms and Definitions
Register Bit Access Types
Register Bit Access
Type Description
R Read The bit is readable by software
R/W Read/Write The bit is readable and writeable by software
R/C Read/Clear The bit is readable by software
The bit is set by firmware
Software may clear the bit by writing a ‘1’
R/S Read/Set The bit is readable by software
Software may set this bit to ‘1’
The bit is cleared by firmware
When reading reserved register bits, the read value is undefined.
For future software compatibility: For register write access reserved bits shall be written ‘0’.
Style Conventions
Hexadecimal characters are specified with prefix 0x (i.e. 0x029E).
For signals on hardware products, "Active Low" is represented by the signal name with an added # (i.e.
IP_RESET#).

TPMC321 User Manual Issue 1.0.0 Page 10 of 33
5 PCI Interface
PCI Identifiers
Vendor-ID 0x1498 (TEWS TECHNOLOGIES)
Device-ID 0x0141 (TPMC321)
Class Code 0x118000 (Other data acquisition/signal
processing controllers)
Subsystem Vendor-ID 0x1498 (TEWS TECHNOLOGIES)
Subsystem Device-ID 0x000A (TPMC321-10R)
0x000B (TPMC321-11R)
0x000C (TPMC321-12R)
Table 5-1 : PCI Identifiers
PCI Base Address Register Configuration
For backward compatibility a subset of PCI9030 registers have been implemented within the PLD besides
the Local Control Logic. This subset contains all registers that are used by the standard TEWS module
driver.
PCI Base Address Register
(Offset in PCI
Configuration Space)
PCI
Space
Mapping
Size
(Byte)
Port
Width
(Bit)
Endian
Mode Description
0 (0x10) MEM 128 32 Little Configuration Register Space
1 (0x14) I/O 128 32 Little
2 (0x18) MEM 256 32 BIG *) Functional Register Space
Table 5-2 : PCI Base Address Registers
*) Can be configured in the “Functional Register Space Descriptor (LAS0BRD)” register. Default is BIG.

TPMC321 User Manual Issue 1.0.0 Page 11 of 33
Configuration Register Space
5.3.1 Register Map
Offset to PCI Base
Address 2 Description Size
(Bit)
0x00 - 0x27 - -
0x28 Local Address Space 0 Bus Region Descriptor (LAS0BRD) 32
0x2C - 0x4B - -
0x4C Interrupt Control/Status (INTCSR) 32
0x50 Serial EEPROM and Initialization Control (CNTRL) 32
0x54 General Purpose I/O Control (GPIOC) 32
0x58 - 0x7B - -
0x7C Configuration Space Revision Register (CREVREG) 32
Table 5-3 : Configuration Register Space
5.3.2 Register Description
5.3.2.1 Functional Register Space Descriptor (LAS0BRD)
Bit Symbol Description Access Reset
Value
31:25 - Reserved R 0
24 ASBYTE_ORDER Address Space Byte Ordering
1: activate Big Endian
0: activate Little Endian
R/W 1
23:0 - Reserved R 0
Table 5-4 : Functional Register Space Descriptor (LAS0BRD)

TPMC321 User Manual Issue 1.0.0 Page 12 of 33
5.3.2.2 Interrupt Control/Status (INTCSR)
Bit Symbol Description Access Reset
Value
31:8 - Reserved R 0
7 SW_INT Software Interrupt
1: generates PCI Interrupt (INTA# output
asserted) if PCI Interrupt Enable bit is set (bit
[6]=1)
0: clears PCI Interrupt
R/W 0
6 PCI_INT_EN PCI Interrupt Enable
1: enables PCI interrupt
0: disables PCI interrupt
R/W 1
5:3 - Reserved R 0
2 LINT_STAT Local Interrupt (LINTi1) Status
1: indicates interrupt active
0: indicates Interrupt not active
R 0
1 LINT_POL Local Interrupt (LINTi1) Polarity
1: adjusts active high polarity
0: adjusts active low polarity
R/W 0
0 LINT_EN Local Interrupt (LINTi1) Enable
1: enables Local Control Logic interrupts
0: disables Local Control Logic interrupts
R/W 1
Table 5-5 : Interrupt Control/Status (INTCSR)

TPMC321 User Manual Issue 1.0.0 Page 13 of 33
5.3.2.3 Serial EEPROM and Initialization Control (CNTRL)
Bit Symbol Description Access Reset
Value
31 - Reserved R 0
30 SWRST Software Reset
1: resets the Functional Register Space. Reset
stays active until it is cleared
0: clears the Functional Register Space reset
R/W 0
29 - Reserved R 0
28 EEPRSNT Serial EEPROM Present
1: indicates serial EEPROM is present
0: indicates no serial EEPROM is present
R 1
27 EEDO Serial EEPROM Data Out Bit
This bit is the data output of the serial EEPROM R -
26 EEDI Serial EEPROM Data In Bit
This bit is the data input of the serial EEPROM R/W 0
25 EECS Serial EEPROM Chip Select
1: asserts serial EEPROM chip select
0: de-asserts serial EEPROM chip select
R/W 0
24 EESK Serial EEPROM Clock
Toggling this bit generates a serial EEPROM clock R/W 0
23:0 - Reserved R 0
Table 5-6 : Serial EEPROM and Initialization Control (CNTRL)

TPMC321 User Manual Issue 1.0.0 Page 14 of 33
5.3.2.4 General Purpose I/O Control (GPIOC)
Bit Symbol Description Access Reset
Value
31:12 - Reserved R 0
11 GPIO3_DATA GPIO3 Data
Output Function: Stimulates corresponding pin
Input Function: Provides state of corresponding
pin
R/W 0
10 GPIO3_DDR GPIO3 Data Direction
1: activates output function
0: activates input function
R/W 0
9 - Reserved R 0
8 GPIO2_DATA GPIO2 Data
Output Function: Stimulates corresponding pin
Input Function: Provides state of corresponding
pin
R/W 0
7 GPIO2_DDR GPIO2 Data Direction
1: activates output function
0: activates input function
R/W 0
6 - Reserved R 0
5 GPIO1_DATA GPIO1 Data
Internally connected to 1 (backward compatibility).
Formerly linked to PROGRAM# pin.
R/W 1
4 GPIO1_DDR GPIO1 Data Direction
GPIO1 represents PROGRAM# state. Hence the
direction configuration is not implemented (input
only).
R 0
3 - Reserved R 0
2 GPIO0_DATA GPIO0 Data
Internally connected to 1 (backward compatibility).
Formerly linked to DONE pin.
R 1
1 GPIO0_DDR GPIO0 Data Direction
GPIO0 represents DONE state. Hence the
direction configuration is not implemented (input
only).
R 0
0 - Reserved R 0
Table 5-7 : General Purpose I/O Control (GPIOC)
The GPIO functionality has been implemented for backward-compatibility reason.

TPMC321 User Manual Issue 1.0.0 Page 15 of 33
5.3.2.5 Configuration Space Revision Register (CREVREG)
Bit Symbol Description Access Reset
Value
31:0 CREVREG Firmware Version Register for Configuration
Space R *)
Table 5-8 : Revision Register (CREVREG)
*) Depends on Firmware Version
Serial EEPROM
The serial EEPROM is not used for storing any configuration settings. All configuration data is stored within
the internal Flash of the PLD. Hence, the device can be completely be used as memory.
For backward compatibility the serial EEPROM contains the configuration data of the previous version PCI
controller.
Address Offset
0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E
0x00 0x0141 0x1498 0x0280 0x0000 0x1180 0x0000 see below 0x1498
0x10 0x0000 0x0040 0x0000 0x0100 0x4801 0x0001 0x0000 0x0000
0x20 0x0000 0x0006 0x0000 0x0003 0x0FFF 0xFF00 0x0000 0x0000
0x30 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0001
0x40 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000
0x50 0x1581 0x20A0 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000
0x60 0x0000 0x0000 0x0000 0x0081 0x0000 0x0002 0x0000 0x0002
0x70 0x0000 0x0002 0x0030 0x0041 0x0078 0x0000 0x0000 0x0240
0x80 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF
0x90 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
0xA0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
0xB0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
0xC0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
0xD0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
0xE0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
0xF0 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
Table 5-9: Serial EEPROM Content
Subsystem-ID Value (Offset 0x0C): TPMC321-10R: 0x000A
TPMC321-11R: 0x000B
TPMC321-12R: 0x000C

TPMC321 User Manual Issue 1.0.0 Page 16 of 33
Functional Register Space
5.5.1 Register Map
Offset to PCI Base
Address 2 Description Size
(Bit)
0x00 Output Register 0 (OUT_REG0) 32
0x04 Output Register 1 (OUT_REG1) 32
0x08 Input Register 0 (IN_REG0) 32
0x0C Input Register 1 (IN_REG1) 32
0x10 Output Enable Register 0 (OE_REG0) 32
0x14 Output Enable Register 1 (OE_REG1) 32
0x18 Interrupt Status Register 0 (ISR0) 32
0x1C Interrupt Status Register 1 (ISR1) 32
0x20 Positive Edge Interrupt Enable Register (PIER0) 32
0x24 Positive Edge Interrupt Enable Register (PIER1) 32
0x28 Negative Edge Interrupt Enable Register (NIER0) 32
0x2C Negative Edge Interrupt Enable Register (NIER1) 32
0x30 - 0x7B - -
0xFC Functional Register Space Revision Register (FREVREG) 32
Table 5-10 : Functional Register Space

TPMC321 User Manual Issue 1.0.0 Page 17 of 33
5.5.2 Register Description
5.5.2.1 Output Register 0 (OUT_REG0)
Please note the “Output Line Switching”-chapter.
Bit Symbol Description Access Reset
Value
31 OUT_REG_BIT_31
Output Port bit 31:0 Data R/W 0
30 OUT_REG_BIT_30
29 OUT_REG_BIT_29
28 OUT_REG_BIT_28
27 OUT_REG_BIT_27
26 OUT_REG_BIT_26
25 OUT_REG_BIT_25
24 OUT_REG_BIT_24
23 OUT_REG_BIT_23
22 OUT_REG_BIT_22
21 OUT_REG_BIT_21
20 OUT_REG_BIT_20
19 OUT_REG_BIT_19
18 OUT_REG_BIT_18
17 OUT_REG_BIT_17
16 OUT_REG_BIT_16
15 OUT_REG_BIT_15
14 OUT_REG_BIT_14
13 OUT_REG_BIT_13
12 OUT_REG_BIT_12
11 OUT_REG_BIT_11
10 OUT_REG_BIT_10
9 OUT_REG_BIT_9
8 OUT_REG_BIT_8
7 OUT_REG_BIT_7
6 OUT_REG_BIT_6
5 OUT_REG_BIT_5
4 OUT_REG_BIT_4
3 OUT_REG_BIT_3
2 OUT_REG_BIT_2
1 OUT_REG_BIT_1
0 OUT_REG_BIT_0
Table 5-11 : Output Register 0 (OUT_REG0)

TPMC321 User Manual Issue 1.0.0 Page 18 of 33
5.5.2.2 Output Register 1 (OUT_REG1)
Please note the “Output Line Switching”-chapter. For the TPMC321-11R and -12R variants this register is
read- and writeable, but the outputs are unused.
Bit Symbol Description Access Reset
Value
63 OUT_REG_BIT_63
Output Port bit 63:32 Data R/W 0
62 OUT_REG_BIT_62
61 OUT_REG_BIT_61
60 OUT_REG_BIT_60
59 OUT_REG_BIT_59
58 OUT_REG_BIT_58
57 OUT_REG_BIT_57
56 OUT_REG_BIT_56
55 OUT_REG_BIT_55
54 OUT_REG_BIT_54
53 OUT_REG_BIT_53
52 OUT_REG_BIT_52
51 OUT_REG_BIT_51
50 OUT_REG_BIT_50
49 OUT_REG_BIT_49
48 OUT_REG_BIT_48
47 OUT_REG_BIT_47
46 OUT_REG_BIT_46
45 OUT_REG_BIT_45
44 OUT_REG_BIT_44
43 OUT_REG_BIT_43
42 OUT_REG_BIT_42
41 OUT_REG_BIT_41
40 OUT_REG_BIT_40
39 OUT_REG_BIT_39
38 OUT_REG_BIT_38
37 OUT_REG_BIT_37
36 OUT_REG_BIT_36
35 OUT_REG_BIT_35
34 OUT_REG_BIT_34
33 OUT_REG_BIT_33
32 OUT_REG_BIT_32
Table 5-12 : Output Register 1 (OUT_REG1)

TPMC321 User Manual Issue 1.0.0 Page 19 of 33
5.5.2.3 Input Register 0 (IN_REG0)
Read directly from the I/O lines 31 to 0.
Bit Symbol Description Access Reset
Value
31 IN_REG_BIT_31
Input Port bit 31:0 Data R -
30 IN_REG_BIT_30
29 IN_REG_BIT_29
28 IN_REG_BIT_28
27 IN_REG_BIT_27
26 IN_REG_BIT_26
25 IN_REG_BIT_25
24 IN_REG_BIT_24
23 IN_REG_BIT_23
22 IN_REG_BIT_22
21 IN_REG_BIT_21
20 IN_REG_BIT_20
19 IN_REG_BIT_19
18 IN_REG_BIT_18
17 IN_REG_BIT_17
16 IN_REG_BIT_16
15 IN_REG_BIT_15
14 IN_REG_BIT_14
13 IN_REG_BIT_13
12 IN_REG_BIT_12
11 IN_REG_BIT_11
10 IN_REG_BIT_10
9 IN_REG_BIT_9
8 IN_REG_BIT_8
7 IN_REG_BIT_7
6 IN_REG_BIT_6
5 IN_REG_BIT_5
4 IN_REG_BIT_4
3 IN_REG_BIT_3
2 IN_REG_BIT_2
1 IN_REG_BIT_1
0 IN_REG_BIT_0
Table 5-13 : Input Register 0 (IN_REG0)

TPMC321 User Manual Issue 1.0.0 Page 20 of 33
5.5.2.4 Input Register 1 (IN_REG1)
Read directly from the I/O lines 63 to 32. For the TPMC321-11R and -12R variants this register reads 0.
Bit Symbol Description Access Reset
Value
63 IN_REG_BIT_63
Input Port bit 63:32 Data R -
62 IN_REG_BIT_62
61 IN_REG_BIT_61
60 IN_REG_BIT_60
59 IN_REG_BIT_59
58 IN_REG_BIT_58
57 IN_REG_BIT_57
56 IN_REG_BIT_56
55 IN_REG_BIT_55
54 IN_REG_BIT_54
53 IN_REG_BIT_53
52 IN_REG_BIT_52
51 IN_REG_BIT_51
50 IN_REG_BIT_50
49 IN_REG_BIT_49
48 IN_REG_BIT_48
47 IN_REG_BIT_47
46 IN_REG_BIT_46
45 IN_REG_BIT_45
44 IN_REG_BIT_44
43 IN_REG_BIT_43
42 IN_REG_BIT_42
41 IN_REG_BIT_41
40 IN_REG_BIT_40
39 IN_REG_BIT_39
38 IN_REG_BIT_38
37 IN_REG_BIT_37
36 IN_REG_BIT_36
35 IN_REG_BIT_35
34 IN_REG_BIT_34
33 IN_REG_BIT_33
32 IN_REG_BIT_32
Table 5-14 : Input Register 1 (IN_REG1)