Tews Technologies TXMC638 User manual

The Embedded I/O Company
TXMC638
Reconfigurable FPGA with 24 x 16 Bit Analog Input
Version 1.0
User Manual
Issue 1.0.2
October 2017
TEWS TECHNOLOGIES GmbH
Am Bahnhof 7 25469 Halstenbek, Germany
Phone: [phone] Fax: [phone]
e-mail: [email protected] www.tews.com

TXMC638 User Manual Issue 1.0.2 Page 2 of 86
TXMC638-10R
24 x Analog In and 64 direct FPGA Back I/O
Lines,
XC7K160T-2 FBG676 Kintex-7 FPGA, 1GB
DDR3
TXMC638-11R
24 x Analog In and 64 direct FPGA Back I/O
Lines,
XC7K325T-2 FBG676 Kintex-7 FPGA, 1GB
DDR3
TXMC638-12R
24 x Analog In and 64 direct FPGA Back I/O
Lines,
XC7K410T-2 FBG676 Kintex-7 FPGA, 1GB
DDR3
This document contains information, which is
proprietary to TEWS TECHNOLOGIES GmbH. Any
reproduction without written permission is forbidden.
TEWS TECHNOLOGIES GmbH has made any
effort to ensure that this manual is accurate and
complete. However TEWS TECHNOLOGIES GmbH
reserves the right to change the product described
in this document at any time without notice.
TEWS TECHNOLOGIES GmbH is not liable for any
damage arising out of the application or use of the
device described herein.
Style Conventions
Hexadecimal characters are specified with prefix 0x,
i.e. 0x029E (that means hexadecimal value 029E).
For signals on hardware products, an ‚Active Low’ is
represented by the signal name with # following, i.e.
IP_RESET#.
Access terms are described as:
W Write Only
R Read Only
R/W Read/Write
R/C Read/Clear
R/S Read/Set
¤2017 by TEWS TECHNOLOGIES GmbH
All trademarks mentioned are property of their respective owners.

TXMC638 User Manual Issue 1.0.2 Page 3 of 86
Issue Description Date
1.0.0 Initial issue October 2016
1.0.1
Additions to the technical specifiction and correction of the
MGT Connections Table.
User FPGA Configuration Flow Charts enhanced.
November 2016
1.0.2 Insert the missing Flow Charts in Chapter 7.4.2 to 7.4.8. October 2017

TXMC638 User Manual Issue 1.0.2 Page 4 of 86
Table of Contents
1 PRODUCT DESCRIPTION ........................................................................................... 8
2 TECHNICAL SPECIFICATION ..................................................................................... 9
3 HANDLING AND OPERATION INSTRUCTION ......................................................... 11
ESD Protection ..............................................................................................................................11 3.1
Thermal Considerations...............................................................................................................11 3.2
Assembling Hints..........................................................................................................................11 3.3
4 PCI DEVICE TOPOLOGY ........................................................................................... 12
User FPGA (Kintex-7)....................................................................................................................13 4.1
BCC (Board Configuration Controller) FPGA ............................................................................13 4.2
4.2.1 PCI Configuration Registers (PCR) ........................................................................................13
4.2.2 PCI BAR Overview..................................................................................................................13
4.2.2.1 Local Configuration Register Space ..................................................................................14
4.2.2.2 In-System Programming Data Space ................................................................................15
5 REGISTER DESCRIPTION......................................................................................... 16
User FPGA (Kintex-7)....................................................................................................................16 5.1
Board Configuration Controller (BCC - FPGA) ..........................................................................16 5.2
5.2.1 Interrupt Enable Register - 0xC0 ............................................................................................16
5.2.2 Interrupt Status Register - 0xC4 .............................................................................................16
5.2.3 User FPGA Configuration Control/Status Register - 0xD0.....................................................17
5.2.4 User FPGA Configuration Data Register - 0xD4 ....................................................................18
5.2.5 ISP Control Register - 0xE0....................................................................................................19
5.2.6 ISP Configuration Register - 0xE4..........................................................................................19
5.2.7 ISP Command Register - 0xE8...............................................................................................20
5.2.8 ISP Status Register - 0xEC ....................................................................................................20
5.2.9 TXMC638 Serial Number - 0xF8 ............................................................................................21
5.2.10 BCC - FPGA Code Version - 0xFC.........................................................................................21
6 INTERRUPTS.............................................................................................................. 22
Interrupt Sources ..........................................................................................................................22 6.1
6.1.1 User FPGA (Kintex-7).............................................................................................................22
6.1.2 Board Configuration Controller (BCC - FPGA) .......................................................................22
Interrupt Handling .........................................................................................................................22 6.2
6.2.1 User FPGA (Kintex-7).............................................................................................................22
6.2.2 Board Configuration Controller (BCC - FPGA) .......................................................................22
7 FUNCTIONAL DESCRIPTION.................................................................................... 23
User FPGA Block Diagram...........................................................................................................23 7.1
User FPGA Highlights...................................................................................................................24 7.2
User FPGA Gigabit Transceiver (MGT) .......................................................................................25 7.3
User FPGA Configuration ............................................................................................................27 7.4
7.4.1 Master Serial SPI Flash Configuration....................................................................................27
7.4.2 Manually User FPGA SPI Flash Reconfiguration ...................................................................28
7.4.3 Slave Select Map Configuration .............................................................................................29
7.4.4 Configuration via JTAG...........................................................................................................31
7.4.5 Programming User FPGA SPI Configuration Flash................................................................32
7.4.6 Erasing User FPGA SPI Configuration Flash .........................................................................33
7.4.7 Sector Erasing User FPGA SPI Configuration Flash..............................................................34
7.4.8 Reading User FPGA SPI Configuration Flash........................................................................35

TXMC638 User Manual Issue 1.0.2 Page 5 of 86
Board Configuration Controller (BCC – FPGA) .........................................................................35 7.5
Clocking .........................................................................................................................................36 7.6
7.6.1 FPGA Clock Sources..............................................................................................................36
7.6.2 Si514 Free Programming Clock source..................................................................................38
Back I/O Interface..........................................................................................................................39 7.7
Memory ..........................................................................................................................................41 7.8
7.8.1 DDR3 SDRAM ........................................................................................................................41
7.8.2 SPI-Flash ................................................................................................................................44
7.8.3 I2C - EEPROM........................................................................................................................44
7.8.3.1 I2C Calibration Data ..........................................................................................................44
7.8.3.2 ADC Calibration Data Values ............................................................................................45
7.8.3.3 ADC Data Correction Formula...........................................................................................46
Serial ADC Interface......................................................................................................................47 7.9
7.9.1 Overview .................................................................................................................................47
7.9.2 ADC digital Output Coding......................................................................................................48
7.9.3 User FPGA Pinning.................................................................................................................49
7.9.4 Programming Hints LTC2323-16 ............................................................................................53
AC coupled differential Inputs.....................................................................................................54 7.10
Serial Number Allocation .............................................................................................................55 7.11
7.11.1 Device Addressing and Operation..........................................................................................55
7.11.2 Read Operation.......................................................................................................................56
7.11.3 Write Operation.......................................................................................................................56
On-Board Indicators .....................................................................................................................57 7.12
Thermal Management ...................................................................................................................58 7.13
8 DESIGN HELP ............................................................................................................ 59
Board Reference Design ..............................................................................................................59 8.1
9 INSTALLATION .......................................................................................................... 60
I/O Interface ...................................................................................................................................60 9.1
9.1.1 Front I/O - ADC Analog Input Level........................................................................................60
9.1.2 Front I/O – AC coupled differential Inputs ..............................................................................62
9.1.3 Back I/O Interface ...................................................................................................................62
FPGA JTAG Connector.................................................................................................................63 9.2
10 PIN ASSIGNMENT – I/O CONNECTOR ..................................................................... 64
Overview ........................................................................................................................................64 10.1
X1 Front Panel I/O Connector ......................................................................................................65 10.2
10.2.1 Connector Type ......................................................................................................................65
10.2.2 Pin Assignment .......................................................................................................................65
Back I/O XMC Connector P14 ......................................................................................................67 10.3
10.3.1 Connector Type ......................................................................................................................67
10.3.2 Pin Assignment .......................................................................................................................67
P16 Back I/O Connector ...............................................................................................................69 10.4
10.4.1 Connector Type ......................................................................................................................69
10.4.2 Pin Assignment .......................................................................................................................69
X4 FPGA JTAG Header.................................................................................................................70 10.5
10.5.1 Connector Type ......................................................................................................................70
10.5.2 Pin Assignment .......................................................................................................................70
11 APPENDIX A............................................................................................................... 71

TXMC638 User Manual Issue 1.0.2 Page 6 of 86
List of Figures
FIGURE 1-1 : BLOCK DIAGRAM......................................................................................................................8
FIGURE 4-1 : PCIE/PCI DEVICE TOPOLOGY...............................................................................................12
FIGURE 7-1 : FPGA BLOCK DIAGRAM.........................................................................................................23
FIGURE 7-2 : GTP BLOCK DIAGRAM ...........................................................................................................25
FIGURE 7-3 : USER JTAG-CHAIN ................................................................................................................31
FIGURE 7-4 : TEWS FACTORY JTAG-CHAIN ..............................................................................................31
FIGURE 7-5 : FPGA CLOCK SOURCES.......................................................................................................36
FIGURE 7-6 : ANALOG INPUT SECTION.....................................................................................................47
FIGURE 7-7 : ANALOG INPUT BLOCK DIAGRAM.......................................................................................47
FIGURE 7-8 : DIGITAL ADC TO FPGA INTERFACE....................................................................................53
FIGURE 7-9 : TIMING DIAGRAM LTC2323-16 .............................................................................................53
FIGURE 7-10: BLOCK DIAGRAM DIFFERENTIAL INPUTS..........................................................................54
FIGURE 7-11: CONFIGURATION FPGA SLAVE ADDRESS ........................................................................55
FIGURE 7-12: CONFIGURATION FPGA START AND STOP CONDITION..................................................55
FIGURE 7-13: CONFIGURATION FPGA OUTPUT ACKNOWLEDGE ..........................................................56
FIGURE 7-14: CONFIGURATION FPGA SLAVE ACCESS ...........................................................................56
FIGURE 7-15: TXMC638 WITH HEATSINK ....................................................................................................58
FIGURE 9-1 : FPGA JTAG CONNECTOR X4 ...............................................................................................63
FIGURE 10-1: PIN ASSIGNMENT P14 BACK I/O CONNECTOR TXMC638 ................................................68
FIGURE 10-2: PIN ASSIGNMENT P16 BACK I/O CONNECTOR TXMC638 ................................................69

TXMC638 User Manual Issue 1.0.2 Page 7 of 86
List of Tables
TABLE 2-1 : TECHNICAL SPECIFICATION...................................................................................................10
TABLE 4-1 : ON-BOARD PCIE / PCI DEVICES ............................................................................................12
TABLE 4-2 : PCI CONFIGURATION REGISTERS........................................................................................13
TABLE 4-3 : PCI BAR OVERVIEW ................................................................................................................13
TABLE 4-4 : LOCAL CONFIGURATION REGISTER SPACE.......................................................................14
TABLE 5-1 : INTERRUPT ENABLE REGISTER............................................................................................16
TABLE 5-2 : INTERRUPT STATUS REGISTER............................................................................................16
TABLE 5-3 : USER FPGA CONFIGURATION CONTROL/STATUS REGISTER .........................................17
TABLE 5-4 : USER FPGA CONFIGURATION DATA REGISTER..................................................................18
TABLE 5-5 : ISP CONTROL REGISTER ........................................................................................................19
TABLE 5-6 : ISP CONFIGURATION REGISTER ...........................................................................................19
TABLE 5-7 : ISP COMMAND REGISTER.......................................................................................................20
TABLE 5-8 : ISP STATUS REGISTER ...........................................................................................................20
TABLE 5-9 : TXMC638 SERIAL NUMBER .....................................................................................................21
TABLE 5-10: BCC - FPGA CODE VERSION..................................................................................................21
TABLE 7-1 : TXMC638 FPGA FEATURE OVERVIEW ..................................................................................24
TABLE 7-2 : FPGA BANK USAGE.................................................................................................................24
TABLE 7-3 : MGT CONNECTIONS ...............................................................................................................25
TABLE 7-4 : MULTI GIGABIT TRANSCEIVER REFERENCE CLOCKS ......................................................26
TABLE 7-5 : AVAILABLE FPGA CLOCKS.....................................................................................................37
TABLE 7-6 : FPGA I2C SI514 CONNECTIONS ............................................................................................38
TABLE 7-7 : DIGITAL BACK I/O INTERFACE...............................................................................................40
TABLE 7-8 : DDR3 SDRAM INTERFACE......................................................................................................42
TABLE 7-9 : FPGA SPI-FLASH CONNECTIONS..........................................................................................44
TABLE 7-10: FPGA I2C EEPROM CONNECTIONS ......................................................................................44
TABLE 7-11: ADC CALIBRATION DATA VALUES ........................................................................................45
TABLE 7-12: ADC DATA CODING EXAMPLE ...............................................................................................48
TABLE 7-13: ADC DATA CODING .................................................................................................................48
TABLE 7-14: ADC INTERFACE CONNECTIONS .........................................................................................52
TABLE 7-15: AC COUPLED DIFFERENTIAL INPUTS .................................................................................54
TABLE 7-16: USER FPGA I2C INTERFACE TO CONFIGURATION FPGA..................................................55
TABLE 7-17: TXMC638 SERIAL NUMBER ....................................................................................................55
TABLE 7-18: BOARD-STATUS AND USER LEDS ........................................................................................57
TABLE 9-1 : DIFFERENTIAL INPUT VOLTAGE ...........................................................................................60
TABLE 10-1: PIN ASSIGNMENT FRONT PANEL I/O CONNECTOR X1 ......................................................66
TABLE 10-2: PIN ASSIGNMENT FPGA JTAG HEADER X4 .........................................................................70

TXMC638 User Manual Issue 1.0.2 Page 8 of 86
1 Product Description
The TXMC638 is a standard single-width Switched Mezzanine Card (XMC) compatible module providing a
user configurable Xilinx Kintex-7 FPGA with 24 ADC input channel.
The TXMC638 provides 24 ADC input channels based on the Linear Dual 16-Bit 5Msps Differential
LTC2323-16 ADC. Each of the 24 channels has a resolution of 16bit and can work with up to 5Msps. The
analog input circuit is designed to allow input voltages up to ±2.5 V on each input-pin (results in ±5 V
differential voltage range)
For customer specific I/O extension or inter-board communication, the TXMC638 provides 64 FPGA I/Os on
P14 and 4 FPGA Multi-Gigabit-Transceiver on P16. P14 I/O lines can be configured as 64 single ended
LVCMOS25 or as 32 differential LVDS25 interface.
Additionally the TXMC638 provides three 100 Ohm terminated ac-coupled, differential inputs with wide Input
voltage range.
The User FPGA is connected to a 1GB, 32 bit wide DDR3 SDRAM. The SDRAM-interface uses an internal
Memory Controller of the Kintex-7.
The User FPGA is configured by a serial SPI flash. For full PCIe specification compliance, the XILINX
Tandem Configuration Feature can be used for FPGA configuration. XILINX Tandem Methodologies
“Tandem PROM” should be the favored Methodology. The SPI flash device is in-system programmable. An
in-circuit debugging option is available via a JTAG header for read back and real-time debugging of the
FPGA design by using the Xilinx Vivado Logic Analyzer.
User applications for the TXMC638 with Kintex-7 FPGA can be developed using the Xilinx design software
Vivado Design Suite. A license for the Vivado Design Suite design tool is required.
Figure 1-1 : Block Diagram

TXMC638 User Manual Issue 1.0.2 Page 9 of 86
2 Technical Specification
XMC Interface
Mechanical Interface Switched Mezzanine Card (XMC) Interface confirming to ANSI/VITA
42.0-2008 (Auxiliary Standard)
Standard single-width (149mm x 74mm)
Electrical Interface PCI Express x4 Link (Base Specification 1.1) compliant interface
conforming to ANSI/VITA 42.3-2006 (XMC PCI Express Protocol
Layer Standard)
On-Board Devices
PCI Express Switch PI7C9X2G312GP (Pericom)
PCI Express to PCI Bridge XIO2001 (Texas Instruments)
User configurable FPGA TXMC638-10R: XC7K160T-2FBG676I (Xilinx)
TXMC638-11R: XC7K325T-2FBG676I (Xilinx)
TXMC638-12R: XC7K410T-2FBG676I (Xilinx)
SPI-Flash N25Q128A (Micron) 128 Mbit (contains TXMC638 FPGA Example) or
compatible; +3.3V supply voltage
DDR3 RAM 2 x MT41K256M16HA-125 (Micron) 256 Meg x 32 Bit
Board Configuration FPGA LCMXO2-7000HC (Lattice)
ADC LTC2323IUFD-16 (Linear Technologies)
I/O Interface
Number of analog Input 24 differential 16 bit Inputs
Analog Input Voltage diff. VINMAX (allowed voltage between input pins):
Common Mode Voltage Range :
Input Voltage limit for each pin relative to common ground
±5.0V
±7.5V
±10V
Number of digital Front I/O Three differential Front I/O Inputs with wide Input voltage range.
Differential voltage range: ±200mV up to ±3.6V
Differential Termination = 100 Ohm
Number of digital Back I/O 64 direct FPGA I/O lines to P14 Back I/O connector
- Possible use as single ended or differential I/O
- FPGA I/O Standard: LVCMOS25, LVTTL25 and LVDS_25
I/O Connector Front I/O Samtec – ERF8-049-01-L-D-RA-L
PMC P14 I/O (64 pin Mezzanine Connector)
XMC P16 I/O (114 pin Mezzanine Connector)
Physical Data
Power Requirements Depends on FPGA design
With TXMC638 Board Reference Design / without external load
typical @ +5V VPWR typical @ +12V VPWR
TXMC638-xxR 3.0 A 1.25 A
Temperature Range Operating
Storage
-40°C to +85 °C
-40°C to +85°C

TXMC638 User Manual Issue 1.0.2 Page 10 of 86
MTBF TXMC638-xxR: 269000 h
MTBF values shown are based on calculation according to MIL-HDBK-217F and
MIL-HDBK-217F Notice 2; Environment: GB20°C.
The MTBF calculation is based on component FIT rates provided by the component
suppliers. If FIT rates are not available, MIL-HDBK-217F and MIL-HDBK-217F Notice 2
formulas are used for FIT rate calculation.
Humidity 5 – 95 % non-condensing
Weight TXMC638-xxR: 133g
Table 2-1 : Technical Specification

TXMC638 User Manual Issue 1.0.2 Page 11 of 86
3 Handling and Operation Instruction
ESD Protection3.1
The TXMC638 is sensitive to static electricity. Packing, unpacking
and all other handling of the TXMC638 has to be done in an ESD/EOS
protected Area.
Thermal Considerations3.2
Forced air cooling is recommended during operation. Without forced
air cooling, damage to the device can occur.
Please also note chapter “Thermal Management”.
Assembling Hints3.3
When disassembling the TXMC638 from carrier board please keep
the mechanical stress as low as possible.

TXMC638 User Manual Issue 1.0.2 Page 12 of 86
4 PCI Device Topology
The TXMC638 consists of two FPGAs. Both FPGA are designed as a PCIe / PCI endpoint devices. One
FPGA is the User FPGA (Kintex-7) which could be programmed with user defined FPGA code. The second
FPGA takes control of on-board hardware functions of TXMC638 and also the configuration control of the
User FPGA. This second FPGA is the BCC (Board Configuration Controller).
The BCC PCI endpoint is connected via a PCI-to-PCIe Bridge to the second x1 Downstream Port of the
PCIe Switch (Pericom PI7C9X2G312GP). The User FPGA (Kintex-7 PCIe endpoint) is directly connected to
the first x4 Downstream Port.
The x4 Upstream Port of the PCIe Switch is connected to the XMC P15 Connector, communicating with the
host system.
P15
XC7KxxxT-2
PCIe-to-PCI Bridge
x4 PCIe
x1 PCIex4 PCIe
PI7C9X2G312GP
XIO2001
LCMXO2
User FPGA
Board Configuration
Controller (FPGA)
Figure 4-1 : PCIe/PCI Device Topology
Device Vendor ID Device ID Class
Code
Description (as shown by lspci)
PI7C9X2G312GP
0x12D8
(Pericom)
0x2312 0x060400 PCI bridge:
0x04h to indicate device as PCI-to-PCI Bridge
0x06h to indicate device as Bridge device
XIO2001
0x104C
(Texas
Instruments)
0x8240 0x060400 PCI bridge: Texas Instruments
0x04h to indicate device as PCI-to-PCI Bridge
0x06h to indicate device as Bridge device
XC7KxxxT-2
user defined Device identification for the User
programmable FPGA is defined by user. The
data will be created with the Xilinx Vivado “7
Series Integrated Block for PCI Express” IP
generator.
BCC
LCMXO2
0x1498
(TEWS)
0x927E 0x068000 Bridge Device: TEWS Technologies GmbH
Device 927E
(TXMC638).
Table 4-1 : On-Board PCIe / PCI Devices

TXMC638 User Manual Issue 1.0.2 Page 13 of 86
User FPGA (Kintex-7)4.1
The User FPGA address map depends on the user application and is not part of this target specification.
BCC (Board Configuration Controller) FPGA4.2
4.2.1 PCI Configuration Registers (PCR)
PCI CFG
Register
Address
Write ‘0’ to all unused (Reserved) bits PCI
writeable
Initial Values
(Hex Values)
31 24 23 16 15 8 7 0
0x00 Device ID Vendor ID N 927E 1498
0x04 Status Command Y 0480 000B
0x08 Class Code Revision ID N 068000 01
0x0C BIST Header Type PCI Latency
Timer
Cache Line
Size
Y[7:0] 00 00 00 08
0x10 PCI Base Address 0 for Local Address Space 0 Y FFFFFF00
0x14 PCI Base Address 1 for Local Address Space 1 Y FFFFFF00
0x18 PCI Base Address 2 for Local Address Space 2 N 00000000
0x1C PCI Base Address 3 for Local Address Space 3 N 00000000
0x20 PCI Base Address 4 for Local Address Space 4 N 00000000
0x24 PCI Base Address 5 for Local Address Space 5 N 00000000
0x28 PCI CardBus Information Structure Pointer N 00000000
0x2C Subsystem ID Subsystem Vendor ID N 927E 1498
0x30 PCI Base Address for Local Expansion ROM Y 00000000
0x34 Reserved New Cap. Ptr. N 000000 40
0x38 Reserved N 00000000
0x3C Max_Lat Min_Gnt Interrupt Pin Interrupt Line Y[7:0] 00 00 01 00
Table 4-2 : PCI Configuration Registers
4.2.2 PCI BAR Overview
BAR Size
(Byte) Space Prefetch
Port
Width
(Bit)
Endian
Mode Description
0 256 MEM No 32 Little Local Configuration Register Space
1 256 MEM No 32 Little In-System Programming Data Space
Table 4-3 : PCI BAR Overview

TXMC638 User Manual Issue 1.0.2 Page 14 of 86
4.2.2.1 Local Configuration Register Space
Offset to PCI
Base Address Register Name Size (Bit)
0x00 – 0xBF Reserved -
0xC0 Interrupt Enable Register 32
0xC4 Interrupt Status Register 32
0xC8 Reserved -
0xCC Reserved -
0xD0 User FPGA Configuration Control/Status Register 32
0xD4 User FPGA Configuration Data Register (Slave SelectMAP) 32
0xD8 Reserved -
0xDC Reserved -
0xE0 ISP Control Register (SPI) 32
0xE4 ISP Configuration Register (SPI) 32
0xE8 ISP Command Register (SPI) 32
0xEC ISP Status Register (SPI) 32
0xF0 Reserved -
0xF4 Reserved -
0xF8 TXMC638 Serial Number 32
0xFC BCC Code Version 32
Table 4-4 : Local Configuration Register Space

TXMC638 User Manual Issue 1.0.2 Page 15 of 86
4.2.2.2 In-System Programming Data Space
The In-System Programming (ISP) Data Space is used for passing user FPGA configuration data for in-
system programming of the User FPGA SPI Flash.
For ISP write/program instructions, the data must be written (zero-based) to the ISP Data Space before the
instruction is started. The data must cover a complete SPI Flash memory page.
For ISP read instructions, the data can be read (zero-based) from the ISP Data Space after the instruction is
done. The data is passed for a complete SPI Flash memory page.
The ISP Data Space size is 256 byte, covering an SPI Flash Memory Page. All supported SPI Flash read
and write instructions are page-based.
Control and status register for ISP are located in the Local Configuration Register Space. The data register
for direct FPGA ISP is also located in the Local Configuration Register Space.

TXMC638 User Manual Issue 1.0.2 Page 16 of 86
5 Register Description
User FPGA (Kintex-7)5.1
The FPGA register description depends on the user application and is not part of this specification.
Board Configuration Controller (BCC - FPGA)5.2
5.2.1 Interrupt Enable Register - 0xC0
Bit Symbol Description Access Reset
Value
31:2 Reserved 0
1 ISP_INS_IE
ISP SPI Instruction Done Event Interrupt Enable
0: Interrupt Disabled
1: Interrupt Enabled
While disabled, the corresponding bit in the Interrupt
Status Register is ‘0’.
Disabling interrupts does not affect the interrupt
source.
R/W 0
0ISP_DAT_IE
ISP SPI Page Data Request Event Interrupt Enable
0: Interrupt Disabled
1: Interrupt Enabled
While disabled, the corresponding bit in the Interrupt
Status Register is ‘0’.
Disabling interrupts does not affect the interrupt
source.
R/W 0
Table 5-1 : Interrupt Enable Register
5.2.2 Interrupt Status Register - 0xC4
Bit Symbol Description Access Reset
Value
31:2 Reserved 0
1ISP_INS_IS
ISP SPI Instruction Done Event Interrupt Status
When set, the PCI INTA# interrupt is asserted.
The Interrupt is cleared by writing a ‘1’.
0: Interrupt not active or disabled
1: Interrupt active and enabled
R/C 0
0 ISP_DAT_IS
ISP SPI Page Data Done Event Interrupt Status
When set, the PCI INTA# interrupt is asserted.
The Interrupt is cleared by writing a ‘1’.
0: Interrupt not active or disabled
1: Interrupt active and enabled
R/C 0
Table 5-2 : Interrupt Status Register

TXMC638 User Manual Issue 1.0.2 Page 17 of 86
5.2.3 User FPGA Configuration Control/Status Register - 0xD0
Bit Symbol Description Access Reset
Value
31:5 Reserved 0
4 K7_LINK_ENA 1: Kintex-7 to PCIe-Switch LINK is enabled
0: Kintex-7 to PCIe-Switch LINK is disabled R/W 1
3 FP_INIT_STAT
User FPGA INIT_B Pin Status
0: FPGA INIT_B Pin Level is Low (active)
1: FPGA INIT_B Pin Level is High (not active)
Rx
2 FP_DONE_STAT
User FPGA DONE Pin Status
The FPGA Done pin is high in case of successful
FPGA configuration.
0: FPGA DONE Pin Level is Low (not active)
1: FPGA DONE Pin Level is High (active)
Rx
1FP_RE_CFG
After power-up the FPGA automatically configures
from the on-board SPI Flash in ‘Master Serial /
SPI’ mode.
User FPGA Re-Configuration
1: Set all FPGA I/O pins to High-Z and prepare a
User FPGA Re-Configuration
1Æ0: Start User FPGA Re-Configuration
R/W 0
0FP_CFG_MD
Set User FPGA Configuration Mode
0: Master Serial / SPI
1: Slave SelectMap (Parallel)
After power-up the User FPGA automatically
configures from the on-board SPI Flash in ‘Master
Serial / SPI’ mode.
R/W 0
Table 5-3 : User FPGA Configuration Control/Status Register

TXMC638 User Manual Issue 1.0.2 Page 18 of 86
5.2.4 User FPGA Configuration Data Register - 0xD4
Bit Symbol Description Access Reset
Value
31:0 ISP_FP_DAT
ISP Select Map Write Data
Write Data Register for direct Slave Select Map
FPGA programming mode
Must be written with 32-bit FPGA programming
data until the FPGA Done pin goes high (after the
actual programming data, writing some dummy
data may be required).
w-
Table 5-4 : User FPGA Configuration Data Register
The User FPGA Configuration Data Register is used to write data within the User FPGA Slave Select Map
Configuration directly to the User FPGA.

TXMC638 User Manual Issue 1.0.2 Page 19 of 86
5.2.5 ISP Control Register - 0xE0
Bit Symbol Description Access Reset
Value
31:1 Reserved 0
0 ISP_EN
ISP Mode Enable
0: Disable ISP Mode
1: Enable ISP Mode
This bit controls the BCC interface between BCC,
SPI-Flash and the User FPGA (Kintex-7).
When set, the BCC is both SPI Flash Master and
FPGA Configuration Interface Master.
Must be set to 1 for direct Slave Select Map mode or
SPI Flash programming.
Must be set to 0 when the User FPGA should
configure from the SPI Flash (e.g. after SPI Flash
programming) in ‘Master Serial / SPI’ mode.
Note, that for ISP Direct FPGA Programming, the
FPGA must first be set to Slave Select Map
configuration mode.
R/W 0
Table 5-5 : ISP Control Register
5.2.6 ISP Configuration Register - 0xE4
Bit Symbol Description Access Reset
Value
31:24
ISP_SPI_ADD
SPI Flash Address A7-A0 w 0x00
23:16 SPI Flash Address A15-A8 w 0x00
15:8 SPI Flash Address A23-A16 w 0x00
7:0 ISP_SPI_INS
SPI Flash Instruction Code
Supported Instructions:
0x02 – Page Program
0x20 – Sector Erase
0xC7 – Chip Erase
0x03 – Read Data
w0x00
Table 5-6 : ISP Configuration Register

TXMC638 User Manual Issue 1.0.2 Page 20 of 86
5.2.7 ISP Command Register - 0xE8
Bit Symbol Description Access Reset
Value
31:2 Reserved - 0
1 ISP_SPI_RST_CMD
ISP SPI Reset Command Bit
Writing a ‘1’ sets the Instruction Busy Bit in the
ISP Status Register (if not already set).
Breaks any ISP SPI instruction in progress and
resets the ISP SPI logic.
Check the Instruction Busy Bit in the ISP Status
Register for reset done status.
Always read as ‘0’.
R/W 0
0 ISP_SPI_INS_CMD
ISP SPI Start Instruction Command Bit
Writing a ‘1’ sets the SPI Instruction Busy Bit in
the ISP Status Register and starts the configured
SPI instruction.
Ignored (lost) while the Instruction Busy Bit is set
in the ISP Status Register.
Always read as ‘0’.
R/W 0
Table 5-7 : ISP Command Register
5.2.8 ISP Status Register - 0xEC
Bit Symbol Description Access Reset
Value
31:2 Reserved - 0x00_0000
1ISP_SPI_
INS_BSY
ISP SPI Instruction Busy Status
Set & Cleared automatically by HW.
Includes SPI Flash internal program/erase times.
When clear again after being set, a new ISP SPI
instruction may be started.
Capable of generating an event based interrupt.
0: No ISP SPI Instruction in Progress
1: ISP SPI Instruction in Progress
R0
0ISP_SPI_
DAT_BSY
ISP SPI Data Transfer Busy Status
Set & Cleared automatically by HW.
Does not include SPI Flash internal program/erase
times.
When clear again after being set, new SPI Flash page
data may be written to the ISP Data Space (in program
mode) or SPI Flash page data is available in the ISP
data space (in read mode).
Capable of generating an event based interrupt.
0: No ISP SPI Data Transfer in Progress
1: ISP SPI Data Transfer in Progress
R0
Table 5-8 : ISP Status Register