Texas Instruments BQ25155 User manual

BQ25155 I2C Controlled 1-Cell 500-mA Linear Battery Charger With 10-nA Ship Mode,
Power Path With Regulated System (PMID) Voltage, ADC, and LDO
1 Features
• Linear battery charger with 1.25-mA to 500-mA
fast charge current range
– 0.5% Accurate I2C programmable battery
regulation voltage ranging from 3.6 V to 4.6 V in
10-mV steps
– Configurable termination current supporting
down to 0.5 mA
– 20-V Tolerant input with typical 3.4-V to 5.5-V
input voltage operating range
– Programmable thermal charging profile, fully
configurable hot, warm, cool and cold
thresholds
• Power Path management for powering system and
charging battery
– I2C Programmable regulated system voltage
(PMID) ranging from 4.4V to 4.9V in addition to
battery voltage tracking and Input pass-though
options
– Dynamic power path management optimizes
charging from weak adapters
– Advanced I2C control allows host to disconnect
the battery or adapter as needed
• I2C Configurable load switch or up to 150-mA LDO
output
– Programmable range from 0.6 V to 3.7 V in
100-mV steps
• Ultra low Iddq for extended battery life
– 10-nA Ship mode battery Iq
– 400-nA Iq While powering the system (PMID
and VDD on)
• One push-button wake-up and reset input with
adjustable timers
– Supports system power cycle and HW reset
• 16-Bit ADC
– Monitoring of charge current, battery thermistor
and battery, input and system (PMID) voltages
– General purpose ADC input
• Always on 1.8-V VDD LDO supporting loads up to
10 mA
• Safety-Related Certifications
– TUV IEC 62368 Certification
• 20-Pin 2-mm x 1.6-mm CSP package
• 12-mm2 Total solution size
2 Applications
• Headsets, earbuds and hearing aids
• Smart watches and smart trackers
• Wearable fitness and activity monitors
• Blood glucose monitors
3 Description
The BQ25155 is a highly integrated battery charge
management IC that integrates the most common
functions for wearable, portable and small medical
devices, namely a charger, a regulated output voltage
rail for system power, ADC for battery and system
monitoring, a LDO, and push-button controller.
The BQ25155 IC integrates a linear charger with
Power Path that enables quick and accurate charging
for small batteries while providing a regulated voltage
to the system. The regulated system voltage (PMID)
output may be configured through I2C based on the
recommended operating condition of downstream IC's
and system loads for optimal system operation.
Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
BQ25155 DSBGA (20) 2.00 mm x 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
BQ25155
VINLS
PMID
LS/LDO
VDD
BAT
TS +
±
NTC
GND
IN
VIO
Host
USB
I2C Bus
<150mA
Load
<10mA
Load
System
ADCIN
MR
PG
INT
LP
CE
C4
C5
C3
C2
C1
Simplified Schematic
BQ25155
SLUSDO1B – JUNE 2019 – REVISED AUGUST 2023
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 4
6 Device Key Default Settings........................................... 5
7 Pin Configuration and Functions...................................6
8 Specifications.................................................................. 8
8.1 Absolute Maximum Ratings........................................ 8
8.2 ESD Ratings............................................................... 8
8.3 Recommended Operating Conditions.........................8
8.4 Thermal Information....................................................8
8.5 Electrical Characteristics.............................................9
8.6 Timing Requirements................................................ 12
8.7 Typical Characteristics..............................................14
9 Detailed Description......................................................17
9.1 Overview................................................................... 17
9.2 Functional Block Diagram......................................... 17
9.3 Feature Description...................................................18
9.4 Device Functional Modes..........................................37
9.5 Register Map.............................................................41
10 Application and Implementation................................ 96
10.1 Application Information........................................... 96
10.2 Typical Application.................................................. 96
11 Power Supply Recommendations............................102
12 Layout.........................................................................103
12.1 Layout Guidelines................................................. 103
12.2 Layout Example.................................................... 103
13 Device and Documentation Support........................104
13.1 Device Support..................................................... 104
13.2 Documentation Support........................................ 104
13.3 Receiving Notification of Documentation Updates104
13.4 Support Resources............................................... 104
13.5 Electrostatic Discharge Caution............................104
13.6 Trademarks........................................................... 104
13.7 Glossary................................................................104
14 Mechanical, Packaging, and Orderable
Information.................................................................. 105
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2019) to Revision B (August 2023) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Added Safety-Related Certifications to Features............................................................................................... 1
• Added Device Key Default Settings Table.......................................................................................................... 5
• Added clarification to LP pin description.............................................................................................................6
• Added clarification to ADCIN pin description...................................................................................................... 6
• Added clarification to LS/LDO pin description.................................................................................................... 6
• Changed maximum IPMID in Recommended Operating Conditions....................................................................8
• Changed maximum RON(BAT-PMID) in Electrical Characteristics.......................................................................... 9
• Added footnote in Electrical Characteristics....................................................................................................... 9
• Changed tHW_RESET_WD test conditions and MAX value from 15s to 14s in Timing Requirements.................. 12
• Changed tRESET_WARN parameter..................................................................................................................... 12
• Changed tHW_RESET parameter.........................................................................................................................12
• Changed Input Voltage Based Dynamic Power Management (VINDPM) and Dynamic Power Path
Management (DPPM)section to simplify description........................................................................................ 21
• Added more details to descriptions in ADC Operation When VIN Present.......................................................23
• Changed Load Switch/LDO Output and Control description............................................................................ 25
• Added clarification on LDO voltage programmability........................................................................................25
• Changed tHW_RESET_WARN to tRESET_WARN in Section 9.3.8.2 .......................................................................... 28
• Changed VIN presence to valid VIN presence in Section 9.3.8.2 ................................................................... 28
• Added clarification to TS biasing operation...................................................................................................... 32
• Changed from as well while the VIN input is valid to while the VIN input is valid in Section 9.4.1 .................. 37
• Added link to BQ25155 Setup Guide tool......................................................................................................... 41
• Changed description of IBAT_OCP_ILIM 2b10 setting to "Disable" to describe correct behavior....................41
• Changed clatification to TS_EN bit functionality............................................................................................... 41
• Changed registers 0x42 to 0x4F from R/W-X to R-X in Section 9.5.1 .............................................................41
• Changed Figure 10-3 .......................................................................................................................................98
• Added TS Biasing Figure..................................................................................................................................98
• Added VINLS bypass capacitor layout guideline............................................................................................103
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Changes from Revision * (June 2019) to Revision A (July 2019) Page
• Changed from Advance Information to Production Data ...................................................................................1
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5 Description (continued)
The device supports charge current up to 500 mA and supports termination current down to 0.5 mA for
maximum charge. The battery is charged using a standard Li-Ion charge profile with three phases: pre-charge,
constant current and constant voltage regulation.
The device integrates advanced power path management and control that allows the device to provide power
to the system while charging the battery even with poor adapters. The host may also control the power path
through I2C allowing it to disconnect the input adapter and/or battery without physically removing them. The
single push-button input eliminates the need of a separate button controller IC reducing the total solution
footprint. The push-button input can be used for wake functions or to reset the system.A 16-bit ADC enables
accurate battery voltage monitoring and can be used to enable a low Iq gauging to monitor battery health.
It can also be used to measure the battery temperature using a thermistor connected to the TS pin as well
as external system signals through the ADCIN pin. The low quiescent current during operation and shutdown
enables maximum battery life. The input current limit, charge current, LDO output voltage, and other parameters
are programmable through the I2C interface making the BQ25155 a very flexible charging solution. A voltage-
based JEITA compatible (or standard HOT/COLD) battery pack thermistor monitoring input (TS) is included that
monitors battery temperature and automatically changes charge parameters to prevent the battery from charging
outside of its safe temperature range. The temperature thresholds are also programable through I2C allowing the
host to customize the thermal charging profile. The charger is optimized for 5-V USB input, with 20-V absolute
maximum tolerance to withstand line transients. The device also integrates a linear regulator to provide a quiet
rail for radios or processors and can be independently sourced and controlled through I2C.
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6 Device Key Default Settings
DEFAULT SETTING BQ25150 BQ25155
Fast Charge Current (ICHARGE) 10 mA 10 mA
Pre-Charge Current (IPRECHARGE) 2.5 mA 2.5 mA
Termination Current (ITERM) 10% of ICHARGE 10%of ICHARGE
Input Current Ljmit (IILIM) 100 mA 500 mA
VIN DPM Enabled Disabled
LDO Output Voltage (VLDO) 1.8 V 1.8 V
Ship Mode Wake Timer 2 seconds 0.125 seconds
DEVICE_ID 0x20h 0x35h
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7 Pin Configuration and Functions
IN PMID BAT GND
/PG PMID BAT TS
/MR /CE NC ADCIN
VDD /INT /LP LSLDO
VIO SDA SCL VINLS
A
B
C
D
E
1 2 3 4
Figure 7-1. YFP Package 20-Pin DSBGA Top View
Table 7-1. Pin Functions
PIN I/O DESCRIPTION
NAME NO.
IN A1 I DC Input Power Supply. IN is connected to the external DC supply. Bypass IN to GND with
at least 1-µF of capacitance using a ceramic capacitor.
PMID A2, B2 I/O
Regulated System Output. Connect 22-µF capacitor from PMID to GND as close to the
PMID and GND pins as possible. If operating in VIN Pass-Through Mode (PMID_REG =
111) a lower capacitor value may be used (at least 3-µF of ceramic capacitance with DC
bias de-rating). Note: Shorting PMID to IN pin is not recommended as it may cause large
discharge current from battery to IN if IN pin is not truly floating.
GND A4 PWR Ground connection. Connect to the ground plane of the circuit.
VDD D1 O Digital supply LDO. Connect a 2.2-µF from this pin to ground. A 4.7-µF capacitor to ground
recommended if loaded externally.
CE C2 I
Charge Enable. Drive CE low or leave disconnected to enable charging when VIN is valid.
Drive CE high to disable charge when VIN is present. CE is pulled low internally with 900-kΩ
resistor. CE has no effect when VIN is not present.
SCL E3 I/O I2C Interface Clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA E2 I I2C Interface Data. Connect SDA to the logic rail through a 10-kΩ resistor.
LP D3 I
Low Power Mode Enable. Drive this pin low to set the device in low power mode when
powered by the battery. This pin must be driven high to allow I2C communication when VIN
is not present. LP is pulled low internally with 900-kΩ resistor. This pin has no effect when
VIN is present.
INT D2 O
INT is an open-drain output that signals fault interrupts. When a fault occurs, a 128-µs pulse
is sent out as an interrupt for the host. INT is enabled/disabled using the MASK_INT bit in
the control register.
ADCIN C4 I Input Channel to the ADC. Maximum ADC range 1.2 V. If not used it may be left floating or
connect to ground.
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Table 7-1. Pin Functions (continued)
PIN I/O DESCRIPTION
NAME NO.
MR C1 I
Manual Reset Input. MR is a general purpose input that must be held low for greater than
tHWRESET to go into HW Reset and power cycle the output rails. If MR is also used to wake
up the device out of Ship Mode when pressed for at least tWAKE1. MR has in internal 125-kΩ
pull-up resistor to BAT.
LS/LDO D4 O
Load Switch or LDO output. Connect 2.2 µF of ceramic capacitance to this pin to assure
stability. Be sure to account for capacitance bias voltage derating when selecting the
capacitor. If LDO is not used, short to VINLS
VINLS E4 I Input to the Load Switch / LDO output. Connect at least 1 µF of ceramic capacitance from
this pin to ground.
BAT A3, B3 I/O Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with
at least 1 µF of ceramic capacitance.
TS B4 I Battery Pack NTC Monitor. Connect TS to a 10-kΩ NTC thermistor in parallel to a 10-kΩ
resistor. If TS function is not to be used connect a 5-kΩ resistor from TS to ground.
PG B1 O
Open-drain Power Good status indication output. PG is pulled to GND when VIN is above
VBAT+ VSLP and less than VOVP. PG is high-impedance when the input power is not within
specified limits. Connect PG to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor,
or use with an LED for visual indication. PG can also be configured through I2C as a
push-button level shifted output ( MR), where the output of the PG pin reflects the status of
the MR input, but pulled up to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor.
The PG pin can also be configured as a general purpose open drain output.
VIO E1 I
System IO supply. Connect to system IO supply to allow level shifting of input signals (SDA,
SCL, LP and CE) to the device internal digital domain. Connect to VDD when external IO
supply is not available.
NC C3 I No Connect. Connect to ground if possible for better thermal dissipation or leave floating. Do
not connect to a any voltage source or signal to avoid higher quiescent current.
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage
IN –0.3 20 V
TS, ADCIN, VDD, NC –0.3 1.95 V
All other pins –0.3 5.5 V
Current
IN 0 800 mA
BAT, PMID –0.5 1.5 A
INT, ADCIN, PG 0 10 mA
Junction temperature, TJ–40 125 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1) ±2000
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VBAT Battery voltage range 2.4 4.6 V
VIN Input voltage range 3.15 5.25(1) V
VINLS LDO input voltage range 2.2 5.25(1) V
VIO IO supply voltage range 1.2 3.6 V
VADCIN ADC input voltage range 0 1.2 V
ILDO LDO output current 0 100 mA
IPMID PMID output current 0 1.5 A
TAOperating free-air temperature range –40 85 °C
(1) Based on minimum VOVP value. 5.5V under typical conditions
8.4 Thermal Information
THERMAL METRIC(1)
BQ25155
UNITYFP (DSBGA)
20-PIN
RθJA Junction-to-ambient thermal resistance (2) 36.1 °C/W
RθJA Junction-to-ambient thermal resistance 74.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.5 °C/W
RθJB Junction-to-board thermal resistance 17.6 °C/W
ΨJT Junction-to-top characterization parameter 0.3 °C/W
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8.4 Thermal Information (continued)
THERMAL METRIC(1)
BQ25155
UNITYFP (DSBGA)
20-PIN
ΨJB Junction-to-board characterization parameter 17.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Measured in BQ25155EVM board.
8.5 Electrical Characteristics
VIN = 5V, VBAT = 3.6V. -40°C < TJ < 125°C unless otherwise noted. Typical data at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CURRENTS
IIN Input supply current
PMID_MODE = 01, VIN = 5V, VBAT = 3.6V 500 µA
0°C <TJ < 85°C , VIN = 5V, VBAT = 3.6V
Charge Disabled 2 mA
IBAT_SHIP Battery Discharge Current in Ship Mode 0°C <TJ < 60°C ,VIN = 0V , VBAT = 3.6V 10 150 nA
IBAT_LP
Battery Quiescent Current in Low-power
Mode
0°C <TJ < 60°C ,VIN = 0V , VBAT = 3.6V,
LDO Disabled 0.46 1.2 µA
0°C <TJ < 60°C ,VIN = 0V , VBAT = 3.6V,
LDO Enabled 1.7 3.5 µA
IBAT_ACTI
VE
Battery Quiescent Current in Active Mode
0°C <TJ < 85°C ,VIN = 0V , VBAT = 3.6V,
LDO Disabled 18 25 µA
0°C <TJ < 85°C ,VIN = 0V , VBAT = 3.6V,
LDO Enabled 21 27 µA
POWER PATH MANAGEMENT AND INPUT CURRENT LIMIT
VPMID_RE
G
Default System (PMID) Regulation
Voltage 4.5 V
VPMID_RE
G_ACC
System Regulation Voltage Accuracy
VIN = 5V, VPMID_REG = 4.5V. IPMID =
100mA, TJ = 25°C -1 1 %
VIN = 5V, VPMID_REG = 4.5V. IPMID = 0-
500mA –3 3 %
RON(IN-
PMID)
Input FET ON resistance IILIM = 500mA (ILIM = 110), VIN = 5V, IIN =
150mA 280 520 mΩ
VBSUP1 Enter supplements mode threshold VBAT > VBATUVLO, DPPM enabled or
Charge disabled
VPMID <
VBAT –
40mV
mV
VBSUP2 Exit supplements mode threshold VBAT > VBATUVLO, DPPM enabled or
Charge disabled
VPMID <
VBAT –
20mV
mV
IILIM Input Current Limit
Programmable Range 50 600 mA
IILIM = 50mA 45 50 mA
IILIM = 100mA 90 100 mA
IILIM = 150mA 135 150 mA
IILIM = 500mA 450 500 mA
VIN_DPM
Input DPM voltage threshold where
current in reduced Programmable Range 4.2 4.9 V
Accuracy –3 3 %
BATTERY CHARGER
VDPPM
PMID voltage threshold when charge
current is reduced VPMID - VBAT 200 mV
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8.5 Electrical Characteristics (continued)
VIN = 5V, VBAT = 3.6V. -40°C < TJ < 125°C unless otherwise noted. Typical data at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RON(BAT-
PMID)
Battery Discharge FET On Resistance VBAT = 4.35V, IBAT = 100mA 100 135 mΩ
VBATREG
Charge Voltage Programmable charge voltage range 3.6 4.6 V
Voltage Regulation Accuracy 0.5 0.5 %
ICHARGE
Fast Charge Programmable Current
Range VLOWV < VBAT < VBATREG 1.25 500 mA
Fast Charge Current Accuracy TJ = 25°C, ICHARGE > 5mA –5 5 %
IPRECHAR
GE
Precharge current Precharge current programmable range 1.25 77.5 mA
Precharge Current Accuracy -40°C < TJ < 85°C –10 10 %
ITERM
Termination Charge Current Termination Current Programmable
Range 1 31 %
Accuracy
TJ = 25°C, ITERM = 10% ICHARGE, ICHARGE
= 100mA –5(1) 5(1) %
-10°C < TJ < 85°C, ITERM = 10% ICHARGE,
ICHARGE = 100mA –10(1) 10(1) %
VLOWV
Programmable voltage threshold for pre-
charge to fast charge transitions VBAT rising. Programmable Range 2.8 3 V
VSHORT
Battery voltage threshold for short
detection VBAT falling, VIN = 5V 2.41 2.54 2.67 V
ISHORT Charge Current in Battery Short Condition VBAT < VSHORT
IPRECHAR
GE
mA
VRCH Recharge Threshold voltage
VBAT falling, VBATREG = 4.2V, VRCH =
140mV setting 140 mV
VBAT falling, VBATREG = 4.2V, VRCH =
200mV setting 200 mV
RPMID_PD PMID pull-down resistance VPMID = 3.6V 25 Ω
VDD
VDD VDD LDO output voltage VBAT = 3.6V, VIN = 0V, 0 < ILOAD_VDD <
10mA 1.8 V
ILOAD_VD
D
Maximum VDD External load capability VPMID > 3V 10 mA
LS/LDO
VINLS
Input voltage range for Load switch Mode 0.8 5.5 V
Input voltage range for LDO Mode
2.2 or
VLDO +
500mV
5.5 V
VLDO
LDO programmable output voltage range 0.6 3.7 V
LDO output accuracy TJ = 25°C –2 2 %
VLDO = 1.8V, VINLS =3.6V. ILOAD = 1mA –3 3 %
ΔVOUT/
ΔIOUT
DC Load Regulation 0°C < TJ < 85°C, 1 mA < IOUT < 150mA,
VLDO = 1.8V 1.2 %
ΔVOUT/
ΔVIN
DC Line Regulation 0°C < TJ < 85°C, Over VINLS range, IOUT =
100mA, VLDO = 1.8V 0.5 %
RDOSN_LD
O
Switch On resistance VINLS = 3.6V 250 450 mΩ
RDSCH_LS
LDO
Discharge FET On-resistance for LS VINLS = 3.6V 40 Ω
IOCL_LDO Output Current Limit VLS/LDO = 0V 200 300 mA
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