Texas Instruments BQ25157 User manual

BQ25157 I2C Controlled 1-Cell 500-mA Linear Battery Charger With 10-nA Ship Mode,
Power Path With Regulated System (PMID) Voltage, ADC, LDO and 6.2-V OVP
1 Features
• Linear battery charger with 1.25-mA to 500-mA
fast charge current range
– 0.5% Accurate I2C programmable battery
regulation voltage ranging from 3.6 V to 4.6 V in
10-mV steps
– Configurable termination current supporting
down to 0.5 mA
– 20-V Tolerant input with typical 3.4-V to 6.2-V
input voltage operating range
– Programmable thermal charging profile, fully
configurable hot, warm, cool and cold
thresholds
• Power Path management for powering system and
charging battery
– Dynamic power path management optimizes
charging from weak adapters
– Advanced I2C control allows host to disconnect
the battery or adapter as needed
• I2C Configurable load switch or up to 150-mA LDO
output
– Programmable range from 0.6 V to 3.7 V in
100-mV steps
• Ultra low Iddq for extended battery life
– 10-nA Ship mode battery Iq
– 400-nA Iq While powering the system (PMID
and VDD on)
• One push-button wake-up and reset input with
adjustable timers
– Supports system power cycle and HW reset
• 16-Bit ADC
– Monitoring of charge current, battery thermistor
and battery, input and system (PMID) voltages
– General purpose ADC input
• Always on 1.8-V VDD LDO supporting loads up to
10 mA
• 20-Pin 2-mm x 1.6-mm CSP package
• 12-mm2 Total solution size
2 Applications
•Headsets, earbuds and hearing aids
•Smart watches and smart trackers
•Wearable fitness and activity monitors
•Blood glucose monitors
3 Description
The BQ25157 is a highly integrated battery charge
management IC that integrates the most common
functions for wearable, portable and small medical
devices, namely a charger, a regulated output voltage
rail for system power, ADC for battery and system
monitoring, a LDO, and push-button controller. The
BQ25157 has the Input Supply Over Voltage
Threshold (VOVP) threshold set to 6.2 V.
The BQ25157 IC integrates a linear charger with
Power Path that enables quick and accurate charging
for small batteries while providing a regulated voltage
to the system. The regulated system voltage (PMID)
output may be configured through I2C based on the
recommended operating condition of downstream IC's
and system loads for optimal system operation.
Device Information (1)
PART NUMBER PACKAGE BODY SIZE (NOM)
BQ25157 DSBGA (20) 2.00 mm x 1.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
BQ25157
VINLS
PMID
LS/LDO
VDD
BAT
TS +
±
NTC
GND
IN
VIO
Host
USB
I2C Bus
<150mA
Load
<10mA
Load
System
ADCIN
MR
PG
INT
LP
CE
C4
C5
C3
C2
C1
Simplified Schematic
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Device Key Default Settings........................................... 4
7 Pin Configuration and Functions...................................5
8 Specifications.................................................................. 7
8.1 Absolute Maximum Ratings........................................ 7
8.2 ESD Ratings............................................................... 7
8.3 Recommended Operating Conditions.........................7
8.4 Thermal Information....................................................7
8.5 Electrical Characteristics.............................................8
8.6 Timing Requirements................................................ 11
8.7 Typical Characteristics..............................................13
9 Detailed Description......................................................15
9.1 Overview................................................................... 15
9.2 Functional Block Diagram......................................... 15
9.3 Feature Description...................................................16
9.4 Device Functional Modes..........................................35
9.5 Register Map.............................................................39
10 Application and Implementation................................ 94
10.1 Application Information........................................... 94
10.2 Typical Application.................................................. 94
11 Power Supply Recommendations............................100
12 Layout.........................................................................101
12.1 Layout Guidelines................................................. 101
12.2 Layout Example.................................................... 101
13 Device and Documentation Support........................102
13.1 Device Support..................................................... 102
13.2 Documentation Support........................................ 102
13.3 Receiving Notification of Documentation Updates102
13.4 Support Resources............................................... 102
13.5 Electrostatic Discharge Caution............................102
13.6 Trademarks...........................................................102
13.7 Glossary................................................................102
14 Mechanical, Packaging, and Orderable
Information.................................................................. 103
4 Revision History
DATE REVISION NOTES
December 2020 * Initial release
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5 Description (continued)
The device supports charge current up to 500 mA and supports termination current down to 0.5 mA for
maximum charge. The battery is charged using a standard Li-Ion charge profile with three phases: pre-charge,
constant current and constant voltage regulation.
The device integrates advanced power path management and control that allows the device to provide power to
the system while charging the battery even with poor adapters. The host may also control the power path
through I2C allowing it to disconnect the input adapter and/or battery without physically removing them. The
single push-button input eliminates the need of a separate button controller IC reducing the total solution
footprint. The push-button input can be used for wake functions or to reset the system.A 16-bit ADC enables
accurate battery voltage monitoring and can be used to enable a low Iq gauging to monitor battery health. It can
also be used to measure the battery temperature using a thermistor connected to the TS pin as well as external
system signals through the ADCIN pin. The low quiescent current during operation and shutdown enables
maximum battery life. The input current limit, charge current, LDO output voltage, and other parameters are
programmable through the I2C interface making the BQ25157 a very flexible charging solution. A voltage-based
JEITA compatible (or standard HOT/COLD) battery pack thermistor monitoring input (TS) is included that
monitors battery temperature and automatically changes charge parameters to prevent the battery from charging
outside of its safe temperature range. The temperature thresholds are also programable through I2C allowing the
host to customize the thermal charging profile. The charger is optimized for 5-V USB input, with 20-V absolute
maximum tolerance to withstand line transients. The device also integrates a linear regulator to provide a quiet
rail for radios or processors and can be independently sourced and controlled through I2C.
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6 Device Key Default Settings
PARAMETER BQ25150 BQ25155 BQ25157
Fast Charge Current (ICHARGE) 10 mA 10 mA 10 mA
Pre-Charge Current (IPRECHARGE) 2.5 mA 2.5 mA 2.5 mA
OVP 5.5V 5.5 V 6.2V
Default Input Current Ljmit (IILIM) 100 mA 500 mA 100 mA
VIN DPM Enabled (4.5 V) Disabled (4.6 V) Enabled (4.2 V)
PMID Passthrough Regulated (4.5V Default) Passthrough
IMAX Enabled Disabled Disabled
Ship Mode Wake Timer 2 seconds 0.125 seconds 2 seconds
DEVICE_ID 0x20h 0x35h 0x3Ch
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7 Pin Configuration and Functions
IN PMID BAT GND
/PG PMID BAT TS
/MR /CE NC ADCIN
VDD /INT /LP LSLDO
VIO SDA SCL VINLS
A
B
C
D
E
1 2 3 4
Figure 7-1. YFP Package 20-Pin DSBGA Top View
Table 7-1. Pin Functions
PIN I/O DESCRIPTION
NAME NO.
IN A1 I DC Input Power Supply. IN is connected to the external DC supply. Bypass IN to GND with
at least 1-µF of capacitance using a ceramic capacitor.
PMID A2, B2 I/O
Regulated System Output. Connect 10-µF capacitor from PMID to GND as close to the
PMID and GND pins as possible. (at least 3-µF of ceramic capacitance with DC bias de-
rating). Note: Shorting PMID to IN pin is not recommended as it may cause large discharge
current from battery to IN if IN pin is not truly floating.
GND A4 PWR Ground connection. Connect to the ground plane of the circuit.
VDD D1 O Digital supply LDO. Connect a 2.2-µF from this pin to ground. A 4.7-µF capacitor to ground
recommended if loaded externally.
CE C2 I
Charge Enable. Drive CE low or leave disconnected to enable charging when VIN is valid.
Drive CE high to disable charge when VIN is present. CE is pulled low internally with 900-kΩ
resistor. CE has no effect when VIN is not present.
SCL E3 I/O I2C Interface Clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA E2 I I2C Interface Data. Connect SDA to the logic rail through a 10-kΩ resistor.
LP D3 I
Low Power Mode Enable. Drive this pin low to set the device in low power mode when
powered by the battery. This pin must be driven high to allow I2C communication when VIN
is not present. LP is pulled low internally with 900-kΩ resistor. This pin has no effect when
VIN is present.
ADCIN C4 I Input Channel to the ADC. Maximum ADC range 1.2 V. If not used it may be left floating or
connect to ground.
MR C1 I
Manual Reset Input. MR is a general purpose input that must be held low for greater than
tHWRESET to go into HW Reset and power cycle the output rails. If MR is also used to wake
up the device out of Ship Mode when pressed for at least tWAKE1. MR has in internal 125-kΩ
pull-up resistor to BAT.
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Table 7-1. Pin Functions (continued)
PIN I/O DESCRIPTION
NAME NO.
LS/LDO D4 O
Load Switch or LDO output. Connect 2.2 µF of ceramic capacitance to this pin to assure
stability. Be sure to account for capacitance bias voltage derating when selecting the
capacitor. If LDO is not used, short to VINLS
VINLS E4 I Input to the Load Switch / LDO output. Connect at least 1 µF of ceramic capacitance from
this pin to ground.
BAT A3, B3 I/O Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with
at least 1 µF of ceramic capacitance.
TS B4 I Battery Pack NTC Monitor. Connect TS to a 10-kΩ NTC thermistor in parallel to a 10-kΩ
resistor. If TS function is not to be used connect a 5-kΩ resistor from TS to ground.
PG B1 O
Open-drain Power Good status indication output. PG is pulled to GND when VIN is above
VBAT+ VSLP and less than VOVP. PG is high-impedance when the input power is not within
specified limits. Connect PG to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor,
or use with an LED for visual indication. PG can also be configured through I2C as a push-
button level shifted output ( MR), where the output of the PG pin reflects the status of the
MR input, but pulled up to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor. The
PG pin can also be configured as a general purpose open drain output.
VIO E1 I
System IO supply. Connect to system IO supply to allow level shifting of input signals (SDA,
SCL, LP and CE) to the device internal digital domain. Connect to VDD when external IO
supply is not available.
NC C3 I No Connect. Connect to ground if possible for better thermal dissipation or leave floating. Do
not connect to a any voltage source or signal to avoid higher quiescent current.
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage
IN –0.3 20 V
TS, ADCIN, VDD, NC –0.3 1.95 V
VINLS, PMID -0.3 6.2 V
All other pins –0.3 5.5 V
Current
IN 0 800 mA
BAT, PMID –0.5 1.5 A
INT, ADCIN, PG 0 10 mA
Junction temperature, TJ–40 125 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1) ±2000
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VBAT Battery voltage range 2.4 4.6 V
VIN Input voltage range 3.15 6.05
(1) V
VINLS LDO input voltage range 2.2 6.05(1) V
VIO IO supply voltage range 1.2 3.6 V
VADCIN ADC input voltage range 0 1.2 V
ILDO LDO output current 0 100 mA
IPMID PMID output current 0 1.5 A
TAOperating free-air temperature range –40 85 °C
(1) Based on minimum VOVP value. 6.2V under typical conditions
8.4 Thermal Information
THERMAL METRIC(1)
BQ25157
UNITYFP (DSBGA)
20-PIN
RθJA Junction-to-ambient thermal resistance (2) 36.1 °C/W
RθJA Junction-to-ambient thermal resistance 74.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.5 °C/W
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8.4 Thermal Information (continued)
THERMAL METRIC(1)
BQ25157
UNITYFP (DSBGA)
20-PIN
RθJB Junction-to-board thermal resistance 17.6 °C/W
ΨJT Junction-to-top characterization parameter 0.3 °C/W
ΨJB Junction-to-board characterization parameter 17.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Measured in BQ25157EVM board.
8.5 Electrical Characteristics
VIN = 5V, VBAT = 3.6V. -40°C < TJ < 125°C unless otherwise noted. Typical data at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CURRENTS
IIN Input supply current
PMID_MODE = 01, VIN = 5V, VBAT = 3.6V 500 µA
0°C <TJ < 85°C , VIN = 5V, VBAT = 3.6V
Charge Disabled 2 mA
IBAT_SHIP Battery Discharge Current in Ship Mode 0°C <TJ < 60°C ,VIN = 0V , VBAT = 3.6V 10 150 nA
IBAT_LP
Battery Quiescent Current in Low-power
Mode
0°C <TJ < 60°C ,VIN = 0V , VBAT = 3.6V,
LDO Disabled 0.46 1.2 µA
0°C <TJ < 60°C ,VIN = 0V , VBAT = 3.6V,
LDO Enabled 1.7 3.5 µA
IBAT_ACTI
VE
Battery Quiescent Current in Active Mode
0°C <TJ < 85°C ,VIN = 0V , VBAT = 3.6V,
LDO Disabled 18 25 µA
0°C <TJ < 85°C ,VIN = 0V , VBAT = 3.6V,
LDO Enabled 21 27 µA
POWER PATH MANAGEMENT AND INPUT CURRENT LIMIT
RON(IN-
PMID)
Input FET ON resistance IILIM = 500mA (ILIM = 110), VIN = 5V, IIN =
150mA 280 520 mΩ
VBSUP1 Enter supplements mode threshold VBAT > VBATUVLO, DPPM enabled or
Charge disabled
VPMID <
VBAT –
40mV
mV
VBSUP2 Exit supplements mode threshold VBAT > VBATUVLO, DPPM enabled or
Charge disabled
VPMID <
VBAT –
20mV
mV
IILIM Input Current Limit
Programmable Range 50 600 mA
IILIM = 50mA 45 50 mA
IILIM = 100mA 90 100 mA
IILIM = 150mA 135 150 mA
IILIM = 500mA 450 500 mA
VIN_DPM
Input DPM voltage threshold where
current in reduced Programmable Range 4.2 4.9 V
Accuracy –3 3 %
BATTERY CHARGER
VDPPM
PMID voltage threshold when charge
current is reduced VPMID - VBAT 200 mV
RON(BAT-
PMID)
Battery Discharge FET On Resistance VBAT = 4.35V, IBAT = 100mA 100 135 mΩ
VBATREG
Charge Voltage Programmable charge voltage range 3.6 4.6 V
Voltage Regulation Accuracy 0.5 0.5 %
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8.5 Electrical Characteristics (continued)
VIN = 5V, VBAT = 3.6V. -40°C < TJ < 125°C unless otherwise noted. Typical data at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICHARGE
Fast Charge Programmable Current
Range VLOWV < VBAT < VBATREG 1.25 500 mA
Fast Charge Current Accuracy TJ = 25°C, ICHARGE > 5mA –5 5 %
IPRECHAR
GE
Precharge current Precharge current programmable range 1.25 77.5 mA
Precharge Current Accuracy -40°C < TJ < 85°C –10 10 %
ITERM
Termination Charge Current Termination Current Programmable
Range 1 31 %
Accuracy
TJ = 25°C, ITERM = 10% ICHARGE, ICHARGE
= 100mA –5 5 %
-10°C < TJ < 85°C, ITERM = 10% ICHARGE,
ICHARGE = 100mA –10 10 %
VLOWV
Programmable voltage threshold for pre-
charge to fast charge transitions VBAT rising. Programmable Range 2.8 3 V
VSHORT
Battery voltage threshold for short
detection VBAT falling, VIN = 5V 2.41 2.54 2.67 V
ISHORT Charge Current in Battery Short Condition VBAT < VSHORT
IPRECHAR
GE
mA
VRCH Recharge Threshold voltage
VBAT falling, VBATREG = 4.2V, VRCH =
140mV setting 140 mV
VBAT falling, VBATREG = 4.2V, VRCH =
200mV setting 200 mV
RPMID_PD PMID pull-down resistance VPMID = 3.6V 25 Ω
VDD
VDD VDD LDO output voltage VBAT = 3.6V, VIN = 0V, 0 < ILOAD_VDD <
10mA 1.8 V
ILOAD_VD
D
Maximum VDD External load capability VPMID > 3V 10 mA
LS/LDO
VINLS
Input voltage range for Load switch Mode 0.8 6.2 V
Input voltage range for LDO Mode
2.2 or
VLDO +
500mV
6.2 V
VLDO
LDO programmable output voltage range 0.6 3.7 V
LDO output accuracy TJ = 25°C –2 2 %
VLDO = 1.8V, VINLS =3.6V. ILOAD = 1mA –3 3 %
ΔVOUT/
ΔIOUT
DC Load Regulation 0°C < TJ < 85°C, 1 mA < IOUT < 150mA,
VLDO = 1.8V 1.2 %
ΔVOUT/
ΔVIN
DC Line Regulation 0°C < TJ < 85°C, Over VINLS range, IOUT =
100mA, VLDO = 1.8V 0.5 %
RDOSN_LD
O
Switch On resistance VINLS = 3.6V 250 450 mΩ
RDSCH_LS
LDO
Discharge FET On-resistance for LS VINLS = 3.6V 40 Ω
IOCL_LDO Output Current Limit VLS/LDO = 0V 200 300 mA
IIN_LDO
LDO VINLS quiescent current in LDO
mode VBAT = VINLS=3.6V 0.9 µA
OFF State Supply Current VBAT = VINLS=3.6V 0.25 µA
ADC
Resolutio
nBits reported by ADC 16 Bits
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8.5 Electrical Characteristics (continued)
VIN = 5V, VBAT = 3.6V. -40°C < TJ < 125°C unless otherwise noted. Typical data at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tADC_CON
V
Conversion-time
ADC_SPEED = 00 24 ms
ADC_SPEED = 01 12 ms
ADC_SPEED = 10 6 ms
ADC_SPEED = 11 3 ms
Resolutio
nEffective Resolution ADC_SPEED = 00 12 Bits
ADC_SPEED = 10 10 Bits
Accuracy
ADC TS Accuracy ADC_SPEED = 00, VTS = 0.4V, -10°C <
TJ < 85°C –1 1 %
ADC ADCIN Accuracy ADC_SPEED = 00, VADCIN = 0.4V, -10°C
< TJ < 85°C –1 1 %
ADC VBAT Accuracy ADC_SPEED = 00, VBAT = 4.2V, -10°C <
TJ < 85°C –0.4 0.4 %
BATTERY PACK NTC MONITOR
VHOT High temperature threshold VTS falling, -10°C < TJ < 85°C 0.182 0.185 0.189 V
VWARM Warm temperature threshold VTS falling, -10°C < TJ < 85°C 0.262 0.265 0.268 V
VCOOL Cool temperature threshold VTS rising, -10°C < TJ < 85°C 0.510 0.514 0.518 V
VCOLD Cold temperature threshold VTS rising, -10°C < TJ < 85°C 0.581 0.585 0.589 V
VOPEN TS Open threshold VTS rising, -10°C < TJ < 85°C 0.9 V
VHYS Threshold hysteresis 4.7 mV
ITS_BIAS TS bias current -10°C < TJ < 85°C 78.4 80 81.6 µA
PROTECTION
VUVLO IN active threshold voltage VIN rising 3.4 V
VIN falling 3.25 V
VBATUVLO
Battery undervoltage Lockout Threshold
Voltage Programmable range, 150 mV Hysteresis 2.4 3 V
Accuracy –3 3 %
Battery undervoltage Lockout Threshold
Voltage at Power Up VBAT rising, VIN = 0V, TJ = 25°C 3.15 V
VSLP_ENT
RY
Sleep Entry Threshold (VIN - VBAT) 2.0V < VBAT < VBATREG, VIN falling 80 mV
VSLP_EXIT Sleep Exit Threshold (VIN - VBAT) 2.0V < VBAT < VBATREG 130 mV
VOVP Input Supply Over Voltage Threshold VIN rising 6.05 6.2 6.5 V
VIN falling (125mV hysteresis) 6.1 V
IBAT_OCP
Battery Over Current Threshold
Programmable range IBAT_OCP increasing 1200 1600 mA
Current Limit Accuracy –30 30 %
TSHUTDO
WN
Thermal shutdown trip point 125 °C
THYS Thermal shutdown trip point hysteresis 15 °C
I2C INTERFACE (SCL and SDA)
I2C Frequency 100 400 kHz
VIL Input Low threshold level VPULLUP = VIO = 1.8V 0.25 *
VIO
V
VIH Input High Threshold level VPULLUP = VIO = 1.8V 0.75 *
VIO
V
VOL Output Low threshold level VPULLUP = VIO = 1.8V, ILOAD = 5mA 0.25 *
VIO
V
ILKG High-level leakage Current VPULLUP = VIO = 1.8V 1 µA
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8.5 Electrical Characteristics (continued)
VIN = 5V, VBAT = 3.6V. -40°C < TJ < 125°C unless otherwise noted. Typical data at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
/MR INPUT
RPU Internal pull up resistance 90 125 170 kΩ
VIL /MR Input Low threshold level VBAT > VBUVLO 0.3 V
/INT, /PG OUTPUTS
VOL Output Low threshold level VPULLUP = VIO = 1.8V, ILOAD = 5mA 0.25 *
VIO
V
ILKG /INT Hi level leakage Current High Impedance, VPULLUP = VIO = 1.8V 1 µA
/CE, /LP INPUTS
RPDOWN /CE pull down resistance 900 kΩ
VIL Input Low threshold level VIO = 1.8V 0.45 V
VIH /CE Input High Threshold level VIO = 1.8V 1.35 V
8.6 Timing Requirements
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BATTERY CHARGE TIMERS
tMAXCHG Charge safety timer Programmable range 180 720 min
tPRECHG Precharge safety timer 0.25 * tMAXCHG
WATCHDOG TIMERS
tWATCHDO
G_SW
SW Watchdog timer 25 50 s
tHW_RESE
T_WD
HW reset watchdog timer WATCHDOG_15S_ENABLE = 1 15 s
LDO
tON_LDO Turn ON time 100mA load, to 90% VLDO 500 µs
tOFF_LDO Turn OFF time 100mA load, to 10% VLDO 30 µs
tPMID_LDO
_DELAY
Delay between PMID and LDO enable
during power up Startup 20 ms
PUSHBUTTON TIMERS (/MR)
tWAKE1
WAKE1 Timer. Time from /MR falling
edge to INT being asserted.
MR_WAKE1_TIMER = 0 106 125 144 ms
MR_WAKE1_TIMER = 1 425 500 575 ms
tWAKE2
WAKE2 Timer. Time from /MR falling
edge to INT being asserted.
MR_WAKE2_TIMER = 0 0.85 1 1.15 s
MR_WAKE2_TIMER = 1 1.7 2 2.3 s
tRESET_W
ARN
RESET_WARN Timer. Time prior to HW
RESET
MR_RESET_WARN = 00 0.42 0.5 0.58 s
MR_RESET_WARN = 01 0.85 1 1.15 s
MR_RESET_WARN = 10 1.27 1.5 1.73 s
MR_RESET_WARN = 11 1.7 2 2.3 s
tHW_RESE
T
HW RESET Timer. Time from /MR falling
edge to HW Reset
MR_HW_RESET = 00 3.4 4 4.6 s
MR_HW_RESET = 01 6.8 8 9.2 s
MR_HW_RESET = 10 8.5 10 11.5 s
MR_HW_RESET = 11 11.9 14 16.1 s
tRESTART(
AUTOWAKE
)
RESTART Timer. Time from /MR HW
Reset to PMID power up
AUTOWAKE = 00 0.52 0.6 0.68 s
AUTOWAKE = 01 1.05 1.2 1.35 s
AUTOWAKE = 10 2.11 2.4 2.69 s
AUTOWAKE = 11 4.4 5 5.6 s
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8.6 Timing Requirements (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PROTECTION
tDGL_SLP
Deglitch time for supply rising above VSLP
+ VSLP_HYS
120 µs
tDGL_OVP Deglitch time for VOVP Threshold VIN falling below VOVP 32 ms
tDGL_OCP Battery OCP deglitch time 30 µs
tREC_SC
Recovery time, BAT Short Circuit during
Discharge Mode 250 ms
tRETRY_SC
Retry window for PMID or BAT short
circuit recovery 2 s
tDGL_SHT
DWN
Deglitch time, Thermal shutdown TJ rising above TSHUTDOWN 10 µs
I2C INTERFACE
tWATCHDO
G
I2C interface reset timer for host When enabled 50 s
tI2CRESET I2C interface inactive reset timer 500 ms
INPUT PINS (/CE and /LP)
tLP_EXIT_I
2C
Time for device to exit Low-power mode
and allow I2C communication VIN = 0V. 1 ms
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8.7 Typical Characteristics
CIN = 1 µF, CPMID= 10 µF, CLSLDO = 2.2 µF, CBAT = 1 µF (unless otherwise specified)
VBATREG (V)
Error (%)
3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5 4.6
-0.5
-0.45
-0.4
-0.35
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
0
D011
TJ= 25C
TJ= 0C
TJ= -40C
TJ= 60C
TJ= 125C
VIN = 5 V PMID = Pass-Through
Figure 8-1. Battery Regulation Voltage Accuracy vs. VBATREG
Setting
ICHARGE (A)
Error (%)
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
-1.75
-1.5
-1.25
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
1.25
D014
TJ= -40C
TJ= 0C
TJ= 25C
TJ= 60C
TJ= 125C
VIN = 5 V VBAT = 3.6 V ICHARGE_RANGE = 1
Figure 8-2. Charge Current Accuracy vs. ICHARGE Setting
IPRECHARGE (mA)
Error (%)
0 5 10 15 20 25 30 35 40
-1.5
-1
-0.5
0
0.5
1
1.5
D012
TJ= 25C
TJ= 0C
TJ= -40C
TJ= 60C
TJ= 125C
VIN = 5 V VBAT = 2.7 V ICHARGE_RANGE = 0
Figure 8-3. Pre-Charge Current Accuracy vs. IPRECHARGE
setting (ICHARGE_RANGE = 0)
IPRECHARGE (A)
Error (%)
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
D013
TJ= 25C
TJ= 0C
TJ= -40C
TJ= 60C
TJ= 125C
VBUS = 5 V VBAT = 2.7 V ICHARGE_RANGE = 1
Figure 8-4. Pre-Charge Current Accuracy vs. IPRECHARGE
Setting (ICHARGE_RANGE = 1)
VINLS (V)
RDSON (:)
1 1.5 2 2.5 3 3.5 4 4.5 5
0
0.2
0.4
0.6
0.8
1
1.2
D015
TJ= -40C
TJ= 25C
TJ= 85C
VBUS = 5 V
Figure 8-5. LS/LDO Switch On Resistance vs. VINLS
ILOAD (A)
VLDO (V)
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2
0.7984
0.7992
0.8
0.8008
0.8016
0.8024
0.8032
0.804
0.8048
0.8056
0.8064
D009
TJ= -40C
TJ= 25C
TJ= 85C
VIN = 0 V VBAT = 3.6 V VINLS = VPMID
Figure 8-6. LDO Load Regulation (VLDO = 0.8 V)
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8.7 Typical Characteristics (continued)
CIN = 1 µF, CPMID= 10 µF, CLSLDO = 2.2 µF, CBAT = 1 µF (unless otherwise specified)
ILOAD (A)
VLDO (V)
0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19
1.79
1.792
1.794
1.796
1.798
1.8
1.802
1.804
1.806
1.808
1.81
1.812
1.814
1.816
1.818
1.82
D008
TJ= -40C
TJ= 25C
TJ= 85C
VIN = 0 V VBAT = 3.6 V VINLS = VPMID
Figure 8-7. LDO Load Regulation (VLDO = 1.8 V)
ILOAD (A)
VLDO (V)
0.01 0.03 0.05 0.07 0.09 0.11 0.13 0.15 0.17 0.19
3.29
3.294
3.298
3.302
3.306
3.31
3.314
3.318
3.322
3.326
3.33
D010
TJ= -40C
TJ= 25C
TJ= 85C
VIN = 0 V VBAT = 3.6 V VINLS= VPMID
Figure 8-8. LDO Load Regulation (VLDO = 3.3 V)
VINLS (V)
VLDO (V)
2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4
1.19
1.192
1.194
1.196
1.198
1.2
1.202
1.204
1.206
1.208
1.21
D004
TJ= -40C
TJ= 25C
TJ= 85C
VBAT = 4.4 V ILOAD = 150 mA
Figure 8-9. LDO Line Regulation (VLDO = 1.2 V)
VINLS (V)
VLDO (V)
2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4
1.79
1.792
1.794
1.796
1.798
1.8
1.802
1.804
1.806
1.808
1.81
D005
TJ= -40C
TJ= 25C
TJ= 85C
VBAT = 4.4 V ILOAD = 150 mA
Figure 8-10. LDO Line Regulation (VLDO = 1.8 V)
VINLS (V)
VLDO (V)
3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4
3.2
3.22
3.24
3.26
3.28
3.3
3.32
3.34
3.36
3.38
3.4
D006
TJ= -40C
TJ= 25C
TJ= 85C
VBAT = 4.4 V ILOAD = 150 mA
Figure 8-11. LDO Line Regulation (VLDO = 3.3 V)
VINLS (V)
VLDO (V)
3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4
3.4
3.425
3.45
3.475
3.5
3.525
3.55
3.575
3.6
3.625
3.65
D007
TJ= -40C
TJ= 25C
TJ= 85C
VBAT = 4.4 V ILOAD = 150 mA
Figure 8-12. LDO Line Regulation (VLDO = 3.6 V)
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9 Detailed Description
9.1 Overview
The BQ25157 IC is a highly programmable battery management device that integrates a 500-mA linear charger
for single cell Li-Ion batteries, a 16-bit ADC, a general purpose LDO that may be configured as a load switch,
and a push-button controller. Through it's I2C interface the host may change charging parameters such as
battery regulation voltage and charge current, and obtain detailed device status and fault information. The host
may also read ADC measurements for battery and input voltage among other parameters, including the ADCIN
pin voltage. The push-button controller allows the user to reset the system without any intervention from the host
and wake up the device from Ship Mode.
9.2 Functional Block Diagram
LDO, and BAT FET Control
Device Control
VIN
Charge
Enable
I2C
Interface
Low Power Mode
Control
Charge Control
LDO / Load Switch
Control
Thermal
Shutdown
IBATREG
LDO
Control UVLO VBATREG
VIN_DPM
BAT
VIN
+
±
ADC
/Power Good
GP Output
Interrupt
JEITA/Temp
Battery Voltage
Charge Current
Information
For Charge Control
VDD
VIN
IIN
PMID
VIN
IIN
VPMID
ICHG
VBAT
VTS
Ext.
S
GD
S
GD
Q7
Q8
IN
GND
VIO
/CE
SCL
SDA
/LP
/MR
/INT
/PG
PMID
VDD
VINLS
LDO
BAT
TS
ADCIN
VBATUVLO
Q5/Q6
1.045 x VBAT
PMID_REG
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9.3 Feature Description
9.3.1 Linear Charger and Power Path
The BQ25157 IC integrates a linear charger that allows the battery to be charged with a programmable charge
current of up to 500 mA. In addition to the charge current, other charging parameters can be programmed
through I2C such as the battery regulation voltage, pre-charge current, termination current, and input current limit
current.
The power path allows the system to be powered from PMID, even when the battery is dead or charging, by
drawing power from IN pin. It also prioritizes the system load connected to PMID, reducing the charging current,
if necessary, in order to support the load when input power is limited. If the input supply is removed and the
battery voltage level is above VBATUVLO, PMID will automatically and seamlessly switch to battery power.
There are several control loops that influence the charge current: constant current loop (CC), constant voltage
loop (CV), input current limit, VDPPM, and VINDPM. During the charging process, all loops are enabled and the
one that is dominant takes control regulating the charge current as needed. The charger input has back to back
blocking FETs to prevent reverse current flow from PMID to IN. They also integrate control circuitry regulating the
input current and prevents excessive currents from being drawn from the IN power supply for more reliable
operation.
The device supports multiple battery regulation voltage regulation settings (VBATREG) and charge current
(ICHARGE) options to support multiple battery chemistries for single-cell applications.
A more detailed description of the charger functionality is presented in the following sections of this document.
9.3.1.1 Battery Charging Process
The following diagram summarizes the charging process of the BQ25157 charger.
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VBAT < VLOWV
Start Precharge
Icharge set by I2C
Connect VIN
Precharge safety
timer expired?
Stop Charging and set
Fault bits
/CE toggled or VIN and
removed and
reconnected?
VBAT > VLOWV
Start FastCharge
Icharge set by I2C
IBAT < ITERM
Fast Charge safety
timer expired?
Charge Done (Set bit
and interrupt and
disconnect BATFET)
VBAT < VBAT - VRCH
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes No
Figure 9-1. BQ25157 Charger Flow Diagram
When a valid input source is connected (VIN > VUVLO and VBAT+VSLP < VIN < VOVP), the state of the CE pin
determines whether a charge cycle is initiated. When the CE input is high and a valid input source is connected,
the battery charge FET is turned off, preventing any kind of charging of the battery. A charge cycle is initiated
when the CHARGE_DISABLE bit is written to 0 and CE pin in low. Table 9-1 shows the CE pin and bit priority to
enable/disable charging.
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Table 9-1. Charge Enable Function Through CE Pin and CE Bit
CE PIN CHARGE _DISABLE BIT CHARGING
0 0 Enabled
0 1 Disabled
1 0 Disabled
1 1 Disabled
Figure 9-2 shows a typical charge cycle.
Figure 9-2. BQ25157 Typical Charge Cycle
9.3.1.1.1 Pre-Charge
In order to prevent damage to the battery, the device will charge the battery at a much lower current level when
the battery voltage (VBAT) is below the VLOWV level. The pre-charge current (IPRECHARGE) can be programmed
through I2C. Once the battery voltage reaches VLOWV, the charger will then operate in Fast Charge Mode,
charging the battery at ICHARGE.
During pre-charge, the safety timer is set to 25% of the safety timer value during fast charge.
9.3.1.1.2 Fast Charge
The charger has two main control loops that control charging when VBAT > VLOWV: the Constant Current (CC)
and Constant Voltage (CV) loops. When the CC loop is dominant, typically when VBAT < VBATREG – 50 mV, the
battery is charged at the maximum charge current level ICHARGE, unless there is a TS fault condition (JEITA
operation), thermal charge current foldback is active, VINDPM is active, or DPPM is active. (See respective
sections for details on these modes of operation.) Once the battery voltage approaches the VBATREG level, the
CV loop becomes more dominant and the charging current starts tapering off as shown in Figure 9-2. Once the
charging current reaches the termination current (ITERM) charging is stopped. Note that to ensure that the battery
is charged to VBATREG level, the regulated PMID voltage should be set to at least 200mV above VBATREG.
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9.3.1.1.3 Pre-Charge to Fast Charge Transitions and Charge Current Ramping
Whenever a change in the charge current setting is triggered, whether it occurs due to I2C programming by the
host, Pre-Charge/Fast Charge transition or JEITA TS control, the device will temporarily disable charging (for ~ 1
ms) before updating the charge current value.
9.3.1.1.4 Termination
The device will automatically terminate charging once the charge current reaches ITERM, which is programmable
through I2C.
After termination the charger will operate in high impedance mode, disabling the BATFET to disconnect the
battery. Power is provided to the system (PMID) by IN supply as long and VIN > VUVLO and VBAT+VSLP < VIN <
VOVP.
Termination is only enabled when the charger CV loop is active in fast charge operation. No termination will
occur if the charge current reaches ITERM while VINDPM or DPPM is active as well as the thermal regulation
loop. Termination is also disabled when operating in the TS WARM region. The charger only goes to termination
when the current drops to ITERM due to the battery reaching the target voltage and not due to the charge current
limitation imposed by the previously mentioned control loops.
9.3.1.2 JEITA and Battery Temperature Dependent Charging
The charger can be configured through I2C setting to provide JEITA support, automatically reducing the charging
current and voltage depending on the battery temperature as monitored by an NTC thermistor connected to the
BQ25157 TS pin. See Section 9.3.11 for details.
9.3.1.3 Input Voltage Based Dynamic Power Management (VINDPM) and Dynamic Power Path
Management (DPPM)
The VINDPM loop prevents the input voltage from collapsing to a point where charging would be interrupted by
reducing the current drawn by charger in order to keep VIN from dropping below VIN_DPM. Once the IN voltage
drops to VIN_DPM, the VINDPM loops will reduce the input current through the blocking FETs, to prevent the
further drop of the supply voltage. The VINDPM function is disabled by default and may be enabled through I2C
command. The VIN_DPM threshold is programmable through the I2C register from 4.2 V to 4.9 V in 100-mV steps.
On the other hand, the DPPM loop prevents the system output (PMID) from dropping below VBAT + 200mV when
the sum of the charge current and system load exceeds the BQ21061 input current limit setting. If PMID drops
below the DPPM voltage threshold, the charging current is reduced. If PMID continues to drop after BATFET
charging current is reduced to zero, the part will enter supplement mode when PMID falls below the supplement
mode threshold (VBAT - VBSUP1). NOte that DPPM function is disabled when PMID regulation is set to battery
tracking.
When the device enters these modes, the charge current may be lower than the set value and the corresponding
status bits and flags are set. If the 2X timer is set, the safety timer is extended while the loops are active.
Additionally, termination is disabled.
9.3.1.4 Battery Supplement Mode
While in DPPM mode, if the charging current falls to zero and the system load current increases beyond the
programmed input current limit, the voltage at PMID reduces further. When the PMID voltage drops below the
battery voltage by VBSUP1, the battery supplements the system load. The battery stops supplementing the
system load when the voltage on the PMID pin rises above the battery voltage by VBSUP2. During supplement
mode, the battery supplement current is not regulated, however, the Battery Over-Current Protection mechanism
is active. Battery charge termination is disabled while in supplement mode.
9.3.2 Protection Mechanisms
9.3.2.1 Input Over-Voltage Protection
The input over-voltage protection protects the device and downstream components connected to PMID, and BAT
against damage from over-voltage on the input supply. When VIN > VOVP an OVP fault is determined to exist.
During the OVP fault, the device turns the input FET off, sends a single 128-µs pulse on INT, and the
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VIN_OVP_FAULT FLAG and STAT bits are updated over I2C. Once the OVP fault is removed, the STAT bit is
cleared and the device returns to normal operation. The FLAG bit is not cleared until it is read through I2C after
the OVP condition no longer exists. The OVP threshold for the device is 6.2 V (typ) on powerup either when VIN
or VBAT is valid.
9.3.2.2 Safety Timer and I2C Watchdog Timer
At the beginning of the charge cycle, the device starts the safety timer. If charging has not terminated before the
programmed safety time, tMAXCHG, expires, charging is disabled. The pre-charge safety time, tPRECHG, is 25% of
tMAXCHG. When a safety timer fault occurs, a single 128-µs pulse is sent on the INT pin and the
SAFETY_TMR_FAULT_FLAG bit in the FLAG3 register is updated over I2C. The CE pin or input power must be
toggled in order to reset the safety timer and exit the fault condition. Note that the flag bit will be reset when the
bit is read by the host even if the fault has not been cleared. The safety timer duration is programmable using the
SAFETY_TIMER bits. When the safety timer is active, changing the safety timer duration resets the safety timer.
The device also contains a 2X_TIMER bit that doubles the timer duration in order to prevent premature safety
timer expiration when the charge current is reduced by a high load on PMID (DPPM operation), VIN DPM,
thermal regulation, or a NTC (JEITA) condition. When 2X_TIMER function is enabled, the timer is allowed to run
at half speed when any loop is active other than CC or CV.
In addition to the safety timer, the device contains a 50-second I2C watchdog timer that monitors the host
through the I2C interface. The watchdog timer is enabled by default and may be disabled by the host through
I2C. Once the watchdog timer is enabled, the watchdog timer is started. The watchdog timer is reset by any
transaction by the host using the I2C interface. If the watchdog timer expires without a reset from the I2C
interface, all charger parameters registers (ICHARGE, IPRECHARGE, ITERM,VLOWV, etc.) are reset to the
default values.
9.3.2.3 Thermal Protection and Thermal Charge Current Foldback
During operation, to protect the device from damage due to overheating, the junction temperature of the die, TJ,
is monitored. When TJ reaches TSHUTDOWN the device stops operation and is turned off. The device resumes
operation when TJ falls below TSHUTDOWN by THYS.
During the charging process, to prevent overheating in the device, the device monitors the junction temperature
of the die and reduces the charging current at a rate of (0.04 x ICHARGE )/°C once TJ exceeds the thermal
foldback threshold, TREG. If the charge current is reduced to 0, the battery supplies the current needed to supply
the PMID output. The thermal regulation threshold may be set through I2C by setting the THERM_REG bits to
the desired value.
To ensure that the system power dissipation is under the limits of the device. The power dissipated by the device
can be calculated using Equation 1:
/DISS PMID LS LDO BAT
P P P P 
(1)
Where:
( )
PMID IN PMID IN
P V V I u
(2)
/ / /
( )
LS LDO INLS LS LDO LS LDO
P V V I u
(3)
( )
BAT PMID BAT BAT
P V V I u
(4)
The die junction temperature, TJ, can be estimated based on the expected board performance using Equation 5:
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