Texas Instruments BQ25120F3A User manual

BQ25120F3A 700-nA Low IQ Highly Integrated Battery Charge Management Solution
for Wearables and IoT
1 Features
• Increases system operation time between charges
– Configurable 300-mA buck regulator
(1.8-V default)
– 700-nA (typical) Iq with buck converter enabled
(no load)
– Configurable load switch or 100-mA LDO
output (LDO by default. VLDO 1.8-V)
– Up to 300-mA charge current for fast charging.
I2C programmable up to 200 mA, external
resistor setting for 200 mA to 300 mA.
– 0.5% Accurate battery voltage regulation
(configurable from 3.6 V to 4.65 V in 10-mV
steps) 4.35-V default
– Configurable termination current down to
500 µA
– Simple voltage based battery monitor
– Watchdog timer disabled
– TS WARM fault disabled (no reduction in
battery regulation voltage)
• Highly integrated solution with small footprint
– 2.5-mm x 2.5-mm WCSP Package and six
external components for minimal solution
– Push-button wake-up and reset with adjustable
timers
– Power path management for powering the
system and charging the battery
– Power path management enables <50 nA Ship
Mode battery quiescent current for longest shelf
life
– Battery charger operates from 3.4 V – 5.5 VIN
(5.5-V OVP / 20-V tolerant)
– Dedicated pins for input current limit, charge
current, termination current, and status output
• I2C communication control
– Charge voltage and current
– Termination threshold
– Input current limit
– VINDPM Threshold
– Timer options
– Load switch control
– System output voltage adjustment
– LDO output voltage adjustment
2 Applications
• Smart watches and other wearable devices
• Fitness accessories
• Health monitoring medical accessories
• Rechargeable toys
3 Description
The BQ25120F3A is a highly integrated battery
charge management IC that integrates the most
common functions for wearable devices: Linear
charger, regulated output, load switch, manual reset
with timer, and battery voltage monitor. The integrated
buck converter is a high efficiency, low IQ switcher
using DCS-Control™ that extends light load efficiency
down to 10-µA load currents. The low quiescent
current during operation and shutdown enables
maximum battery life. The device supports charge
currents from 5 mA to 300 mA.
Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
BQ25120F3A DSBGA (25) 2.50 mm x 2.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
GND
HOST SDA
SCL
INT
SW
BAT
MR
BQ2512x
MCU /
SYSTEM
-+
NTC
TS
LS / LDO
<100mA
Load
IN
SYS
RESET
LSCTRL
VINLS
Unregulated
Load
PMID
PG
IPRETERM
ISET
ILIM
CD
IN
Copyright © 2016, Texas Instruments Incorporated
Simplified Schematic
BQ25120F3A
SLUSDI4A – OCTOBER 2018 – REVISED APRIL 2021
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Device Comparison Table...............................................3
7 Pin Configuration and Functions...................................4
8 Specifications.................................................................. 6
8.1 Absolute Maximum Ratings........................................ 6
8.2 ESD Ratings............................................................... 6
8.3 Recommended Operating Conditions.........................6
8.4 Thermal Information....................................................7
8.5 Electrical Characteristics.............................................8
8.6 Timing Requirements................................................12
8.7 Typical Characteristics.............................................. 15
9 Detailed Description......................................................17
9.1 Overview................................................................... 17
9.2 Functional Block Diagram......................................... 17
9.3 Feature Description...................................................18
9.4 Device Functional Modes..........................................30
9.5 Programming............................................................ 32
9.6 Register Maps...........................................................35
10 Application and Implementation................................ 48
10.1 Application Information........................................... 48
10.2 Typical Application.................................................. 49
11 Power Supply Recommendations..............................64
12 Layout...........................................................................65
12.1 Layout Guidelines................................................... 65
12.2 Layout Example...................................................... 65
13 Device and Documentation Support..........................66
13.1 Device Support....................................................... 66
13.2 Receiving Notification of Documentation Updates..66
13.3 Trademarks.............................................................66
13.4 Support Resources................................................. 66
13.5 Electrostatic Discharge Caution..............................66
13.6 Glossary..................................................................66
14 Mechanical, Packaging, and Orderable
Information.................................................................... 66
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (October 2018) to Revision A (January 2021) Page
• Changed status from restricted to public............................................................................................................ 1
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5 Description (continued)
The battery is charged using a standard Li-Ion charge profile with three phases: precharge, constant current
and constant voltage. A voltage-based battery pack thermistor monitoring input (TS) is included that monitors
battery temperature and automatically changes charge parameters to prevent the battery from charging outside
of its safe temperature range. The charger is optimized for 5-V USB input, with 20-V tolerance to withstand line
transients. The buck converter is run from the input or battery. When in battery only mode, the device can run
from a battery up to 4.65 V.
A configurable load switch allows system optimization by disconnecting infrequently used devices. The manual
reset with timer allows multiple different configuration options for wake are reset optimization. A simple voltage
based monitor provides battery level information to the host in 2% increments from 60% to 100% of the
programmed V(BATREG).
6 Device Comparison Table
PART
NUMBER
Default
VINDPM
DEFAULT
SYS OUTPUT
DEFAULT
LDO OUTPUT
DEFAULT
VBATREG
DEFAULT
CHARGE
CURRENT
DEFAULT
TERMINATION
CURRENT
VDPPM WATCHDOG
BQ25120F3A Enabled 1.8 V 1.8 V (LDO) 4.35 V 40 mA 10 mA Enabled Disabled
BQ25120A Enabled 1.8 V Load Switch 4.2 V 10 mA 2 mA Enabled Enabled
BQ25121A Enabled 2.5 V Load Switch 4.2 V 10 mA 2 mA Enabled Disabled
BQ25122 Enabled 1.2 V Load Switch 4.2 V 11 mA 0.5 mA Enabled Enabled
BQ25125 Disabled 1.8 V 1.8 V (LDO) 4.2 V 10 mA 2 mA Disabled Enabled
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7 Pin Configuration and Functions
GND
RESETINT
MR
IPRETE
RM
ISET
BATBAT
TS
ILIM
PG
VINLS
VINLS
PGNDSWPMID
A
B
C
D
1 2 3 4
SDALSCTRLCD SCL
E
IN
LS/LDO
SYSPMID
GND
5
Figure 7-1. YFP Package 25-Pin DSBGA Top View
Table 7-1. Pin Functions
PIN I/O DESCRIPTION
NAME NO.
IN A2 I DC Input Power Supply. IN is connected to the external DC supply. Bypass IN to GND with
at least 1 µF of capacitance using a ceramic capacitor.
PMID A3, B3 I/O
High Side Bypass Connection. Connect at least 3µF of ceramic capacitance with DC bias
derating from PMID to GND as close to the PMID and GND pins as possible. When entering
Ship Mode, PMID is discharged by a 20-kΩ internal discharge resistor.
GND A1, D5 Ground connection. Connect to the ground plane of the circuit.
PGND A5 Power ground connection. Connect to the ground plane of the circuit. Connect the output
filter cap from the buck converter to this ground as shown in the layout example.
CD E2 I
Chip Disable. Drive CD low to place the part in High-Z mode with battery only present, or
enable charging when VIN is valid. Drive CD high for Active Battery mode when battery only
is present, and disable charge when VIN is present. CD is pulled low internally with 900 kΩ.
SDA E4 I/O I2C Interface Data. Connect SDA to the logic rail through a 10-kΩ resistor.
SCL E5 I I2C Interface Clock. Connect SCL to the logic rail through a 10-kΩ resistor.
ILIM C2 I
Adjustable Input Current Limit Programming. Connect a resistor from ILIM to GND to
program the input current limit. The input current includes the system load and the battery
charge current. Connect ILIM to GND to set the input current limit to the internal default
threshold. ILIM can also be updated through I2C.
LSCTRL E3 I Load Switch and LDO Control Input. Pull high to enable the LS/LDO output, pull low to
disable the LS/LDO output.
ISET C1 I
Fast-Charge Current Programming Input. Connect a resistor from ISET to GND to program
the fast-charge current level. Connect a resistor from ISET to GND to set the charge current
to the internal default. ISET can also be updated through I2C. While charging, the voltage
at ISET reflects the actual charging current and can be used to monitor charge current if an
ISET resistor is present and the device is not in host mode.
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Table 7-1. Pin Functions (continued)
PIN I/O DESCRIPTION
NAME NO.
IPRETERM D1 I
Termination current programming input. Connect a 0-Ω to 10-kΩ resistor from IPRETERM to
GND to program the termination current between 5% and 20% of the charge current. The
pre-charge current is the same as the termination current setting. Connect IPRETERM to
GND to set the termination current to the internal default threshold. IPRETERM can also be
updated through I2C.
INT D2 O
Status Output. INT is an open-drain output that signals charging status and fault interrupts.
INT pulls low during charging. INT is high impedance when charging is complete, disabled,
or the charger is in high impedance mode. When a fault occurs, a 128µs pulse is sent out as
an interrupt for the host. INT charge indicator function is enabled/disabled using the EN_INT
bit in the control register. Connect INT to a logic rail using an LED for visual indication of
charge status or through a 100kΩ resistor to communicate with the host processor.
PG D4 O
Open-drain Power Good status indication output. PG pulls to GND when VIN is above
V(BAT) + VSLP and less that VOVP. PG is high-impedance when the input power is not within
specified limits. Connect PG to the desired logic voltage rail using a 1kΩ to 100kΩ resistor,
or use with an LED for visual indication. PG can also be configured as a push-button voltage
shifted output (MRS) in the registers, where the output of the PG pin reflects the status of
the MR input, but pulled up to the desired logic voltage rail using a 1kΩ to 100kΩ resistor.
RESET D3 O
Reset Output. RESET is an open drain active low output that goes low when MR is held
low for longer than tRESET, which is configurable by the MRRESET registers. RESET is
deasserted after the tRESET_D, typically 400ms.
MR E1 I
Manual Reset Input. MR is a push-button input that must be held low for greater than tRESET
to assert the reset output. If MR is pressed for a shorter period, there are two programmable
timer events, tWAKE1 and tWAKE2, that trigger an interrupt to the host. The MR input can also
be used to bring the device out of Ship mode.
SW A4 O Inductor Connection. Connect to the switched side of the external inductor.
SYS B5 I System Voltage Sense Connection. Connect SYS to the system output at the output bulk
capacitors. Bypass SYS locally with at least 4.7 µF of effective ceramic capacitance.
LS/LDO C5 O
Load Switch or LDO output. Connect 1 µF of effective ceramic capacitance to this pin to
assure stability. Be sure to account for capacitance bias voltage derating when selecting the
capacitor.
VINLS B4, C4 I Input to the Load Switch / LDO output. Connect 1 µF of effective ceramic capacitance from
this pin to GND.
BAT B1, B2 I/O Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with
at least 1 µF of ceramic capacitance.
TS C3 I
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from VIN to
GND. The NTC is connected from TS to GND. TS faults are reported by the I2C interface
during charge mode.
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Input voltage
IN wrt GND –0.3 20 V
PMID, VINLS wrt GND –0.3 7.7 V
CD, SDA, SCL, ILIM, ISET, IPRETERM, LSCTRL,
INT, RESET, TS wrt GND –0.3 5.5 V
Output voltage SYS 3.6 V
Input current IN 400 mA
Sink current INT 10 mA
Sink/Source Current RESET 10 mA
Output Voltage Continuos SW –0.7 7.7 V
Output Current Continuous SW 400 mA
SYS, BAT 300 mA
Current LS/LDO 150 mA
BAT Operating Voltage VBAT, MR, 6.6 V
Junction Temperature –40 125 °C
Storage Temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
8.2 ESD Ratings
VALUE UNIT
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V
Charged device model (CDM), per JEDEC specification JESD22-
C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN
IN voltage range 3.4 5 20 V
IN operating voltage range, recommended 3.4 5 5.5
V(BAT) V(BAT) operating voltage range 5.5(1) V
V(VINLS) VINLS voltage range for Load Switch 0.8 5.5(2) V
V(VINLS) VINLS voltage range for LDO 2.2 5.5 V
IIN Input Current, IN input 400 mA
I(SW) Output Current from SW, DC 300 mA
I(PMID) Output Current from PMID, DC 300 mA
ILS/LDO Output Current from LS/LDO 100 mA
I(BAT), I(SYS) Charging and discharging using internal battery FET 300 mA
TJOperating junction temperature range –40 125 °C
(1) Any voltage greater than shown should be a transient event.
(2) These inputs will support 6.6 V for less than 10% of the lifetime at V(BAT) or VIN, with a reduced current and/or performance.
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8.4 Thermal Information
THERMAL METRIC(1)
BQ25120F3A
UNITYFP (DSBGA)
25 PINS
RθJA Junction-to-ambient thermal resistance 60 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.3 °C/W
RθJB Junction-to-board thermal resistance 12.0 °C/W
ψJT Junction-to-top characterization parameter 1.2 °C/W
ψJB Junction-to-board characterization parameter 12.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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8.5 Electrical Characteristics
Circuit of Figure 8-1, V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP), TJ = –40°C to 85°C and TJ = 25°C for typical values
(unless otherwise noted)
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
INPUT CURRENTS
IIN
Supply Current for
Control
V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP) PWM
Switching, –40°C < TJ < 85°C 1 mA
V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP) PWM NOT
Switching 3 mA
0°C < TJ < 85°C, VIN = 5 V, Charge Disabled 1.5 mA
I(BAT_HIZ)
Battery discharge current
in High Impedance Mode
0°C < TJ < 60°C, VIN = 0 V, High-Z Mode, PWM Not
Switching, V(BUVLO) < V(BAT) < 4.65 V 0.7 1.2 µA
0°C < TJ < 60°C, VIN = 0 V, High-Z Mode, PWM Not
Switching, V(BUVLO) < V(BAT) < 6.6 V 0.9 1.5 µA
0°C < TJ < 60°C, VIN = 0 V or floating, High-Z Mode, PWM
Switching, No Load 0.75 3.5 µA
0°C < TJ < 85°C, VIN = 0 V, High-Z Mode, PWM Switching,
LSLDO enabled 1.35 4.25 µA
I(BAT_ACTIVE)
Battery discharge current
in Active Battery Mode
0°C < TJ < 85°C, VIN = 0 V, Active Battery Mode, PWM
Switching, LSLDO enabled, I2C Enabled, V(BUVLO) < V(BAT) <
4.65 V
6.8 12 µA
0°C < TJ < 85°C, 0 < VIN < VIN(UVLO), Active Battery Mode,
PWM Switching, LSLDO disabled, I2C Enabled, CD = Low,
V(BUVLO) < V(BAT) < 4.65 V
6.2 11 µA
I(BAT_SHIP)
Battery discharge current
in Ship Mode 0°C < TJ < 85°C, VIN = 0 V, Ship Mode 2 150 nA
POWER-PATH MANAGEMENT and INPUT CURRENT LIMIT
VDO(IN-PMID) VIN – V(PMID) VIN = 5 V, IIN = 300 mA 125 170 mV
VDO(BAT-PMID) V(BAT) – V(PMID) VIN = 0 V, V(BAT) > 3 V, Iff = 400 mA 120 160 mV
V(BSUP1)
Enter supplement mode
threshold V(BAT) > V(BUVLO)
V(PMID) <
V(BAT) – 25
mV
V
V(BSUP2)
Exit supplement mode
threshold V(BAT) > V(BUVLO)
V(PMID) <
V(BAT) –
5mV
V
I(BAT_OCP)
Current Limit, Discharge
Mode V(BAT) > V(BUVLO) 0.85 1.15 1.35 A
I(ILIM)
Input Current Limit Programmable Range, 50-mA steps 50 400 mA
Maximum Input Current
using ILIM
K(ILIM) /
R(ILIM)
IILIM accuracy IILIM
accuracy
50 mA to 100 mA –12% 12%
100 mA to 400 mA –5% 5%
K(ILIM)
Maximum input current
factor
I(ILIM) = 50 mA to 100 mA 175 200 225 AΩ
I(ILIM) = 100 mA to 400 mA 190 200 210 AΩ
VIN(DPM)
Input voltage threshold
when input current is
reduced
Programmable Range using VIN(DPM) Registers. Can be
disabled using VIN(DPM_ON)
4.2 4.9 V
VIN_DPM threshold
accuracy –3% 3%
BATTERY CHARGER
V(DPPM)
PMID voltage threshold
when charge current is
reduced
Above V(BATREG) 0.2 V
RON(BAT-PMID)
Internal Battery Charger
MOSFET on-resistance Measured from BAT to PMID, V(BAT) = 4.35 V, High-Z mode 300 400 mΩ
V(BATREG)
Charge Voltage Operating in voltage regulation, Programmable Range, 10-
mV steps 3.6 4.65 V
Voltage Regulation
Accuracy
TJ = 25°C –0.5% 0.5%
TJ = 0°C to 85°C –0.5% 0.5%
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8.5 Electrical Characteristics (continued)
Circuit of Figure 8-1, V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP), TJ = –40°C to 85°C and TJ = 25°C for typical values
(unless otherwise noted)
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
I(CHARGE)
Fast Charge Current
Range V(BATUVLO) < V(BAT) < V(BATREG) 5 300 mA
Fast Charge Current
using ISET
K(ISET) /
R(ISET)
A
Fast Charge Current
Accuracy –5% 5%
K(ISET)
Fast Charge Current
Factor 5 mA > I(CHARGE) > 300 mA 190 200 210 AΩ
I(TERM)
Termination charge
current Termination current programmable range over I2C 0.5 37 mA
Termination Current
using IPRETERM
I(CHARGE) < 300 mA, R(ITERM) = 15 kΩ 5 % of ISET
I(CHARGE) < 300 mA, R(ITERM) = 4.99 kΩ 10 % of ISET
I(CHARGE) < 300 mA, R(ITERM) = 1.65 kΩ 15 % of ISET
I(CHARGE) < 300 mA, R(ITERM) = 549 Ω 20 % of ISET
Accuracy I(TERM) > 4 mA –10% 10%
tDGL(TERM) TERM deglitch time Both rising and falling, 2-mV over-drive, tRISE, tFALL = 100 ns 64 ms
I(PRE_CHARGE)
Pre-charge current Pre-charge current programmable range over I2C 0.5 37 mA
Pre-charge Current using
IPRETERM
I(TERM) A
Accuracy –10% 10%
V(RCH)
Recharge threshold
voltage Below V(BATREG) 100 120 140 mV
tDGL(RCHG)
Recharge threshold
deglitch time tFALL = 100 ns typ, V(RCH) falling 32 ms
SYS OUTPUT
RDS(ON_HS) PMID = 3.6 V, I(SYS) = 150 mA 675 850 mΩ
RDS(ON_LS) PMID = 3.6 V, I(SYS) = 150 mA 300 475 mΩ
RDS(CH_SYS)
MOSFET on-resistance
for SYS discharge VIN = 3.6 V, IOUT = –10 mA into VOUT pin 22 40 Ω
I(LIMF)
SW Current limit HS 2.2 V < V(PMID) < 5.5 V 450 600 675 mA
SW Current limit LS 2.2 V < V(PMID) < 5.5 V 450 700 850 mA
I(LIM_SS)
PMOS switch current limit
during softstart Current limit is reduced during softstart 80 130 200 mA
VSYS
SYS Output Voltage
Range Programmable range, 100 mV Steps 1.1 3.3 V
Output Voltage Accuracy VIN = 5 V, PFM mode, IOUT = 10 mA, V(SYS) = 1.8 V –2.5% 0 2.5%
DC Output Voltage Load
Regulation in PWM mode VOUT = 2 V, over load range 0.01 %/mA
DC Output Voltage Line
Regulation in PWM mode VOUT = 2 V, IOUT = 100 mA, over VIN range 0.01 %/V
LS/LDO OUTPUT
VIN(LS)
Input voltage range for
LS/LDO Load Switch Mode 0.8 6.6 V
Input voltage range for
LS/LDO LDO Mode 2.2 6.6 V
VOUT DC output accuracy TJ = 25°C –2% ±1% 2%
Over VIN, IOUT, temperature –3% ±2% 3%
VLDO Output range for LS/LDO Programmable Range, 0.1 V steps 0.8 3.3 V
ΔVOUT / Δ VIN
DC Line regulation VOUT(NOM) + 0.5 V < VIN < 6.6 V, IOUT = 5 mA –1% 1%
DC Load regulation 0 mA < IOUT < 100 mA –1% 1%
Load Transient 2 µA to 100 mA, VOUT = 1. 8 V –120 60 mV
RDS(ON_LDO) FET Rdson V(VINLS) = 3.6 V 570 800 mΩ
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8.5 Electrical Characteristics (continued)
Circuit of Figure 8-1, V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP), TJ = –40°C to 85°C and TJ = 25°C for typical values
(unless otherwise noted)
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
R(DSCH_LSLDO)
MOSFET on-resistance
for LS/LDO discharge 1.7 V < V(VINLS) < 6.6 V, ILOAD = –10 mA 20 Ω
I(OCL_LDO)
Output Current Limit –
LDO VLS/LDO = 0 V 275 365 475 mA
I(LS/LDO) Output Current
V(VINLS) = 3.6 V, VLSLDO = 3.3 V 100 mA
V(VINLS) = 3.3 V, VLSLDO = 0.8 V 100 mA
V(VINLS) = 2.2 V, VLSLDO = 0.8 V 10 mA
IIN(LDO)
Quiescent current for
VINLS in LDO mode 0.9 µA
OFF-state supply current 0.25 µA
VIH(LSCTRL)
High-level input voltage
for LSCTRL 1.15 V > V(VINLS) > 6.6 V 0.75 x V(SYS)
6.6 V
VIL(LSCTRL)
Low-level input voltage
for LSCTRL 1.15 V > V(VINLS) > 6.6 V 0.25 x V(SYS)
V
PUSHBUTTON TIMER ( MR)
VIL Low-level input voltage VBAT > VBUVLO 0.3 V
RPU
Internal pull-up
resistance 120 kΩ
VBAT MONITOR
VBMON
Battery Voltage Monitor
Accuracy V(BAT) Falling - Including 2% increment –3.5 3.5 %V(BATREG)
BATTERY-PACK NTC MONITOR
VHOT
High temperature
threshold VTS falling, 1% VIN Hysteresis 14.5 15 15.2 %VIN
VCOOL
Cool temperature
threshold VTS rising, 1% VIN Hysteresis 35.4 36 36.4 %VIN
VCOLD
Low temperature
threshold VTS rising, 1% VIN Hysteresis 39.3 39.8 40.2 %VIN
TSOFF TS Disable threshold VTS rising, 2% VIN Hysteresis 55 60 %VIN
PROTECTION
V(UVLO)
IC active threshold
voltage VIN rising 3.4 3.6 3.8 V
VUVLO(HYS) IC active hysteresis VIN falling from above VUVLO 150 mV
V(BUVLO)
Battery Undervoltage
Lockout threshold Range
Programmable Range for V(BUVLO) VBAT falling, 150 mV
Hysteresis 2.2 3.0 V
Default Battery
Undervoltage Lockout
Accuracy
V(BAT) falling –2.5% 2.5%
V(BATSHORT)
Battery short circuit
threshold Battery voltage falling 2 V
V(BATSHORT_HYS)
Hysteresis for
V(BATSHORT)
100 mV
I(BATSHORT)
Battery short circuit
charge current I(PRETERM) mA
V(SLP)
Sleep entry threshold, VIN
– V(BAT)
2 V < VBAT < V(BATREG), VIN falling 65 120 mV
V(SLP_HYS)
Sleep-mode exit
hysteresis VIN rising above V(SLP) 40 65 100 mV
VOVP
Maximum Input Supply
OVP threshold voltage VIN rising, 100 mV hysteresis 5.35 5.55 5.75 V
tDGL_OVP
Deglitch time, VIN OVP
falling VIN falling below VOVP, 1V/us 32 ms
TSHTDWN Thermal trip VIN > VUVLO 114 °C
THYS Thermal hysteresis VIN > VUVLO 11 °C
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8.5 Electrical Characteristics (continued)
Circuit of Figure 8-1, V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP), TJ = –40°C to 85°C and TJ = 25°C for typical values
(unless otherwise noted)
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
tDGL_SHTDWN
Deglitch time, Thermal
shutdown TJ rising above TSHTDWN 4 µs
I2C INTERFACE
I2C Bus Specification
standard and fast mode
frequency support
100 400 kHz
VIL Input low threshold level VPULLUP = 1.1 V, SDA and SCL 0.275 V
VIH Input high threshold level VPULLUP = 1.1 V, SDA and SCL 0.825 V
VIH Input high threshold level VPULLUP = 3.3 V, SDA and SCL 2.475 V
VOL
Output low threshold
level IL = 5 mA, sink current, VPULLUP = 1.1 V 0.275 V
IBIAS
High-Level leakage
current VPULLUP = 1.8 V, SDA and SCL 1 µA
INT, PG, and RESET OUTPUT (Open Drain)
VOL
Low level output
threshold Sinking current = 5 mA 0.25 x V(SYS)
V
IIN Bias current into pin Pin is high impedance, IOUT = 0 mA; TJ = –40°C to 60°C 12 nA
VIN(BAT_DELTA)
Input voltage above
VBAT where PG sends
two 128 µs pulses each
minute to signal the host
of the input voltage status
VUVLO < VIN < VOVP 0.825 1 1.15 V
INPUT PIN ( CD LSCTRL)
VIL(/CD_LSCTRL) Input low threshold V(PULLUP) = VSYS = 3.3 V 0.25 * VSYS V
VIH(/CD_LSCTRL) Input high threshold V(PULLUP) = VSYS = 3.3 V 0.75 * VSYS V
RPULLDOWN/CD
Internal pull-down
resistance 900 kΩ
R(LSCTRL)
Internal pull-down
resistance 2 MΩ
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8.6 Timing Requirements
MIN TYP MAX UNIT
POWER-PATH MANAGEMENT AND INPUT CURRENT LIMIT
tDGL_SC
Deglitch Time, PMID or SW Short Circuit
during Discharge Mode 250 µs
tREC_SC
Recovery time, OUT Short Circuit during
Discharge Mode 2 s
BATTERY CHARGER
tDGL_SHORT
Deglitch time transition from ISET short to
I(CHARGE) disable Clear fault by disconnecting VIN 1 ms
BATTERY CHARGING TIMERS
tMAXCHG Charge safety timer Programmable range 2 540 min
tPRECHG Precharge safety timer 0.1 x tMAXCHG
SYS OUTPUT
tONMIN Minimum ON time VIN = 3.6 V, VOUT = 2 V, IOUT = 0 mA 225 ns
tOFFMIN Minimum OFF time VIN = 4.2 V 50 ns
tSTART_SW SW start up time VIN = 5 V, from write on EN_SW_OUT
until output starts to rise 5 25 ms
tSTART_SYS SYS output time to start switching From insertion of BAT > V(BUVLO) or
VIN > V(UVLO)
350 µs
tSOFTSTART Softstart time with reduced current limit 400 1200 µs
LS/LDO OUTPUT
tON_LDO Turn ON time 100-mA load 500 µs
tOFF_LDO Turn OFF time 100-mA load 5 µs
PUSHBUTTON TIMER
tWAKE1 Push button timer wake 1 Programmable Range for wake1
function 0.08 1 s
tWAKE2 Push button timer wake 2 Programmable Range for wake2
function 1 2 s
tRESET Push button timer reset Programmable Range for reset
function 5 15 s
tRESET_D Reset pulse duration 400 ms
tDD
Detection delay (from MR, input to
RESET) For 0s condition 6 µs
BATTERY-PACK NTC MONITOR
tDGL(TS) Deglitch time on TS change Applies to V(HOT), V(WARM), V(COOL),
and V(COLD)
50 ms
I2C INTERFACE
tWATCHDOG I2C interface reset timer for host 50 s
tI2CRESET I2C interface inactive reset timer 700 ms
tHIZ_ACTIVEBAT
Transition time required to enable the I2C
interface from HiZ to Active BAT 1 ms
INPUT PIN
t/CD_DGL Deglitch for CD CD rising/falling 100 µs
tQUIET Input quiet time for Ship Mode transition 1 ms
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VIN
SW
SYS
VBAT
CD
PG
IBAT
PMID
Insert
Battery
Apply
VIN
VIN > UVLO
After delay of several ms,
switching starts and SYS
starts to rise
Charging
enabled
Charging
disabled
VBAT
rises
VBAT = VBATREG
Charge
Current
Taper
IBAT=ICHRG VBAT =
VBATREG - VRCHG
IBAT = ITERM
BAT supplies SYS
when VIN removed
INT
BAT IQ
Typical Start-Up Timing and Operation
VBAT>VBUVLO
Remove
Battery
Shows
Charge
Status
VISET
<3uA max <4uA max
No SYS Load
SYS Load Applied
<3uA max
<5uA max
<4uA max
nA of leakage with VIN present
0mA
Conditions: PGB_MRS = 0, TE = 1, SW_LDO = 1, VINDPM_ON = 0, PG and INT pulled up to SYS, EN_INT = 1
Figure 8-1. Typical Start-Up Timing and Operation
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Conditions: SW_LDO = 1, MRREC = 1, PG and INT pulled up to SYS, ISYS = 10 µA, EN_INT = 1
Figure 8-2. Battery Operation and Sleep Mode
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8.7 Typical Characteristics
BAT (V)
BAT IQ(PA)
3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6
0
2
4
6
8
10
12
D016
85qC
60qC
25qC
0qC
Figure 8-3. Active BAT, IQ
BAT (V)
BAT IQ(PA)
3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6
0.0
0.5
1.0
1.5
2.0
D017
85qC
60qC
25qC
0qC
1.8 V System Enabled (No Load)
Figure 8-4. Hi-Z BAT, IQ
BAT (V)
BAT IQ(PA)
3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
D018
85qC
60qC
25qC
0qC
Figure 8-5. Ship Mode BAT, IQ
Temperature (qC)
RDS(ON) (m:)
-40 -25 -10 5 20 35 50 65 80 95 110 125
0
100
200
300
400
500
600
700
D024
Figure 8-6. Blocking FET RDS(ON) vs Temperature
Temperature (qC)
RDS(ON) (m:)
-40 -25 -10 5 20 35 50 65 80 95 110 125
0
50
100
150
200
250
300
350
400
D025
Figure 8-7. Battery Discharge FET RDS(ON) vs Temperature
Temperature (qC)
Accuracy
-40 -10 20 50 80 110 125
-0.5%
-0.3%
-0.1%
0.1%
0.3%
0.5%
D019
4.35 V(BATREG)
4.2 V(BATREG)
4 V(BATREG)
3.8 V(BATREG)
3.6 V(BATREG)
Figure 8-8. V(BATREG) Accuracy vs Temperature
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8.7 Typical Characteristics (continued)
Input Current Limit (A)
Accuracy
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
-5%
-4%
-3%
-2%
-1%
0
1%
2%
3%
4%
5%
D020
-40qC
0qC
25qC
85qC
125qC
Figure 8-9. ILIM Accuracy vs Input Current
Charge Current (mA)
Accuracy
0 50 100 150 200 250 300
-5%
-3%
-1%
1%
3%
5%
D021
-40qC
0qC
25qC
85qC
125qC
Figure 8-10. Charge Current Accuracy vs Charge Current
Pre-Charge Current (mA)
Accuracy
0 5 10 15 20 25 30 35 40
-10%
-8%
-6%
-4%
-2%
0
2%
4%
6%
8%
10%
D022
-40qC
0qC
25qC
85qC
125qC
Figure 8-11. Pre-Charge Accuracy vs Pre-Charge Current
Temperature (qC)
RDS(ON) (m:)
-40 -25 -10 5 20 35 50 65 80 95 110 125
0
100
200
300
400
500
600
700
800
900
1000
D026D024
VIN = 5 V
Figure 8-12. RDS(ON) of High Side MOSFET vs Temperature
Temperature (qC)
RDS(ON) (m:)
-40 -25 -10 5 20 35 50 65 80 95 110 125
0
50
100
150
200
250
300
350
400
D027
VIN = 5 V
Figure 8-13. RDS(ON) of Low Side MOSFET vs Temperature
Frequency (Hz)
PSRR (dB)
10 20 50 100 1000 10000 100000 1000000
0
20
40
60
80
100
120
140
160
D028
Noise Floor
1 mA
10 mA
50 mA
100 mA
Figure 8-14. LS/LDO PSRR vs Frequency
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9 Detailed Description
9.1 Overview
The following sections describe in detail the functions provided by the BQ25120F3A. These include linear
charger, PWM output, configurable LS/LDO output, Push-button input, reset timer, functional modes, battery
monitor, I2C configurability and functions, and safety features.
9.2 Functional Block Diagram
SW
MR
TS
LS/LDO
BAT
PWM, LDO, and BAT FET
Control
I2C
Interface
Hi-Z
Mode
Device Control
Reset and
Timer
+
+
+
+
VIN
TS COLD
TS HOT
TS WARM
TS COOL
SYS
1C/
0.5C
Disable
Disable
VBATREG
±140mV
LDO/ Load Switch
Control
IINLIM
Q1/Q2 Q3
Q4
VIN_DPM
VSUPPLY
VBATREG
LDO
Control
VSYSREG
Thermal
Shutdown
+
+
Termination
Reference
IBAT
VIN
VINOVP VBAT
VBATOVP
VBATREG ±0.12 V
VBAT
VBAT
VBATSHRT
IBATREG
+
+
+
RESET
Q5
Q7
VOVP
BATOVP
BATSHRT
Recharge
PMID
LDO/ Load Switch
Host Control
Input Current Limit
Charge Current
Termination Current
PG
+VBAT(SC)
SDA
SCL
LSCTRL
ILIM
ISET
IPRETERM
INT
GND
IN
VINLS
CD
Copyright © 2016, Texas Instruments Incorporated
S
D
G
S
D
G
S
D
G
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9.3 Feature Description
9.3.1 Ship Mode
Ship Mode is the lowest quiescent current state for the device. Ship Mode latches off the device and BAT FET
until VIN > VBAT + VSLP or the MR button is depressed for tWAKE1 and released. The following list shows the
events that are active during Ship Mode:
1. VIN_UV Comparator
2. MR Input (No clock or delay in this mode for lowest power consumption)
3. PMID active pull down
9.3.1.1 Ship Mode Entry and Exit
The device may only enter Ship Mode when there is not a valid VIN supply present (VIN < VUVLO). Once the
IN supply is removed there are two ways for the device to enter Ship Mode: through I2C command using the
EN_SHIPMODE bit and by doing a long button press when MRREC bit is set to 0. If the EN_SHIPMODE
bit is set while the IN supply is present, the device will enter Ship Mode upon removal of the supply. The
EN_SHIPMODE bit can be cleared using the I2C interface as well while the IN input is valid.
In addition to VIN < VUVLO, CD and MR must be high. Once all of these conditions are met the device will begin
the transition to Ship Mode. All three conditions must remain unchanged for a period of tQUIET to ensure proper
operation. Figure 9-1 and Figure 9-2 show the correct sequencing to ensure proper entry into the Ship Mode
through I2C command and MR button press respectively.
VIN
MR
CD
Shipmode
I2C
Write
xxxxxx
xxxxxx
xx
tQUIET
Figure 9-1. CD, MR and VIN Sequencing for Ship Mode Entry Through I2C Command
VIN
MR
CD
Shipmode
I2C
Write
xxxxxx
xxxxxx
t > tRESET
tQUIET
Figure 9-2. CD, MR and VIN Sequencing for Ship Mode Entry Through Long MR Button Press
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The end user can enable the device (exit Ship Mode) by connecting an adapter to IN (VIN > VBAT + VSLP) or
by toggling the MR button. Note that in the case where an adapter is connected while the MR is still held low
and immediately after the RESET timer has expired ( MR low for tRESET), the device will not enter Ship Mode,
but may enter it upon adapter removal (Same behavior as setting the EN_SHIPMODE bit when the adapter is
present). This will not be the case if MR has gone high when the adapter is connected or MR continues to be
held low for a period longer than tWAKE1 after the adapter is connected.
To exit Ship Mode through and MR press the battery voltage must be above the maximum programmable
BUVLO threshold when VIN is not present. Once MR goes low, the device will start to exit Ship Mode, powering
PMID. The device will not complete the transition from Ship Mode until MR has been held low for at least tWAKE1.
Only after the transition is complete may the host start I2C communication if the device has not entered High
Impedance Mode.
9.3.2 High Impedance Mode
High Impedance mode is the lowest quiescent current state while operating from the battery. During Hi-Z mode
the SYS output is powered by BAT, the MR input is active, and the LSCTRL input is active. All other circuits are
in a low power or sleep state. The LS/LDO output can be enabled in Hi-Z mode with the LSCTRL input. If the
LS/LDO output has been enabled through I2C prior to entering Hi-Z mode, it will stay enabled. The CD pin is
used to put the device in a high-impedance mode when battery is present and VIN < VUVLO. Drive CD high to
enable the device and enter active battery operation when VIN is not valid. When the HZ_MODE bit is written by
the host, the I2C interface is disabled if only battery is present. To resume I2C, the CD pin must be toggled. If the
supply for the CD pull up glitches or experiences a brownout condition , it is recommended to toggle the /CD pin
to resume I2C communication.. The functionality of the pin is shown in Table 9-1.
Table 9-1. CD, State Table
CD, STATE VIN < VUVLO VIN > VUVLO
L Hi-Z Charge Enabled
H Active Battery Charge Disabled
9.3.3 Active Battery Only Connected
When the battery above VBATUVLO is connected with no input source, the battery discharge FET is turned on.
After the battery rises above VBATUVLO and the deglitch time is reached, the SYS output starts to rise. The
current from PMID and SYS is not regulated, but is protected by a short circuit current limit. If the short circuit
limit is reached for the deglitch time (tDGL_SC), the battery discharge FET is turned off for the recovery time
(tREC_SC). After the recovery time, the battery FET is turned on to test if the short has been removed. If it has not,
the FET turns off and the process repeats until the short is removed. This process protects the internal FET from
over current. During this event PMID will likely droop and cause SYS to go out of regulation.
To provide designers the most flexibility in optimizing their system, an adjustable BATUVLO is provided. When
the voltage drops below the VBATUVLO threshold, the battery discharge FET is turned off. Deeper discharge of
the battery enables longer times between charging, but may shorten the battery life. The BATUVLO is adjustable
with a fixed 150-mV hysteresis.
If a valid VIN is connected during active battery mode, VIN > VUVLO, the supplement and battery discharge FET is
turned on when the battery voltage is above the minimum VBATUVLO.
Drive CD high or write the CE register to disable charge when VIN > VUVLO is present. CD is internally pulled
down. When exiting this mode, charging resumes if VIN is present, CD is low and charging is enabled.
All HOST interfaces ( CD, SDA/SCL, INT, RESET and LSCTRL) are active no later than 5 ms after SYS reaches
the programmed level.
9.3.4 Voltage Based Battery Monitor
The device implements a simple voltage battery monitor which can be used to determine the depth of discharge.
Prior to entering High-Z mode, the device will initiate a VBMON reading. The host can read the latched value for
the no-load battery voltage, or initiate a reading using VBMON_READ to see the battery voltage under a known
load. The register will be updated and can be read 2ms after a read is initiated. The VBMON voltage threshold is
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readable with 2% increments with ±1.5% accuracy between 60% and 100% of VBATREG using the VBMON_TH
registers. Reading the value during charge is possible, but for the most accurate battery voltage indication, it is
recommended to disable charge, initiate a read, and then re-enable charge.
A typical discharge profile for a Li-Ion battery is shown in Table 9-2. The specific battery to be used in the
application should be fully characterized to determine the thresholds that will indicate the appropriate battery
status to the user. Two typical examples are shown below, assuming the VBMON reading is taken with no load
on the battery.
This function enables a simple 5-bar status indicator with the following typical performance with different
VBATREG settings:
Table 9-2. Discharge Profile for a Li-Ion Battery
VBATREG BATTERY FULL 95% to 65%
REMAINING CAPACITY
65% to 35%
REMAINING CAPACITY
35% to 5%
REMAINING CAPACITY BATTERY EMPTY
4.35 V VBMON > 90% VBMON = 88% VBMON = 86% VBMON = 84% VBMON < 82%
4.2 V VBMON > 98% VBMON = 94% or 96% VBMON = 90% or 92% VBMON = 86% or 88% VBMON < 84%
D
E
C
O
D
E
R
S 3
S 2
S 1
S 0
- 2 % BAT TAP
- 4 % BAT TAP
- 6 % BAT TAP
- 8 % BAT TAP
- 10 % BAT TAP
VREF
90 % VB
80 % VB
70 % VB
60 % VB
VB = 0 . 8 VBAT
VBGUAGE_TH<2:0>
Figure 9-3. Voltage Battery Monitor
9.3.5 Sleep Mode
The device enters the low-power sleep mode if the voltage IN falls below the sleep-mode entry threshold and
VIN is higher than the undervoltage lockout threshold. In sleep mode, the input is isolated from the connected
battery. This feature prevents draining the battery during the absence of VIN. When VIN < V(BAT) + VSLP, the
device turns the battery discharge FET on, sends a 128-µs pulse on the INT output, and the FAULT bits of the
register are update over I2C. Once VIN > V(BAT) + VSLP, the device initiates a new charge cycle. The FAULT bits
are not cleared until they are read over I2C and the sleep condition no longer exists. It is not recommended to do
a battery connection or plug in when VUVLO< VIN < VBAT + VSLP as it may cause higher quiescent current to be
drained form the battery.
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