Texas Instruments DLPLCRC910EVM User manual

User's Guide
DLP® DLPC910 Apps FPGA Guide
ABSTRACT
The DLPC910 Apps FPGA Guide describes the functions and registers of the DLPC910 Applications FPGA
(Apps FPGA) designed to work with a DLP LightCrafter DLPC910 EVM (DLPLCRC910EVM) and a supported
DMD EVM. In addition, the guide provides an overview of the VHDL code and implementation.
Table of Contents
1 Introduction.............................................................................................................................................................................4
1.1 Welcome............................................................................................................................................................................ 4
2 Overview..................................................................................................................................................................................5
2.1 Purpose..............................................................................................................................................................................5
2.2 Apps FPGA Hardware Target.............................................................................................................................................5
3 Interfaces.................................................................................................................................................................................6
3.1 LVDS high speed data interface to DLPC910.................................................................................................................... 6
3.1.1 DLP9000X and DLP9000XUV.....................................................................................................................................6
3.1.2 DLP6500......................................................................................................................................................................6
3.2 Data Load Control Signals to DLPC910.............................................................................................................................6
3.3 DMD Reset and Block Clear Signals to the DLPC910.......................................................................................................7
3.4 DLPC910 Initialization and Controller Reset Signals......................................................................................................... 7
3.5 Apps FPGA Reset Signal - apps_resetz .......................................................................................................................7
3.6 DLPC910 Status-Info Signals............................................................................................................................................ 7
3.7 USB GPIF (Interface)......................................................................................................................................................... 8
3.7.1 Apps FPGA Register Address Read-Write Transactions............................................................................................ 8
3.7.2 FIFO Write Transaction..............................................................................................................................................11
3.8 DLPLCRC910EVM Dip Switch (SW2)..............................................................................................................................11
3.9 VC-707 Dip Switch (SW2)................................................................................................................................................12
3.10 VC-707 Push Button Switches....................................................................................................................................... 12
3.11 VC-707 Status LEDs...................................................................................................................................................... 12
3.12 DLPLCRC910EVM Apps FPGA Test Points.................................................................................................................. 13
4 Operation...............................................................................................................................................................................14
4.1 Initialization...................................................................................................................................................................... 14
4.1.1 Initialization Prompts................................................................................................................................................. 14
4.1.2 Init Routine................................................................................................................................................................ 15
4.1.3 GPIO Status LEDs.....................................................................................................................................................15
4.1.4 Errors.........................................................................................................................................................................15
4.2 Test Pattern Generator (TPG) and Apps Loader - DLP Control.......................................................................................15
4.2.1 Test Pattern Generator (TPG)................................................................................................................................... 16
4.2.2 DMD Data Buffer....................................................................................................................................................... 16
4.2.3 DMD Load State Machine......................................................................................................................................... 16
4.2.4 DMD Reset State Machine........................................................................................................................................ 18
4.2.5 DMD Load Parameters..............................................................................................................................................18
4.2.6 Synchronization Pulse............................................................................................................................................... 18
4.3 User DLP Control............................................................................................................................................................. 18
4.3.1 DLP6500 (1920 x 1080) User Image Display Example (Global)............................................................................... 19
4.3.2 DLP9000X (2560 x 1600) User Image Display Example (Global).............................................................................20
4.3.3 Load4 - Using with DLP6500 DMD............................................................................................................................20
4.3.4 USB GPIF FIFO Data Writes.....................................................................................................................................20
4.3.5 External Trigger......................................................................................................................................................... 20
4.4 USB GPIF (Operation)..................................................................................................................................................... 21
4.5 Clocks and Resets........................................................................................................................................................... 21
4.5.1 Reference Clocks...................................................................................................................................................... 21
4.5.2 Clk50 and Clk100...................................................................................................................................................... 21
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4.5.3 DLP Clocks................................................................................................................................................................21
4.5.4 USB GPIF Clock........................................................................................................................................................21
4.5.5 Logic Resets..............................................................................................................................................................21
4.5.6 Clock Domain Crossings (CDC)................................................................................................................................ 22
4.6 Switch Debounce............................................................................................................................................................. 22
5 USB GPIF Registers............................................................................................................................................................. 23
5.1 Register Definitions.......................................................................................................................................................... 23
5.1.1 Status (0x000C).........................................................................................................................................................23
5.1.2 Data Loading Control (0x0010)................................................................................................................................. 24
5.1.3 Test Pattern Control (0x0014)....................................................................................................................................24
5.1.4 Test Row Address (0x0018) - [Unused].....................................................................................................................25
5.1.5 Loader Reset Type (0x001C).................................................................................................................................... 25
5.1.6 Type and Version (0x0020)........................................................................................................................................25
5.1.7 User Image Buffer Write Settings (0x0024)............................................................................................................... 25
5.1.8 USB GPIF FIFO Read Burst Size (0x0028) - [Obsolete]...........................................................................................26
5.1.9 User Row Command Register (0x002C)................................................................................................................... 26
5.1.10 User Block Command Register (0x0030)................................................................................................................ 26
5.1.11 Loader Row Control (0x0034)..................................................................................................................................27
5.1.12 Loader Load Interval (0x0038)................................................................................................................................ 27
5.1.13 Loader Expose Time (0x003C)................................................................................................................................27
5.1.14 Address Write (0x003F) - [Unused]......................................................................................................................... 27
5.1.15 Loader Control (0x0040)..........................................................................................................................................27
5.1.16 Park [PWR_FLOAT] (0x0044)................................................................................................................................. 28
5.1.17 External Trigger Status (0x0048).............................................................................................................................28
5.1.18 FPGA Build Date (0x0080)...................................................................................................................................... 28
5.1.19 Major-Minor Revision (0x0084)............................................................................................................................... 28
5.1.20 Fixed Value FPGA Identifier (0x0088)..................................................................................................................... 28
5.1.21 Test Register (0x008C)............................................................................................................................................28
6 FPGA Configuration............................................................................................................................................................. 29
7 Apps FPGA Source Files and Compilation........................................................................................................................ 30
7.1 Design Tools ....................................................................................................................................................................30
7.2 Source Files..................................................................................................................................................................... 30
7.2.1 Primary VHDL and IP Modules..................................................................................................................................30
7.2.2 Modules with Multiple Instantiations.......................................................................................................................... 31
7.2.3 VHDL Packages........................................................................................................................................................ 31
7.2.4 Vivado Constraints.....................................................................................................................................................31
7.2.5 Memory IP Initialization Files.....................................................................................................................................31
7.3 Building the Apps FPGA Code.........................................................................................................................................31
7.3.1 Source Code..............................................................................................................................................................31
7.3.2 Creating the Vivado Project.......................................................................................................................................32
7.3.3 Compiling the Design................................................................................................................................................ 32
7.3.4 Simulation..................................................................................................................................................................32
8 Related Documentation from Texas Instruments.............................................................................................................. 35
9 Appendix................................................................................................................................................................................35
9.1 Abbreviations and Acronyms........................................................................................................................................... 35
9.2 Information About Cautions and Warnings.......................................................................................................................36
List of Figures
Figure 2-1. Apps FPGA Hardware Target....................................................................................................................................5
Figure 3-1. Register Address Transaction Timing Diagram.........................................................................................................9
Figure 3-2. Register Data Write Transaction Timing Diagram..................................................................................................... 9
Figure 3-3. Register Data Read Transaction Timing Diagram...................................................................................................10
Figure 3-4. FIFO Write Transaction Timing Diagram................................................................................................................. 11
Figure 4-1. Apps FPGA Functional Block Diagram................................................................................................................... 14
Figure 4-2. Apps Loader Data Flow...........................................................................................................................................15
Figure 4-3. DMD Load State Machine....................................................................................................................................... 17
Figure 7-1. Source Files............................................................................................................................................................ 30
Figure 7-2. Test Benches...........................................................................................................................................................33
Figure 7-3. Settings Dialog........................................................................................................................................................ 33
Figure 7-4. Vivado Waveform Window...................................................................................................................................... 34
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List of Tables
Table 3-1. Apps FPGA - LVDS data interface output signal names.............................................................................................6
Table 3-2. Data Load Control Signals.......................................................................................................................................... 6
Table 3-3. Reset and Block Clear Signals................................................................................................................................... 7
Table 3-4. DLPC910 Initialization and Controller Reset Signals..................................................................................................7
Table 3-5. DLPC910 Status-Info Signals..................................................................................................................................... 7
Table 3-6. USB GPIF Interface Signals....................................................................................................................................... 8
Table 3-7. USB GPIF Transaction Type Definition.......................................................................................................................8
Table 3-8. Register Address Transaction Example......................................................................................................................9
Table 3-9. Register Data Write Transaction Example................................................................................................................ 10
Table 3-10. Register Data Read Transaction Example..............................................................................................................10
Table 3-11. DLPLCRC910EVM Dip Switch (SW2).....................................................................................................................11
Table 3-12. VC-707 Dip Switch (SW2).......................................................................................................................................12
Table 3-13. VC-707 Push Button Switches................................................................................................................................12
Table 3-14. VC-707 Status LEDs...............................................................................................................................................12
Table 3-15. DLPLCRC910EVM Apps FPGA Test Points...........................................................................................................13
Trademarks
Virtex™ and Vivado™ are trademarks of AMD.
All trademarks are the property of their respective owners.
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DLP® DLPC910 Apps FPGA Guide 3
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1 Introduction
The DLPC910 Apps FPGA code provides functionality and an example of interfacing to a DLPC910 controller
and supported DMD. The DLPC910 Apps FPGA Guide details the functions and registers of the DLPC910
Applications FPGA (Apps FPGA) as well as the organization of the VHDL code used to create.
1.1 Welcome
The DLP LightCrafter DLPC910 EVM (DLPLCRC910EVM) is a great way to evaluate the highest bandwidth data
rates the DLP chip portfolio offers. Designers get pixel-accurate control of all DMD micromirrors with Global,
Quad, Dual and Single Block Modes available for tailoring DMD micromirror pattern timing for continuous (lamp)
or solid state (switched) illuminated applications.
The DLPC910 Apps FPGA implementation enables exploration of the capabilities of the DLPLCRC910EVM and
supported DMDs such as the DLP6500, DLP9000X, and DLP9000XUV
The DLPLCRC910EVM is also a path for customers to design with the high-performance DLP9000XUV chip for
systems such as:
• Lithography
• 3D printing and additive manufacturing
• Dynamic grayscale marking and coding
• Industrial printing
• Structured light such as:
– Factory automation and 3D machine vision
– 3D In-line automated optical inspection (AOI)
– Robotic vision
– Offline 3D metrology
– 3D scanners
– 3D identification and biometrics
• Medical and life sciences
• High-speed imaging and display
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2 Overview
2.1 Purpose
This document describes the functions and registers of the DLPC910 Applications FPGA (Apps FPGA). An
overview of the VHDL code is also provided.
2.2 Apps FPGA Hardware Target
The apps FPGA reference code is targeted to the AMD Xilinx Virtex™-7 FPGA housed on an AMD Xilinx
VC-707 Evaluation Board. As shown in Apps FPGA Hardware Target, the VC-707 Evaluation Board connects
to the Texas Instruments (TI) DLPC910 Evaluation Module (DLPLCRC910EVM), which connects to one of three
available TI DMD boards.
Figure 2-1. Apps FPGA Hardware Target
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3 Interfaces
This section describes the apps FPGA interface signals. Apps FPGA interfaces to the DLPC910 EVM board
through two high pin count FMC connectors (J500 and J501 on the DLPLCRC910EVM board). In addition to
the DLPC910 interfaces, the apps FPGA uses push button switches, dip switches, and LEDs on the VC-707
evaluation board.
Apps FPGA interface signal pin numbers and signal properties are described in the input-output (IO) physical
constraints (.xdc) file provided with the Apps FPGA source code.
Signal names used in this section match the signal names used in the Apps FPGA top level VHDL module.
3.1 LVDS high speed data interface to DLPC910
The Apps FPGA drives image data to the DLPC910 over VC-707 FMC HPC1 connector, consisting of four, 16
data pair, LVDS buses. Each of the four buses also has their own clock and data valid signal pairs. Signal level,
timing, and data mapping details can be found in the DLPC910 data sheet.
Apps FPGA output signal names for the LVDS data interface to the DLPC910 are summarized in Apps FPGA -
LVDS data interface output signal names.
Table 3-1. Apps FPGA - LVDS data interface output signal names
LVDS Bus A LVDS Bus B LVDS Bus C LVDS Bus D
Data dout_ap(15:0)
dout_an(15:0)
dout_bp(15:0)
dout_bn(15:0)
dout_cp(15:0)
dout_cn(15:0)
dout_dp(15:0)
dout_dn(15:0)
Clock dclk_ap
dclk_an
dclk_bp
dclk_bn
dclk_cp
dclk_cn
dclk_dp
dclk_dn
Data Valid dvalid_ap
dvalid_an
dvalid_bp
dvalid_bn
dvalid_cp
dvalid_cn
dvalid_dp
dvalid_dn
3.1.1 DLP9000X and DLP9000XUV
The Apps FPGA sends data to DLPC910 over all four (A,B,C,D) LVDS data buses when a DLP9000X or
a DLP9000XUV DMD is in use. At startup, the Apps FPGA determines the connected DMD Type using
dmd_type(3:0) input from the DLPLCRC910EVM, and drives the appropriate number of LVDS buses.
Additionally, at startup, the Apps FPGA sets the interface clock speed to either 400 MHz or 480 MHz according
to dmd_speed_sel(1:0) input from the DLPLCRC910EVM.
Note
Although the DLP9000X and DLP9000XUV run at 400 MHz, only 480 MHz operation has been fully
validated.
3.1.2 DLP6500
The Apps FPGA sends data to the DLPC910 over LVDS data buses A and B when a DLP6500 DMD is in use.
The Apps FPGA determines the connected DMD using dmd_type(3:0) input. For a DLP6500 DMD, clock
frequency is fixed to 400 MHz.
3.2 Data Load Control Signals to DLPC910
Data load control signals listed in Table 3-2 are output to the DLPC910 over VC-707 FMC connectors. Signal
function is described in the DLPC910 data sheet.
Table 3-2. Data Load Control Signals
Name Apps FPGA I/O Function
rowmd(1:0) out DMD row mode
rowad(10:0) out DMD row address
comp_data out Complement data
load4z out DMD load 4 function enable (active low)
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Table 3-2. Data Load Control Signals (continued)
Name Apps FPGA I/O Function
ns_flip out Top/bottom image flip on DMD
3.3 DMD Reset and Block Clear Signals to the DLPC910
Table 3-3 lists the DMD Reset and Block Clear signals to and from the DLPC910. These signals connect through
the VC-707 FMC connectors. Refer to the DLPC910 data sheet for additional information.
Table 3-3. Reset and Block Clear Signals
Name Apps FPGA I/O Function
blkad(3:0) out block address
blkmd(1:0) out block mode
rst2blkz out dual and quad block control
wdt_enablez out DMD reset pulse watch dog timer enable
rst_active in DMD mirror clocking pulse (MCP) in progress
3.4 DLPC910 Initialization and Controller Reset Signals
Table 3-4 describes the initialization signals for the DLPC910 controller. See the DLPC910 data sheet for
additional signal information.
Table 3-4. DLPC910 Initialization and Controller Reset Signals
Name Apps FPGA I/O Function
ctrl_rstz out DLPC910 controller reset
pwr_floatz out DLPC910 PWR_FLOAT
ecp2_finished in DLPC910 configuration from SPI Flash status
init_active in DLPC910 initialization active status
3.5 Apps FPGA Reset Signal - apps_resetz
Signal apps_resetz originates from a push button switch (SW1 APP RST) on the DLPLCRC910EVM board.
When the switch is pressed the apps_resetz signal goes low, causing the init-run-park state machine in the
apps FPGA to drive pwr_floatz low to park the DMD mirrors. Upon release of the push button switch, the
init-run-park state machine re-initializes the DLPC910 controller and resets the Apps FPGA logic.
3.6 DLPC910 Status-Info Signals
DLPC910 status-info signals are listed in Table 3-5. The ddc_version, DMD_type, and DMD_irq signals are
from the DLPC910 controller. Only DMD_type is used by the Apps FPGA logic. The version and irq signals are
made available in status registers via the USB GPIF.
The DMD_speed_sel signal is from a set of jumpers on the DLPLCRC910EVM board. The jumper settings are
used by DLPC910 controller and by Apps FPGA to determine clock frequency of the LVDS high speed interface
DLP9000X and DLP9000XUV.
Reference the DLPC910 data sheet for additional information.
Table 3-5. DLPC910 Status-Info Signals
Name Apps FPGA I/O Function
ddc_version(2:0) in DLPC910 firmware version
dmd_type(3:0) in DLPC910 DMD type
dmd_speed_sel(1:0) in Apps/DLPC910 LVDS speed select jumpers
dmd_irq in DMD irq status signal
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3.7 USB GPIF (Interface)
The USB GPIF port provides access to Apps FPGA internal control-status registers. The USB GPIF port also
provides a data input FIFO used for loading the user image buffer with user images for display. Table 3-6
describes the signals in the interface.
Table 3-6. USB GPIF Interface Signals
Name Apps FPGA I/O Function
gpif_addr(8:0) in Not used
usb_fd(15:0) in/out USB GPIF data, bi-directional
usb_ctrl(5:3) in USB GPIF control – not used(1)
usb_ctrl(2:0) in USB GPIF control, identifies transaction type
usb_rdy(2:1) out USB GPIF ready outputs – not used(2)
usb_rdy(0) out USB GPIF ready output 0(3)
usb_reset out Not used – apps FPGA drives low always
usb_if_clock in USB GPIF clock, 48 MHz
(1) usb_ctrl(5:3) inputs are not used.
(2) usb_rdy(2:1) outputs are always driven low.
(3) usb_rdy(0) is the empty flag of the USB GPIF input FIFO.
The type of GPIF transaction is defined by usb_ctrl(2:0) as shown in Table 3-7.
Table 3-7. USB GPIF Transaction Type Definition
Signal Idle Address Data write Data read FIFO burst
usb_ctrl(2) 1 0 0 0 1
usb_ctrl(1) 1 1 1 0 1
usb_ctrl(0) 1 1 0 1 0
3.7.1 Apps FPGA Register Address Read-Write Transactions
Reading or writing Apps FPGA registers requires first sending a register address followed by register data.
Register addresses and data are 32 bits in width. Two 16-bit bus transactions are required to transfer 32 bits.
Note
Data is sampled on the falling edges of the usb_if_clk.
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3.7.1.1 Apps FPGA Register Address Transaction
Register address transaction timing is shown in Register Address Transaction Timing Diagram.
One Clock
Cycle
usb_if_clock
Idle One Clock
Cycle
usb_fd(15:8)
usb_fd(7:0)
usb_ctrl(2:0)
Address
Byte 1
Address
Byte 0
Write Address
011b
Address
Byte 3
Address
Byte 2
Write Address
011b
(48 MHz)
Idle Idle
Address Low Address High
111b 111b 111b 111b111b
Figure 3-1. Register Address Transaction Timing Diagram
A register address transaction example is shown in Register Address Transaction Example. There can be more
than one idle clock cycle between address transfers. The address transaction table shows an address transfer of
0x00010228.
Table 3-8. Register Address Transaction Example
Signal Idle Write low address Idle Write high address Idle
usb_if_clock 1 clock cycle 1 clock cycle
usb_fd(15:8) 0x00 0x02 0x00 0x00 0x00
usb_fd(7:0) 0x00 0x28 0x00 0x01 0x00
usb_ctrl(2:0) Idle Address – “011” Idle Address – “011” Idle
3.7.1.2 Apps FPGA Register Data Write Transaction
Register data write transaction timing is shown in Register Data Write Transaction Timing Diagram.
One Clock
Cycle
usb_if_clock
Idle One Clock
Cycle
usb_fd(15:8)
usb_fd(7:0)
usb_ctrl(2:0) 111b 111b 111b
(48 MHz)
Idle Idle
Data Low Data High
111b111b
Data
Byte 1
Data
Byte 0
Data Write
010b
Data
Byte 3
Data
Byte 2
Data Write
010b
Figure 3-2. Register Data Write Transaction Timing Diagram
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A register data write transaction example is shown in Register Data Write Transaction Example. A register write
data value of 0x04030201 is being transferred.
Table 3-9. Register Data Write Transaction Example
Signal Idle Write low word Idle Write high word Idle
usb_if_clock 1 clock cycle 1 clock cycle
usb_fd(15:8) 0x00 0x02 0x00 0x04 0x00
usb_fd(7:0) 0x00 0x01 0x00 0x03 0x00
usb_ctrl(2:0) Idle Data wrt – “010” Idle Data wrt – “010” Idle
3.7.1.3 Apps FPGA Register Data Read Transaction
Register read word transactions are 3 clocks in length. Register data read transaction timing is shown in
Register Data Read Transaction Timing Diagram.
Two Clock
Cycles
usb_if_clock
Idle
usb_fd(15:8)
usb_fd(7:0)
usb_ctrl(2:0) Data Read
001b
111b
(48 MHz)
Read Low
Word
111b Data Read
001b
Start Low
Word Read
Data Read
001b
111b
Idle
One Clock
Cycle
Data Read
001b
Two Clock
Cycles
Data Read
001b 111b
Idle
One Clock
Cycle
Data Read
001b
Read High
Word
Start High
Word Read
111b
Data
Byte 1
Data
Byte 0
Data
Byte 3
Data
Byte 2
Figure 3-3. Register Data Read Transaction Timing Diagram
The Apps FPGA GPIF supports multiple register read transactions from the previously written register address,
without needing a new address transaction. This lowers the time overhead when polling a status register.
A Register read word transaction example is shown in Register Data Read Transaction Example and illustrates
reading of register value 0x04030201.
Table 3-10. Register Data Read Transaction Example
Signal Idle Start low word
read
Read low word Idle Start high word
read
Read high word Idle
usb_if_clock 2 clock cycles 1 clock cycle 2 clock cycles 1 clock cycle
usb_fd(15:8) 0x00 -- 0x02 0x00 -- 0x04 0x00
usb_fd(7:0) 0x00 -- 0x01 0x00 -- 0x03 0x00
usb_ctrl(2:0) Idle Data read– “001” Data read– “001” Idle Data read– “001” Data read – “001” Idle
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3.7.2 FIFO Write Transaction
The USB GPIF FIFO is used to transfer image data from the USB GPIF to the user image buffer in the Apps
FPGA. The FIFO size is 256 words of 16 bits each. FIFO write transactions are always 256 words (512 bytes) in
length.
FIFO write transaction timing is shown in FIFO Write Transaction Timing Diagram.
usb_if_clock
Idle
usb_fd(15:8)
usb_fd(7:0)
usb_ctrl(2:0) 111b
(48 MHz)
Word Writen
111b
Word Write0
253 Clock
Cycles Idle
One Clock
Cycle
One Clock
Cycle
One Clock
Cycle
Data
Byte 1
Data
Byte 0
FIFO Write
110b
Data
Byte 3
Data
Byte 2
FIFO Write
110b
Data
Byte 2n+1
Data
Byte 2n
FIFO Write
110b
Word Write1
Data
Byte 511
Data
Byte 510
FIFO Write
110b
Word Write255
111b 111b
Figure 3-4. FIFO Write Transaction Timing Diagram
3.8 DLPLCRC910EVM Dip Switch (SW2)
The DLPLCRC910EVM houses a dip switch (SW2) whose switch settings are used by the Apps FPGA as
described in Table 3-11.
Note
The inputs connected to DLPLCRC910EVM SW2 are pulled high through a pullup resistor when in the
"OFF" position [logic 1] and pulled low when in the "ON" position [logic 0]. Positions 0 and 1 are not
enabled when the switch is "OFF" [logic 1] and positions 2, 3, and 7 are not enabled when "ON" [logic
0].
Table 3-11. DLPLCRC910EVM Dip Switch (SW2)
Signal Switch Label Function Default Position(1)
evm_in_dip_sw(7) 8 wdt_enblz(2) ON [logic 0]
evm_in_dip_sw(6) 7 not used ON [logic 0]
evm_in_dip_sw(5) 6 not used ON [logic 0]
evm_in_dip_sw(4) 5 not used ON [logic 0]
evm_in_dip_sw(3) 4 ns_flip(2) ON [logic 0]
evm_in_dip_sw(2) 3 comp_data(2) ON [logic 0]
evm_in_dip_sw(1) 2 load4_enz(2) OFF [logic 1]
evm_in_dip_sw(0) 1 pwr_float(3) OFF [logic 1]
(1) Default Positions are as seen on the physical switch.
(2) Instructs the Apps FPGA to perform the function as described in DLPC910 data sheet. These functions are replicated in register
0x0010 (section Data Loading Control (0x0010)).
(3) Instructs the Apps FPGA to issue pwr_floatz to DLPC910. This function is replicated in register 0x0044 (section Park
[PWR_FLOAT] (0x0044)).
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3.9 VC-707 Dip Switch (SW2)
The VC-707 EVM board houses a dip switch (SW2 GPIO DIP SW) whose switch settings are used by the Apps
FPGA as described in Table 3-12. For normal operation, set position 0 to ON, all other switches to OFF.
Table 3-12. VC-707 Dip Switch (SW2)
Signal Switch Label Function Default Position
vc707_in_dip_sw(7) 8 not used OFF
vc707_in_dip_sw(6) 7 not used OFF
vc707_in_dip_sw(5) 6 alt_rows_sel(1) OFF
vc707_in_dip_sw(4) 5 not used OFF
vc707_in_dip_sw(3) 4 not used OFF
vc707_in_dip_sw(2) 3 not used OFF
vc707_in_dip_sw(1) 2 not used OFF
vc707_in_dip_sw(0) 1 USB GPIF FIFO input word
swap(2)
ON
(1) When position 6 switch is ON, a horizontal line pattern (all 0’s even rows, all 1’s odd rows) is inserted after the test pattern buffer. Used
for debug only.
(2) When position 1 switch is ON, even input 16-bit words are swapped with odd input 16-bit words, before writing to the USB GPIF FIFO.
The DLPLCRC910EVM implementation requires this setting to be enabled (ON).
3.10 VC-707 Push Button Switches
The VC-707 EVM houses push button switches whose switch inputs are used by the Apps FPGA as described in
Table 3-13.
Table 3-13. VC-707 Push Button Switches
Signal Switch Label Function
vc707_in_pb_sw(7) SW7 Not used
vc707_in_pb_sw(6) SW6 Not used
vc707_in_pb_sw(5) SW5 Debounced external trigger test(1)
vc707_in_pb_sw(4) SW4 Reset for init-run-park – debug only
vc707_in_pb_sw(3) SW3 Test pattern cycling(2)
(1) A debounced SW5 on the VC-707 board is made available to use as a test external trigger on the Apps FPGA test header (J3-pin 3 on
DLPLCRC910EVM board). To test the external trigger using SW5 short J3-pin 2 to J3-pin3.
(2) When the Apps FPGA starts up, test patterns are sent to the DLPC910 for display on DMD. Test patterns change periodically (current
default is two seconds). Pressing SW3 halts test pattern cycling. Subsequent presses of SW3 changes to the next test pattern. SW3
controlled pattern sequencing is ended by pressing the Apps FPGA reset switch on the DLPLCRC910EVM board.
3.11 VC-707 Status LEDs
The apps FPGA uses the VC-707 GPIO LEDs to indicate initialization & operating modes as described in Table
3-14.
Table 3-14. VC-707 Status LEDs
Signal LED Label Function
vc707_led_ds(9) 7ON = dmd_type of 0xF, DLP9000X or
DLP9000XUV
vc707_led_ds(8) 6ON = dmd_type of 0xE, DLP6500
vc707_led_ds(7) 5 Spare
vc707_led_ds(6) 4 Spare
vc707_led_ds(5) 3 ON = USB GPIF clock PLL locked(1)
vc707_led_ds(4) 2ON = pwr_floatz asserted, system parked
vc707_led_ds(3) 1 ON = Initialization complete, system running
vc707_led_ds(2) 0 ON = Initialization error(2)
(1) GPIO LED 3 is illuminated when the USB GPIF PLL is locked to the input clock, usb_if_clk, from the Infineon - Cypress USB
interface chip.
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(2) GPIO LED 0 is illuminated by the init-run-park state machine when anomalies occur during DLPC910 initialization.
3.12 DLPLCRC910EVM Apps FPGA Test Points
The DLPLCRC910EVM houses a dip switch (SW2) whose switch settings are used by the Apps FPGA as
described in Table 3-15.
Table 3-15. DLPLCRC910EVM Apps FPGA Test Points
Signal J3 pin Apps FPGA signal
APP_TSTPT7 2 External global reset trigger input for user
control
APP_TSTPT6 3 Debounced VC707 push button switch SW5
output
APP_TSTPT5 4 Data enable from the apps loader, output
APP_TSTPT4 5 Load busy from the apps loader, output
APP_TSTPT3 6 Mirror settling busy from the apps loader,
output
APP_TSTPT2 7 Expose trigger from the apps loader, output
APP_TSTPT1 8 Mirror reset busy from the apps loader finite
state machine (FSM), output
APP_TSTPT0 9 Reset active signal, output(1)
(1) Reset active signal does not go high during a Mirror Float operation
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4 Operation
A functional block diagram of the Apps FPGA is shown in Figure 4-1. The overlay colors highlight the VHDL
modules that perform each set of functions, with VHDL module names in italics.
Figure 4-1. Apps FPGA Functional Block Diagram
The Apps FPGA has three operating states:
1. Initializing
2. Initialization error
3. Run
a. Test pattern / Apps DLP load control
b. User DLP load control
The Apps FPGA performs initialization and responds to initialization errors, as described in the Loader Control
(0x0040) section. Once initialization is complete, the run state begins. In the run state, there are two independent
DLP control methods selected by bit zero of the loader control register (Loader Control (0x0040)). The first is the
test pattern Apps FPGA loader control of the DLP component set. The second is when the Apps FPGA loader is
not in control, the DLP component set can be controlled through the USB GPIF interface (user control mode).
4.1 Initialization
The Apps FPGA provides the DLPC910 and attached DMD chip set initialization per the DLPC910 data sheet
requirements. VHDL module irp.vhd (init-run-park control) and the sub-module irp_fsm.vhd (init-run-park state
machine) provide this startup logic.
4.1.1 Initialization Prompts
Any of the following events cause the init-run-park state machine to execute the initialization routine:
1. Completion of the Apps FPGA configuration.
2. Pressing SW1 APP RST switch on DLPLCRC910EVM (apps_resetz to the Apps FPGA).
3. ON to OFF transition by position 1 of dip switch SW2 on DLPLCRC910EVM (un-parking the system using
dip switch).
4. ‘1’ to ‘0’ transition of park bit in USB GPIF register 0x0044 (for example, un-parking the system using register
command bit).
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4.1.2 Init Routine
The init routine performed by the VC-707 consists of the following basic steps:
1. Issue reset to the DLPC910 controller (ctrl_rstz).
2. Verify that DLPC910 is configured (ecp2_finished).
3. Ensure Apps FPGA DLP PLLs are locked (dclk_ap/n).
4. Capture the selected DLPC910 interface clock speed (dmd_speed_sel).
5. Select either 400 or 480 MHz clock based on the value read from dmd_speed_sel.
6. Reset the AMD / Xilinx oserdes output primitives.
7. Ensure DLPC910 begins the initialization (init_active).
8. Turn on DLPC910 training pattern.
9. Release reset to DLPC910 (ctrl_rstz).
10. Wait for training to complete (init_active low).
11. Capture the type of DMD (dmd_type).
12. Reset Apps FPGA control logic (automatic).
13. Run.
Upon successful init completion, the init-run-park state machine enters the RUN state. From there, the USB
GPIF park register, switch SW1 APP RST, and position 1 of SW2 are monitored. If any one of these inputs
indicates mirrors require parking, then pwr_floatz is issued, and the state machine waits for these inputs to
return to an operating state, before running the init routine again.
Note
A change to the dmd_speed_sel jumpers on the DLPLCRC910EVM requires re-running initialization
(press SW1 APP RST switch).
4.1.3 GPIO Status LEDs
Three VC-707 board GPIO LEDs are used to give init-run-park status:
• GPIO LED 1 is illuminated when in the RUN state
• GPIO LED 2 is illuminated when DMD mirrors are parked
• GPIO LED 0 is illuminated when there is an initialization error
4.1.4 Errors
The initialization error flag is raised if any of the following occur:
1. DLPC910 does not issue ecp2_finished.
2. Apps FPGA DLP PLLs not locked.
3. DLPC910 init_active behavior is not as expected.
4. Mis-match between selected clock speed and DMD type.
Once an init error flag is raised, the init-run-park state machine stays in error state until reset (SW2 APP RST),
upon which another initialization is attempted.
4.2 Test Pattern Generator (TPG) and Apps Loader - DLP Control
When the apps loader is controlling the DLP component set, basic data flow is as shown in Apps Loader Data
Flow. The test pattern generator (TPG), data buffer, and apps loader control functions are all contained in VHDL
module dlp_ctl_n_tpg.vhd.
Test Pattern
Generator Data Buffer To DLPC910
Figure 4-2. Apps Loader Data Flow
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4.2.1 Test Pattern Generator (TPG)
Test pattern generation is provided by VHDL module tpg.vhd along with the sub-modules tpg_trig.vhd and
tpg_timing.vhd. A VHDL package tpg_pkg.vhd provides test data constants for various test patterns.
After apps FPGA initialization is complete, 16 test patterns (section Test Pattern Control (0x0014)) are
continuously cycled through periodically. Modify the cycle interval field of the test pattern control register (Test
Pattern Control (0x0014)) to change the cycling rate. The test pattern control register also provides control bits to
disable pattern cycling and continuously display a selected test pattern.
When test patterns are cycling after initialization, pressing momentary push button switch SW3 on the VC-707
board stops the pattern cycling. Successive activation of SW3 selects the next test pattern in the sequence.
Pressing the Apps FPGA reset switch on the DLPLCRC910EVM board re-initializes the Apps FPGA and DLP
component set and return to auto pattern cycling.
The test pattern generator provides control and addressing to write test patterns into the DMD data buffer.
Patterns are read from the data buffer and sent to the DLPC910 under control of the DMD load state machine.
4.2.2 DMD Data Buffer
The DMD data buffer is comprised of five instantiations of a 512x1600x1 dual port RAM. The dual port RAM is
created using the AMD Xilinx Block Memory Generator tool, accessible from the IP catalog in the AMD Vivado™
GUI. The VHDL module dmd_data_buffer.vhd provides the dual port data buffer function.
The DLP6500 uses only four of the five instantiations.
4.2.3 DMD Load State Machine
VHDL module, dmd_load_fsm.vhd, performs the DLPC910 test pattern data load function (“loader” function).
The loader reads test pattern data from the DMD data buffer, formats the data, and sends the data to the
data_ctl_out.vhd module for serialization and buffering to the DLPC910. In addition, the appropriate row address,
row command, and DVALID control signals are created to send along with the data.
By default, the loader loads test pattern images in response to a load trigger pulse from the dload_trigger.vhd
module. The default period for the trigger pulse is 400 us. The loader load interval register provides the capability
to change the trigger period. Section 5.1.12.
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dmd_load_fsm.vhd
dload_trigger.vhd
Data Bu

er
= Interval?
Y
N
Serialized Data
row address
row command
DVALID
data_ctl_out.vhd
Formaed Data
DLPC910
Figure 4-3. DMD Load State Machine
When the reset type is global or quad-block phased, the loader can be put into free-run mode, where the load
trigger is ignored and the loader loads images successively, and as quickly as possible. The free-run mode
demonstrates the minimum DLP component set image load times. Loader Control (0x0040)
The following loader control settings are configurable through USB GPIF registers:
1. Reset type. Default is global. See Loader Reset Type (0x001C).
2. Starting DMD row and number of DMD rows to load. Default is row 0 and full device load. See Loader Row
Control (0x0034).
3. Expose time. Default is 0. See Loader Expose Time (0x003C).
4. Data loading control. See Data Loading Control (0x0010) for default values.
Note
To avoid unpredictable results when the loader is in free-run mode, do not change the above loader
control settings. To see the effect of changing the above settings in free-run mode, exit free-run mode,
modify settings, then re-enter free-run mode.
Once a full image is loaded, or a single mirror block is loaded, the loader sends mirror reset request to the
phased DMD reset state machine. The loader uses DLP6500 and DLP9000X look up tables, addressable by the
current device row number, to determine on which rows to send phased reset requests.
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4.2.4 DMD Reset State Machine
The phased reset state machine, phase_dmd_reset_fsm.vhd, processes mirror reset requests from the loader
state machine. The state machine processes requests for global and phased resets, issuing the required block
mode and block address commands to the DLPC910 controller.
After issuing a block command, the state machine monitors rst_active from the DLPC910 controller. Once
rst_active goes high then returns to a low state, a mirror settling time interval is executed before indicating
the reset request is complete.
A small FIFO is used to queue reset commands for cases where back-to-back phased reset requests occur.
These are likely to occur when loading an image that has a resolution of 1 mirror block plus 1 DMD row. The
reset for the block is requested, and then 1 row later another reset is requested for the next block.
4.2.5 DMD Load Parameters
The DMD load parameters module, dmd_load_params.vhd, selects load parameters from the package file,
dmd_params_pkg.vhd, based on the DMD type. The selected data is used by the loader state machines for
resolution and timing settings.
Refer to the DLPC910 data sheet for resolution and timing details.
4.2.6 Synchronization Pulse
Both the loader and DMD reset state machines synchronize their operation to an internal sync pulse in the Apps
FPGA. The pulse is one clkd cycle in width. The pulse period varies by dmd_type. For the DLP9000X devices,
there is one sync pulse every five clkd cycles. For the DLP6500, there is one sync pulse every eight clkd
cycles. For each DMD type, the period indicates the row cycle time – the time required to load data and issue
row-block command for a given DMD row.
The row command and block command state machines in the user DLP control logic also time their operation to
the row cycle sync pulse.
4.3 User DLP Control
The Apps FPGA provides users the ability to load images to the DLPC910 - DMD chip set over the USB GPIF.
Two VHDL modules provide the user control, ugpif.vhd and dlp_ctl_ugpif.vhd. A full resolution, 1-bit deep, dual
port RAM buffer is provided to store an image.
The basic steps to display a user image on DMD are:
1. Write image data to user image buffer (USB GPIF FIFO write transfers, FIFO Write Transaction).
2. Send USB GPIF row commands to load buffer data to DLPC910 - DMD (User Row Command Register
(0x002C)).
3. Send USB GPIF block commands to create mirror control pulses to display image data (User Block
Command Register (0x0030)).
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4.3.1 DLP6500 (1920 x 1080) User Image Display Example (Global)
The following steps describe how to display an image on a DLP6500 DMD:
Send the Buffer Data from the PC to the Apps FPGA
Step Description Register Address Data
1 Set Apps FPGA user load mode (all zeros) 0x0040 enable bit = '0'
2 Set buffer starting write to zero and number of rows to 1080 (0x438) 0x0024 0x438
3Send the 1080p image to the user image buffer.
Requires 507 write bursts (FIFO Write Transaction)
Burst 1 256, 16-bit words
Burst 2 256, 16-bit words
⁞
Burst n256, 16-bit words
⁞
Burst 507 256, 16-bit words
Send Data from the Apps FPGA Data Buffer to the DLPC910 - DMD
Set image data modifiers if needed (ns_flip, comp_data). Use dip switch (SW2) on DLPLCRC910EVM board or
use register 0x0010.
Step Description Register Address Data
1 Send first row of data to DLPC910 - DMD 0x002C 0x00000003
2 Send the remaining 1079 rows 0x002C 0x04370001
3 Issue a global mirror reset to DLPC910 - DMD 0x0030 0x00000183
1. Send first row of image data to DLPC910 - DMD by writing 0x00000003 to row command register 0x002C.
2. Send all remaining rows by writing 0x04370001 to register 0x002C.
3. Issue a global mirror reset to DLPC910 - DMD by writing to register 0x0030.
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4.3.2 DLP9000X (2560 x 1600) User Image Display Example (Global)
The following steps describe how to display an image on a DLP9000X or DLP9000XUV DMD:
Send the Buffer Data from the PC to the Apps FPGA
Step Description Register Address Data
1 Set Apps FPGA user load mode (all zeros) 0x0040 enable bit = '0'
2 Set buffer starting write to zeros and number of rows to 1600 (0x640) 0x0024 0x640
3Send the WQXGA image to the user image buffer.
This requires 1000 write bursts (FIFO Write Transaction)
Burst 1 256, 16-bit words
Burst 2 256, 16-bit words
⁞
Burst n256, 16-bit words
⁞
Burst 1000 256, 16-bit words
Send Data from the Apps FPGA Data Buffer to the DLPC910 - DMD
Set image data modifiers if needed (ns_flip, comp_data). Use dip switch (SW2) on DLPLCRC910EVM board or
use register 0x0010.
Step Description Register Address Data
1 Send first row of data to DLPC910 - DMD 0x002C 0x00000003
2 Send the remaining 1599 rows 0x002C 0x063F0001
3 Issue a global mirror reset to DLPC910 - DMD 0x0030 0x00000183
4.3.3 Load4 - Using with DLP6500 DMD
Note
When using the DLP6500 DMD in load4 mode, the DMD row pointer does not accept pre-loads
(rowmd = “10”). The row pointer can only be cleared (rowmd = “11”) and incremented (rowmd = “01”).
Furthermore, there are 15 row pointer counts that do not result in data being written to DMD memory.
So, to write to row 0 of the DMD, the row pointer must be cleared first (rowmd = “11”), followed by 14
dummy writes (rowmd = “01”).
4.3.4 USB GPIF FIFO Data Writes
An image is transferred to the user image buffer, by writing to the USB GPIF FIFO.
Images must be transferred from top left to bottom right. The first 16-bit word received, after the USB IF FIFO
is reset (reg 0x0024), are placed in columns 0 through 15 of the DMD. The LSB of the first 16-bit word received
goes to DMD column 0, MSB to column 15.
For a DLP6500 DMD, the transfer process continues until 120, 16-bit FIFO words are sent, which comprises a
1920 column row on the DMD. Then the next 120 words sent are placed on the next DMD row.
For DLP9000X or DLP9000XUV DMDs, the transfer process continues until 160, 16-bit words per DMD row
which comprises a 2560 column row on the DMD. Then the next 160 words sent are placed on the next DMD
row.
4.3.5 External Trigger
In lieu of issuing a global reset using a register write, an external trigger port is available on the
DLPLCRC910EVM (Enable External Global Reset Trigger). When the trigger input is pulsed with an active
high signal, a global reset block command is issued to the DLP component set.
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