Texas Instruments MSP430x11x1 User manual

MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
1
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
D Low Supply Voltage Range 1.8 V – 3.6 V
D Ultralow-Power Consumption
Low Operation Current,
1.3 µA at 4 kHz, 2.2 V
160 µA at 1 MHz, 2.2 V
D Five Power Saving Modes:
(Standby Mode: 0.8 µA,
RAM Retention Off Mode: 0.1 µA)
D Wake-Up From Standby Mode in 6 µs
D 16-Bit RISC Architecture, 125 ns
Instruction Cycle Time
D Basic Clock Module Configurations:
– Various Internal Resistors
– Single External Resistor
– 32 kHz Crystal
– High Frequency Crystal
– Resonator
– External Clock Source
D 16-Bit Timer With Three Capture/Compare
Registers
D Slope A/D Converter With External
Components
D On-Chip Comparator for Analog Signal
Compare Function or Slope A/D
Conversion
D Serial Onboard Programming
D Programmable Code Protection by Security
Fuse (C11x1 Only)
D Family Members Include:
MSP430C1111: 2KB ROM,128B RAM
MSP430C1121: 4KB ROM, 256B RAM
MSP430F1101: 1KB + 128B Flash Memory
(MTP { ), 128B RAM
MSP430F1121: 4KB + 256B Flash Memory
(MTP { ), 256B RAM
D Available in a 20-Pin Plastic Small-Outline
Wide Body (SOWB) Package and 20-Pin
Plastic Thin Shrink Small-Outline Package
(TSSOP)
description
TheTexasInstrumentsMSP430seriesisanultralow-powermicrocontrollerfamilyconsistingofseveraldevices
featuringdifferentsetsofmodulestargetedtovariousapplications.Themicrocontrollerisdesignedtobebattery
operated for an extended-application lifetime. With 16-bit RISC architecture, 16 bit integrated registers on the
CPU, and a constant generator, the MSP430 achieves maximum code efficiency. The digitally-controlled
oscillator provides fast wake-up from all low-power modes to active mode in less than 6 m s.
Typicalapplicationsincludesensorsystemsthatcaptureanalogsignals,convertthemtodigitalvalues,andthen
processthedataanddisplaythemortransmitthemtoahostsystem.StandaloneRFsensorfrontendisanother
areaof application.The I/Oport inputsprovide singleslope A/Dconversion capabilityon resistivesensors. The
MSP430x11x series is an ultralow-power mixed signal microcontroller with a built in 16-bit timer and fourteen
I/O pins. The MSP430x11x1 family adds a versatile analog comparator.
The flash memory provides added flexibility of in-system programming and data storage without significantly
increasing the current consumption of the device. The programming voltage is generated on-chip, thereby
alleviatingtheneedforanadditionalsupply,andevenallowingforreprogrammingofbattery-operatedsystems.
{ MTP = Multiple Time Programmable
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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20
19
18
17
16
15
14
13
12
11
TEST
VCC
P2.5/Rosc
VSS
XOUT
XIN
RST/NMI
P2.0/ACLK
P2.1/INCLK
P2.2/CAOUT/TA0
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/CA1/TA2
P2.3/CA0/TA1
DW OR PW PACKAGE
(TOP VIEW)

MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
2POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICES
TAPLASTIC
20-PIN SOWB
(DW)
PLASTIC
20-PIN TSSOP
(PW)
40
°
Cto85
°
C
MSP430C1111IDW
MSP430C1121IDW MSP430F1101IPW MSP430F1121IPW
–
40°C
to
85°C
MSP430F1101IDW
MSP430F1121IDW
functional block diagram
Oscillator
System Clock
ACLK
SMCLK
1/2/4 KB ROM/
’C’: ROM
128/256B
RAM Power-on- Reset
I/O Port P1
8 I/O’s, All With
Interrupt
CPU
Incl. 16 Reg. Test JTAG
Bus
Conv.
MAB, 16 Bit
MDB, 16 Bit
MAB, 4 Bit
MDB, 8 Bit
MCB
XIN XOUT VCC VSS RST/NMI P1.0–7
DCOR
ACLK
P2.0 / ACLK
Rosc
TEST
’F’: Flash
Outx
Timer_A
3 CC
CCR0/1/2
Watchdog
Timer
15/16 Bit
MCLK
x = 0, 1, 2
ACLK
SMCLK
Outx
CCIx
CCIx
TACLK or
INCLK INCLK
Out0
CCI0
JTAG
CCIxA
TACLK
SMCLK
I/O Port P2
6 I/O’s All With
8
Capabililty
Interrupt
Capabililty
Register CCI1 Comparator-A
Input Multiplexer
RC Filtered O/P
Internal Vref
Analog Switch
P2.1 / INCLK
P2.2 / CAOUT/TA0
P2.5 / Rosc
P2.4 / CA1/TA2
P2.3 / CA0/TA1
CCI1
Flash+126/256B
Flash INFO
†
†A pulldown resistor of 30 kΩis needed on F11x1.

MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
3
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
P1.0/TACLK 13 I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input
P1.1/TA0 14 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output
P1.2/TA1 15 I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2 16 I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK/TCK 17 I/O General-purpose digital I/O pin/SMCLK signal output/test clock, input terminal for device programming
and test
P1.5/TA0/TMS 18 I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/test mode select, input terminal for
device programming and test
P1.6/TA1/TDI 19 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/test data input terminal
P1.7/TA2/TDO/TDI†20 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/test data output terminal or data input
during programming
P2.0/ACLK 8 I/O General-purpose digital I/O pin/ACLK output
P2.1/INCLK 9 I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0 10 I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/comparator_A, output
P2.3/CA0/TA1 11 I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/comparator_A, input
P2.4/CA1/TA2 12 I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/comparator_A, input
P2.5/Rosc 3 I/O General-purpose digital I/O pin/Input for external resistor that defines the DCO nominal frequency
RST/NMI 7 I Reset or nonmaskable interrupt input
TEST 1 I Select of test mode for JTAG pins on Port1. Must be tied low with less than 30 kΩ(F11x1).
VCC 2Supply voltage
VSS 4Ground reference
XIN 6 I Input terminal of crystal oscillator
XOUT 5 I/O Output terminal of crystal oscillator
†TDO or TDI is selected via JTAG instruction.
short-form description
processing unit
The processing unit is based on a consistent, and orthogonally-designed CPU and instruction set. This design
structure results in a RISC-like architecture, highly transparent to the application development, and noted for
its programming simplicity. All operations other than program-flow instructions are consequently performed as
register operations in conjunction with seven addressing modes for source, and four modes for destination
operands.

MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
4POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
short-form description (continued)
CPU
All sixteen registers are located inside the CPU,
providingreducedinstructionexecutiontime.This
reduces a register-register operation execution
time to one cycle of the processor.
Four registers are reserved for special use as a
programcounter,astackpointer,astatusregister,
and a constant generator. The remaining twelve
registers are available as general-purpose
registers.
Peripherals are connected to the CPU using a
data address and control buses and can be
handled easily with all instructions for memory
manipulation.
instruction set
The instructions set for this register-register architecture provides a powerful and easy-to-use assembly
language. The instruction set consists of 51 instructions with three formats and seven addressing modes.
Table 1providesasummationand exampleof thethreetypes ofinstruction formats;theaddressing modesare
listed in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination e.g. ADD R4, R5 R4 + R5 →R5
Single operands, destination only e.g. CALL R8 PC →(TOS), R8 →PC
Relative jump, un-/conditional e.g. JNE Jump-on equal bit = 0
Most instructions can operate on both word and byte data. Byte operations are identified by the suffix B.
Examples: Instructions for word operation Instructions for byte operation
MOV EDE,TONI MOV.B EDE,TONI
ADD #235h,&MEM ADD.B #35h,&MEM
PUSH R5 PUSH.B R5
SWPB R5 —
Table 2. Address Mode Descriptions
ADDRESS MODE s d SYNTAX EXAMPLE OPERATION
Register √ √ MOV Rs, Rd MOV R10, R11 R10 →R11
Indexed √ √ MOV X(Rn), Y(Rm) MOV 2(R5), 6(R6) M(2 + R5) →M(6 + R6)
Symbolic (PC relative) √ √ MOV EDE, TONI M(EDE) →M(TONI)
Absolute √ √ MOV &MEM, &TCDAT M(MEM) →M(TCDAT)
Indirect √MOV @Rn, Y(Rm) MOV @R10, Tab(R6) M(R10) →M(Tab + R6)
Indirect autoincrement √MOV @Rn+, RM MOV @R10+, R11 M(R10) →R11, R10 + 2 →R10
Immediate √MOV #X, TONI MOV #45, TONI #45 →M(TONI)
NOTE: s = source d = destination Rs/Rd = source register/destination register Rn = register number
Program Counter
General-Purpose Register
PC/R0
Stack Pointer SP/R1
Status Register SR/CG1/R2
Constant Generator CG2/R3
R4
General-Purpose Register R5
General-Purpose Register R14
General-Purpose Register R15

MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
5
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
instruction set (continued)
Computedbranches(BR)andsubroutinecalls(CALL)instructionsusethesameaddressingmodesastheother
instructions. These addressing modes provide
indirect addressing, ideally suited for computed branches and
calls.The fulluseofthisprogrammingcapabilitypermits aprogram structuredifferentfrom conventional8-and
16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks
instead of using flag type programs for flow control.
operation modes and interrupts
TheMSP430operating modessupportvarious advancedrequirements for ultralow-powerand ultralow energy
consumption. This is achieved by the intelligent management of the operations during the different module
operation modes and CPU states. The advanced requirements are fully supported during interrupt event
handling. An interrupt event awakens the system from each of the various operating modes and returns with
the
RETI instruction to the mode that was selected before the interrupt event. The different requirements of the
CPU and modules, which are driven by system cost and current consumption objectives, necessitate the use
of different clock signals:
D Auxiliary clock ACLK (from LFXT1CLK/crystal’s frequency), used by the peripheral modules
D Main system clock MCLK, used by the CPU and system
D Subsystem clock SMCLK, used by the peripheral modules
low-power consumption capabilities
The various operating modes are controlled by the software through controlling the operation of the internal
clock system. This clock system provides many combinations of hardware and software capabilities to run the
application with the lowest power consumption and with optimized system costs:
D Use the internal clock (DCO) generator without any external components.
D Select an external crystal or ceramic resonator for lowest frequency or cost.
D Select and activate the proper clock signals (LFXT1CLK and/or DCOCLK) and clock pre-divider function.
D Apply an external clock source.
Four of the control bits that influence the operation of the clock system and support fast turnon from low power
operating modes are located in the status register SR. The four bits that control the CPU and the system clock
generator are SCG1, SCG0, OscOff, and CPUOff:

MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
6POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
status register R2
Reserved For Future
Enhancements
15 9 8 7 0
V SCG1 SCG0 OscOff CPUOff GIE N Z C
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
6543 21
The bits CPUOff, SCG1, SCG0, and OscOff are the most important low-power control bits when the basic
function of the system clock generator is established. They are pushed onto the stack whenever an interrupt
is accepted and thereby saved so that the previous mode of operation can be retrieved after the interrupt
request. During execution of an interrupt handler routine, the bits can be manipulated via indirect access of the
data on the stack. That allows the program to resume execution in another power operating mode after the
return from interrupt (RETI).
SCG1: The clock signal SMCLK, used for peripherals, is enabled when bit SCG1 is reset or disabled if
the bit is set.
SCG0: The dc-generator is active when SCG0 is reset. The dc-generator can be deactivated only if the
SCG0 bit is set and the DCOCLK signal is not used for MCLK or SMCLK. The current consumed
by the dc-generator defines the basic frequency of the DCOCLK. It is a dc current.
The clock signal DCOCLK is deactivated if it is not used for MCLK or SMCLK or if the SCG0 bit
is set. There are two situations when the SCG0 bit cannot switch off the DCOCLK signal:
1. DCOCLK frequency is used for MCLK (CPUOff=0 and SELM.1=0).
2. DCOCLK frequency is used for SMCLK (SCG1=0 and SELS=0).
NOTE:
When the current is switched off (SCG0=1) the start of the DCOCLK is delayed slightly. The delay
is in the µs-range (see device parameters for details).
OscOff: The LFXT1 crystal oscillator is active when the OscOff bit is reset. The LFXT1 oscillator can only
be deactivated if the OscOff bit is set and it is not used for MCLK or SMCLK. The setup time to
start a crystal oscillation needs consideration when oscillator off option is used. Mask
programmable(ROM)devicescandisablethisfeaturesothattheoscillatorcanneverbeswitched
off by software.
CPUOff: The clock signal MCLK, used for the CPU, is active when the CPUOff bit is reset or stopped if it
is set.

MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
7
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the memory with an address range of
0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction
sequence.
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power-up, external reset, watchdog WDTIFG (Note1)
KEYV (Note 1) Reset 0FFFEh 15, highest
NMI, oscillator fault, flash memory
access violation
NMIIFG (Notes 1 and 4)
OFIFG (Notes 1 and 4)
ACCVIFG (Notes 1 and 4)
(non)-maskable,
(non)-maskable,
(non)-maskable 0FFFCh 14
0FFFAh 13
0FFF8h 12
Comparator_A CAIFG maskable 0FFF6h 11
Watchdog timer WDTIFG maskable 0FFF4h 10
Timer_A CCIFG0 (Note 2) maskable 0FFF2h 9
Timer_A CCIFG1, CCIFG2, TAIFG
(Notes 1 and 2) maskable 0FFF0h 8
0FFEEh 7
0FFECh 6
0FFEAh 5
0FFE8h 4
I/O Port P2 (eight flags – see Note 3) P2IFG.0 to P2IFG.7
(Notes 1 and 2) maskable 0FFE6h 3
I/O Port P1 (eight flags) P1IFG.0 to P1IFG.7
(Notes 1 and 2) maskable 0FFE4h 2
0FFE2h 1
0FFE0h 0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module
3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0–5) are implemented on the 11x1 devices.
4. (non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt enable bit will disable an interrupt event.

MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
8POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
special function registers
Mostinterruptandmoduleenablebitsarecollectedintothelowestaddressspace.Specialfunction registerbits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
7654 0
OFIE WDTIE
321
rw-0 rw-0 rw-0
Address
0h NMIIEACCVIE
rw-0
WDTIE: Watchdog timer enable signal
OFIE: Oscillator fault enable signal
NMIIE: Nonmaskable interrupt enable signal
ACCVIE: Access violation at flash memory
7654 0321
Address
01h
interrupt flag register 1 and 2
7654 0
OFIFG WDTIFG
321
rw-0 rw-1 rw-0
Address
02h NMIIFG
WDTIFG: Set on overflow or security key violation or
Reset on VCC power-on or reset condition at RST/NMI-pin
OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST/NMI-pin
7654 0321
Address
03h
Legend rw:
rw-0: Bit can be read and written. Bit can be read and written. It is reset by PUC
SFR bit is not present in device.

MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
9
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
memory organization
Int. Vector
2 KB ROM
128B RAM
16b Per.
8b Per.
SFR
FFFFh
FFE0h
FFDFh
F800h
027Fh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
MSP430C1111
Int. Vector
4 KB
Flash
Segment0–7
256B RAM
16b Per.
8b Per.
SFR
FFFFh
FFE0h
FFDFh
02FFh
0200h
01FFh 0100h
00FFh
0010h
000Fh
0000h
MSP430F1121
Int. Vector
4 KB
ROM
256B RAM
16b Per.
8b Per.
SFR
FFFFh
FFE0h
FFDFh
F000h
02FFh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
MSP430C1121
F000h
Main
Memory
10FFh 2 ×128B
Flash
SegmentA,B
Information
Memory
1000h
1 KB
Boot ROM
0FFFh
0C00h
Int. Vector
1 KB Flash
Segment0,1
128B RAM
16b Per.
8b Per.
SFR
FFDFh
FC00h
027Fh
0200h
0100h
00FFh
0010h
000Fh
0000h
MSP430F1101
1 KB
Boot ROM
128B Flash
SegmentA
10FFh
1080h
01FFh
0C00h
0FFFh
FFFFh
FFE0h
boot ROM containing bootstrap loader
Theintentionofthebootstraploaderistodownloaddataintotheflashmemorymodule.Variouswrite,read,and
erase operations are needed for a proper download environment. The bootstrap loader is only available on F
devices.
functions of the bootstrap loader:
Definition of read: apply and transmit data of peripheral registers or memory to pin P1.1 (BSLTX)
write: read data from pin P2.2 (BSLRX) and write them into flash memory
unprotected functions
Mass erase, erase of the main memory (Segment0 to Segment7)
Access to the MSP430 via the bootstrap loader is protected. It must be enabled before any protected function
can be performed. The 256 bits in 0FFE0h to 0FFFFh provide the access key.
protected functions
All protected functions can be executed only if the access is enabled.
D Write/program byte into flash memory; Parameters passed are start address and number of bytes (the
segment-write feature of the flash memory is not supported and not useful with the UART protocol).
D Segment erase of Segment0 to Segment7 in the main memory and segment erase of SegmentA and
SegmentB in the information memory.
D Read all data in main memory and information memory.
D Read and write to all byte peripheral modules and RAM.
D Modify PC and start program execution immediately.
NOTE:
Unauthorized readout of code and data is prevented by the user’s definition of the data in the
interrupt memory locations.

MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C – SEPTEMBER 1999 – REVISED JUNE 2000
10 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265
boot ROM containing bootstrap loader (continued)
features of the bootstrap loader are:
D UART communication protocol, fixed to 9600 baud
D Port pin P1.1 for transmit, P2.2 for receive
D TI standard serial protocol definition
D Implemented in flash memory version only
D Program execution starts with the user vector at 0FFFEh or with the bootstrap loader (start vector is at
address 0C00h)
hardware resources used for serial input/output:
D Pins P1.1 and P2.2 for serial data transmission
D Test and RST/NMI to start program execution at the reset or bootstrap loader vector
D Basic clock module: Rsel=5,DCO=4,MOD=0, DCOCLK for MCLKandSMCLK, clock divider forMCLK
and SMCLK at default: dividing by 1
D Timer_A: Timer_A operates in continuous mode with MCLK source selected, input divider set to 1,
using CCR0, and polling of CCIFG0.
D WDT: Watchdog timer is halted
D Interrupt: GIE=0, NMIIE=0, OFIFG=0, ACCVIFG=0
D Memory allocation and stack pointer:
If the stack pointer points to RAM addresses above 0220h, 6 bytes of the stack are allocated
plus RAM addresses 0200h to 0219h. Otherwise the stack pointer is set to 0220h and allocates
RAM from 0200h to 021Fh.
NOTE:
Whenwriting RAMdataviabootstraploader,takecarethat thestack isoutsidetherange
of the data being written.
Program execution begins with the user’s reset vector at FFFEh (standard method) if TEST is held low while
RST/NMI goes from low to high:
RST/NMI PIN
TEST PIN
User Program Starts
VCC
Reset Condition