Texas Instruments TMS320C6201 User manual

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
1
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
DHigh-Performance Fixed-Point Digital
Signal Processor (DSP) TMS320C6201
-- 5-ns Instruction Cycle Time
-- 200-MHz Clock Rate
-- Eight 32-Bit Instructions/Cycle
-- 1600 MIPS
DVelociTI™Advanced Very Long Instruction
Word (VLIW) TMS320C62x™DSP CPU Core
-- Eight Independent Functional Units:
-- SixALUs(32-/40-Bit)
-- Two 16-Bit Multipliers (32-Bit Results)
-- Load-Store Architecture With 32 32-Bit
General-Purpose Registers
-- Instruction Packing Reduces Code Size
-- All Instructions Conditional
DInstruction Set Features
-- Byte-Addressable (8-, 16-, 32-Bit Data)
-- 32-Bit Address Range
-- 8-Bit Overflow Protection
-- Saturation
-- Bit-Field Extract, Set, Clear
-- Bit-Counting
-- Normalization
D1M-Bit On-Chip SRAM
-- 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
-- 512K-Bit Dual-Access Internal Data
(64K Bytes) Organized as Two Blocks for
Improved Concurrency
D32-Bit External Memory Interface (EMIF)
-- Glueless Interface to Asynchronous
Memories: SRAM and EPROM
-- Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
DFour-Channel Bootloading
Direct-Memory-Access (DMA) Controller
with an Auxiliary Channel
D16-Bit Host-Port Interface (HPI)
-- Access to Entire Memory Map
DTwo Multichannel Buffered Serial Ports
(McBSPs)
-- Direct Interface to T1/E1, MVIP, SCSA
Framers
-- ST-Bus-Switching Compatible
-- Up to 256 Channels Each
-- AC97-Compatible
-- Serial Peripheral Interface (SPI)
Compatible (Motorola™)
DTwo 32-Bit General-Purpose Timers
DFlexible Phase-Locked Loop (PLL) Clock
Generator
DIEEE-1149.1 (JTAG†) Boundary-Scan
Compatible
D352-Pin BGA Package (GJC Suffix)
D352-Pin BGA Package (GJL Suffix)
DCMOS Technology
-- 0.18-μm/5-Level Metal Process
D3.3-V I/Os, 1.8-V Internal
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI and TMS320C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright ©2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
GJC/GJL
352-PIN BALL GRID ARRAY (BGA) PACKAGES
(BOTTOM VIEW)
AF
AD
AB
AA
AC
W
Y
U
V
AE
R
N
P
L
H
J
K
M
F
G
D
E
B
A
C
T
25
2622
23
20
19 211715
1612
13
14 1810
9
8
75
64
3
2
111
24

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
2POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
Table of Contents
parameter measurement information 30...............
input and output clocks 31...........................
asynchronous memory timing 33.....................
synchronous-burst memory timing 35.................
synchronous DRAM timing 39.......................
HOLD/HOLDA timing 43............................
reset timing 44.....................................
external interrupt timing 46..........................
host-port interface timing 47.........................
multichannel buffered serial port timing 50.............
DMAC, timer, power-down timing 61..................
JTAG test-port timing 62............................
revision history 63..................................
thermal/mechanical data 64.........................
GJC/GJL BGA packages (bottom view) 1.................
description 2.........................................
device characteristics 3................................
functional and CPU (DSP core) block diagram 4...........
CPU (DSP core) description 5..........................
signal groups description 7.............................
signal descriptions 9...................................
development support 20...............................
documentation support 23..............................
clock PLL 24.........................................
power-down mode logic 25.............................
power-supply sequencing 27...........................
absolute maximum ratings over operating case
temperature ranges 28............................
recommended operating conditions 28...................
electrical characteristics over recommended ranges of
supply voltage and operating case temperature 29....
description
The TMS320C62x™DSPs (including the TMS320C6201†) are the fixed-point DSP family in the
TMS320C6000™DSP platform. The C6201 device is based on the high-performance, advanced VelociTI™
very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an
excellent choice for multichannel and multifunction applications. With performance of up to 1600 MIPS at a
clock rate of 200 MHz, the C6201 offers cost-effective solutions to high-performance DSP programming
challenges. The C6201 DSP possesses the operational flexibility of high-speed controllers and the numerical
capability of array processors. The processor has 32 general-purpose registers of 32-bit word length and eight
highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high
degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6201 can produce two
multiply-accumulates (MACs) per cycle—for a total of 466 million MACs per second (MMACS). The C62x™
DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
The C6201 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program
memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space.
Data memory of the C6201 consists of two 32K-byte blocks of RAM for improved concurrency. The peripheral
set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface
(HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and
asynchronous peripherals.
The C62x™DSP has a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows™debugger interface for visibility into source
code execution.
TMS320C6000 and C62x are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
†The TMS320C6201 device shall be referred to as C6201 throughout the remainder of this document.

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
3
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
device characteristics
Table 1 provides an overview of the C6201 DSP. The table shows significant features of each device, including
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.
Table 1. Characteristics of the C6201 Processor
HARDWARE FEATURES C6201 (FIXED-POINT DSP)
EMIF 1
DMA 1
Peripherals HPI 1
P
e
r
i
p
h
e
r
a
l
s
McBSPs 2
32-Bit Timers 2
Size (Bytes) 72K
On-Chip Memory Organization 512-Kbit Program Memory
512-Kbit Data Memory (organized as two blocks)
CPU ID+Rev ID Control Status Register (CSR.[31:16]) 0x0002
Frequency MHz 200
Cycle Time ns 5 ns (C6201-200)
V
o
l
t
a
g
e
Core (V) 1.8
Voltage I/O (V) 3.3
PLL Options CLKIN frequency multiplier Bypass (x1), x4
B
G
A
P
a
c
k
a
g
e
s
27 x 27 mm 352-Pin BGA (GJL)
BG
A
Packages 35 x 35 mm 352-Pin BGA (GJC)
Process Technology μm0.18 μm
Product Status
Product Preview (PP)
Advance Information (AI)
Production Data (PD)
PD
Device Part Numbers (For more details on the C6000™DSP part
numbering, see Figure 4)
TMS320C6201GJC200
TMS320C6201GJCA200
TMS320C6201GJL200
TMS320C6201GJLA200
C6000 is a trademark of Texas Instruments.

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
4POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
functional and CPU (DSP core) block diagram
Multichannel
Buffered Serial
Port 1
32
Direct Memory
Access Controller
(DMA)
(4 Channels)
Test
C62x CPU (DSP Core)
Data Path B
B Register File
Program
Access/Cache
Controller
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path A
A Register File
PLL
(x1, x4)
Data
Access
Controller
Power-
Down
Logic
.L1 .S1 .M1 .D1 .D2 .M2 .S2 .L2
ROM/FLASH
SRAM
I/O Devices
32
Synchronous
FIFOs
I/O Devices
Timer 0
Timer 1
External Memory
Interface (EMIF)
Multichannel
Buffered Serial
Port 0
Host Port
Interface
(HPI)
Internal Program Memory
(64K Bytes)
Control
Registers
Control
Logic
Internal Data
Memory
(64K Bytes)
In-Circuit
Emulation
Interrupt
Control
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
HOST CONNECTION
Master /Slave
TI PCI2040
Power PC
683xx
960
C6201 Digital Signal Processors
Peripheral Control Bus
DMA Bus
Boot Configuration
Interrupt
Selector
SBSRAM
SDRAM

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
5
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
CPU (DSP core) description
The CPU fetches VelociTI™advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight
32-bit instructions to the eight functional units during every clock cycle. The VelociTI™VLIW architecture
features controls by which all eight units do not have to be supplied with instructions if they are not ready to
execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute
packet as the previous instruction, or whether it should be executed in the following clock as a part of the next
execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The
variable-length execute packets are a key memory-saving feature, distinguishing the C62x CPU from other
VLIW architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along
with two register files, compose sides A and B of the CPU [see functional and CPU (DSP core) block diagram
and Figure 1]. The four functional units on each side of the CPU can freely share the 16 registers belonging to
that side. Additionally, each side features a single data bus connected to all the registers on the other side, by
which the two sets of functional units can access data from the register files on the opposite side. While register
access by functional units on the same side of the CPU as the register file can service all the units in a single
clock cycle, register access using the register file across the CPU supports one read and one write per cycle.
Another key feature of the C62x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes
with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch
packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the
current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can
vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per
clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
6POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
CPU (DSP core) description (continued)
2X
1X
.L2
.S2
.M2
.D2
.D1
.M1
.S1
.L1
long src
dst
src2
src1
src1
src1
src1
src1
src1
src1
src1
8
8
8
8
8
8
long dst
long dst
dst
dst
dst
dst
dst
dst
dst
src2
src2
src2
src2
src2
src2
src2
long src
DA1
DA2
ST1
LD1
LD2
ST2
32
32
Register
File A
(A0--A15)
long src
long dst
long dst
long src
Data Path B
Data Path A
Register
File B
(B0--B15)
Control
Register
File
Figure 1. TMS320C62x CPU (DSP Core) Data Paths

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
7
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
signal groups description
HHWIL
HBE0
HBE1
HCNTL0
HCNTL1
TRST
EXT_INT7
Clock/PLL
JTAG
Emulation
Reserved
Data
Register Select
Half-Word/Byte
Select
Boot Mode
Reset and
Interrupts
Little ENDIAN
Big ENDIAN
DMA Status
Power-Down
Status
Control
HPI
(Host-Port Interface)
16
Control/Status
TDI
TDO
TMS
TCK
CLKIN
CLKOUT2
CLKOUT1
CLKMODE1
CLKMODE0
PLLFREQ3
PLLFREQ2
PLLFREQ1
PLLV
PLLG
PLLF
EMU1
EMU0
RSV3
RSV2
RSV1
RSV0
HD[15:0]
BOOTMODE4
BOOTMODE3
BOOTMODE2
BOOTMODE1
BOOTMODE0
NMI
IACK
INUM3
INUM2
INUM1
INUM0
LENDIAN
DMAC3
DMAC2
DMAC1
DMAC0
PD
HAS
HR/W
HCS
HDS1
HDS2
HRDY
HINT
RSV7
RSV6
RSV5
RSV4
RSV8
EXT_INT6
EXT_INT5
EXT_INT4
RESET
RSV9
Figure 2. CPU (DSP Core) and Peripheral Signals

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
8POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
signal groups description (continued)
CE3
ARE
ED[31:0]
CE2
CE1
CE0
EA[21:2]
BE3
BE2
BE1
BE0
HOLD
HOLDA
TOUT1
CLKX1
FSX1
DX1
CLKR1
FSR1
DR1
CLKS1
AOE
AWE
ARDY
SSADS
SSOE
SSWE
SSCLK
SDA10
SDRAS
SDCAS
SDWE
SDCLK
TOUT0
CLKX0
FSX0
DX0
CLKR0
FSR0
DR0
CLKS0
Data
Memory Map
Space Select
Word Address
Byte Enables
HOLD/
HOLDA
32
20
Asynchronous
Memory
Control
SBSRAM
Control
SDRAM
Control
EMIF
(External Memory Interface)
Timer 1
Receive Receive
Timer 0
Timers
McBSP1 McBSP0
Transmit Transmit
Clock Clock
McBSPs
(Multichannel Buffered Serial Ports)
TINP1 TINP0
Figure 3. Peripheral Signals

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
9
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
Signal Descriptions
SIGN
A
LPIN NO.
T
Y
P
E
†
D
E
S
C
R
I
P
T
I
O
N
S
I
G
N
A
L
NAME GJC GJL T
Y
PE†DESCRIPTION
CLOCK/PLL
CLKIN C10 B9 IClock Input
CLKOUT1 AF22 AC18 OClock output at full device speed
CLKOUT2 AF20 AC16 OClock output at half of device speed
CLKMODE1 C6 D8
I
Clock mode selects
-
S
e
l
e
c
t
s
w
h
e
t
h
e
r
t
h
e
C
P
U
c
l
o
c
k
f
r
e
q
u
e
n
c
y
=
i
n
p
u
t
c
l
o
c
k
f
r
e
q
u
e
n
c
y
x
4
o
r
x
1
CLKMODE0 C5 C7
I
-
S
e
l
e
c
t
s
w
h
e
t
h
e
r
t
h
e
C
P
U
c
l
o
c
k
f
r
e
q
u
e
n
c
y
=
i
n
p
u
t
c
l
o
c
k
f
r
e
q
u
e
n
c
y
x
4
o
r
x
1
For more details on the GJC and GJL CLKMODE pins and the PLL multiply factors,
see the Clock PLL section of this data sheet.
PLLFREQ3 A9 A9 PLL
f
re
q
uenc
y
ran
g
e
(
3, 2, and 1
)
PLLFREQ2 D11 D11 I
P
L
L
f
r
e
q
u
e
n
c
y
r
a
n
g
e
(
3
,
2
,
a
n
d
1
)
-
Th
e
t
a
r
g
e
tr
a
n
g
e
f
o
r
C
LK
O
U
T1
f
r
e
q
u
e
n
c
y
i
s
d
e
t
e
rmin
e
d
b
y
th
e
3
-
b
it v
a
l
u
e
o
f
th
e
PLLFREQ1 B10 B10
I
-
T
h
e
t
a
r
g
e
t
r
a
n
g
e
f
o
r
C
L
K
O
U
T
1
f
r
e
q
u
e
n
c
y
i
s
d
e
t
e
r
m
i
n
e
d
b
y
t
h
e
3
-
b
i
t
v
a
l
u
e
o
f
t
h
e
PLLFREQ pins.
PLLV‡D12 B11 A§PLL analog VCC connection for the low-pass filter
PLLG‡C12 C12 A§PLL analog GND connection for the low-pass filter
PLLF A11 D12 A§PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS L3 L3 IJTAG test port mode select (features an internal pullup)
TDO W2 U4 O/Z JTAG test port data out
TDI R4 T2 IJTAG test port data in (features an internal pullup)
TCK R3 R3 IJTAG test port clock
TRST T1 R4 IJTAG test port reset (features an internal pulldown)
EMU1 Y1 V3 I/O/Z Emulation pin 1, pullup with a dedicated 20-kΩresistor¶
EMU0 W3 W2 I/O/Z Emulation pin 0, pullup with a dedicated 20-kΩresistor¶
RESET AND INTERRUPTS
RESET K2 K2 IDevice reset
NMI L2 L2 INonmaskable interrupt
-Edge-driven (rising edge)
EXT_INT7 U3 U2 External interrupts
EXT_INT6 V2 T4
I
E
x
t
e
r
n
a
l
i
n
t
e
r
r
u
p
t
s
-
Ed
g
e-driven
EXT_INT5 W1 V1 I
-
E
d
g
e
-
d
r
i
v
e
n
-
P
o
l
a
r
i
t
y
i
n
d
e
p
e
n
d
e
n
t
l
y
s
e
l
e
c
t
e
d
v
i
a
t
h
e
e
x
t
e
r
n
a
l
i
n
t
e
r
r
u
p
t
p
o
l
a
r
i
t
y
r
e
g
i
s
t
e
r
b
i
t
s
EXT_INT4 U4 V2
-
P
o
l
a
r
i
t
y
i
n
d
e
p
e
n
d
e
n
t
l
y
s
e
l
e
c
t
e
d
v
i
a
t
h
e
e
x
t
e
r
n
a
l
i
n
t
e
r
r
u
p
t
p
o
l
a
r
i
t
y
r
e
g
i
s
t
e
r
b
i
t
s
(EXTPOL.[3:0])
IACK Y2 Y1 OInterrupt acknowledge for all active interrupts serviced by the CPU
INUM3 AA1 V4
A
t
i
i
t
t
i
d
t
i
f
i
t
i
b
INUM2 W4 Y2
O
Active interrupt identification number
INUM1 AA2 AA1 O-Valid during IACK for all active interrupts (not just external)
-
E
n
c
o
d
i
n
g
o
r
d
e
r
f
o
l
l
o
w
s
t
h
e
i
n
t
e
r
r
u
p
t
s
e
r
v
i
c
e
f
e
t
c
h
p
a
c
k
e
t
o
r
d
e
r
i
n
g
INUM0 AB1 W4 -Encoding order
f
ollows the interrupt-service
f
etch-packet ordering
LITTLE ENDIAN/BIG ENDIAN
LENDIAN H3 G2 IIf high, LENDIAN selects little-endian byte/half-word addressing order within a word
If low, LENDIAN selects big-endian addressing
POWER-DOWN STATUS
PD D3 E2 OPower-down mode 2 or 3 (active if high)
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
‡PLLV and PLLG are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins.
§A = Analog Signal (PLL Filter)
¶For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩresistor. For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-kΩresistor.

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
10 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
Signal Descriptions (Continued)
SIGN
A
LPIN NO.
T
Y
P
E
†
D
E
S
C
R
I
P
T
I
O
N
S
I
G
N
A
L
NAME GJC GJL T
Y
PE†DESCRIPTION
HOST-PORT INTERFACE (HPI)
HINT H26 J26 O Host interrupt (from DSP to host)
HCNTL1 F23 G24 IHost control -- selects between control, address, or data registers
HCNTL0 D25 F25 IHost control -- selects between control, address, or data registers
HHWIL C26 E26 IHost half-word select -- first or second half-word (not necessarily high or low order)
HBE1 E23 F24 IHost byte select within word or half-word
HBE0 D24 E25 IHost byte select within word or half-word
HR/WC23 B22 IHost read or write select
HD15 B13 A12
HD14 B14 D13
HD13 C14 C13
HD12 B15 D14
HD11 D15 B15
HD10 B16 C15
HD9 A17 D15
HD8 B17 B16
I
/
O
/
Z
H
o
s
t
p
o
r
t
d
a
t
a
(
s
e
d
f
o
r
t
r
a
n
s
f
e
r
o
f
d
a
t
a
a
d
d
r
e
s
s
a
n
d
c
o
n
t
r
o
l
)
HD7 D16 C16 I
/
O
/
ZHost-port data (used
f
or trans
f
er o
f
data, address, and control)
HD6 B18 B17
HD5 A19 D16
HD4 C18 A18
HD3 B19 B18
HD2 C19 D17
HD1 B20 C18
HD0 B21 A20
HAS C22 C20 IHost address strobe
HCS B23 B21 IHost chip select
HDS1 D22 C21 IHost data strobe 1
HDS2 A24 D20 IHost data strobe 2
HRDY J24 J25 OHost ready (from DSP to host)
BOOT MODE
BOOTMODE4 D8 C8
BOOTMODE3 B4 B6
BOOTMODE2 A3 D7 IBoot mode
BOOTMODE1 D5 C6
I
B
o
o
t
m
o
d
e
BOOTMODE0 C4 B5
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
11
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
Signal Descriptions (Continued)
SIGN
A
LPIN NO.
T
Y
P
E
†
D
E
S
C
R
I
P
T
I
O
N
S
I
G
N
A
L
NAME GJC GJL T
Y
PE†DESCRIPTION
EMIF -- CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE3 AE22 AD20
CE2 AD26 AA24 O
/
Z
Memory space enables
-
E
n
a
b
l
e
d
b
y
b
i
t
s
2
4
a
n
d
2
5
o
f
t
h
e
w
o
r
d
a
d
d
r
e
s
s
CE1 AB24 AB26
O
/
Z
-
E
n
a
b
l
e
d
b
y
b
i
t
s
2
4
a
n
d
2
5
o
f
t
h
e
w
o
r
d
a
d
d
r
e
s
s
-Only one asserted during any external data access
CE0 AC26 AA25
-
O
n
l
y
o
n
e
a
s
s
e
r
t
e
d
d
u
r
i
n
g
a
n
y
e
x
t
e
r
n
a
l
d
a
t
a
a
c
c
e
s
s
BE3 AB25 Y24 B
y
te-enable control
BE2 AA24 W23
O
/
Z
B
y
t
e
-
e
n
a
b
l
e
c
o
n
t
r
o
l
-
D
e
c
o
d
e
d
f
r
o
m
t
h
e
t
w
o
l
o
w
e
s
t
b
i
t
s
o
f
t
h
e
i
n
t
e
r
n
a
l
a
d
d
r
e
s
s
BE1 Y23 AA26 O
/
Z
-
D
e
c
o
d
e
d
f
r
o
m
t
h
e
t
w
o
l
o
w
e
s
t
b
i
t
s
o
f
t
h
e
i
n
t
e
r
n
a
l
a
d
d
r
e
s
s
-Byte-write enables for most types of memory
BE0 AA26 W25
-
B
y
t
e
w
r
i
t
e
e
n
a
b
l
e
s
f
o
r
m
o
s
t
t
y
p
e
s
o
f
m
e
m
o
r
y
-Can be directly connected to SDRAM read and write mask signal (SDQM)
EMIF -- ADDRESS
EA21 J26 K25
EA20 K25 L24
EA19 L24 L25
EA18 K26 M23
EA17 M26 M25
EA16 M25 M24
EA15 P25 N23
EA14 P24 P24
EA13 R25 P23
EA12 T26 R25
O
/
Z
E
x
t
e
r
n
a
l
a
d
d
r
e
s
s
(
w
o
r
d
a
d
d
r
e
s
s
)
EA11 R23 R24 O
/
Z E
x
ternal address (word address)
EA10 U26 R23
EA9 U25 T25
EA8 T23 T24
EA7 V26 U25
EA6 V25 T23
EA5 W26 V26
EA4 V24 V25
EA3 W25 U23
EA2 Y26 V24
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
12 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
Signal Descriptions (Continued)
SIGN
A
LPIN NO.
T
Y
P
E
†
D
E
S
C
R
I
P
T
I
O
N
S
I
G
N
A
L
NAME GJC GJL T
Y
PE†DESCRIPTION
EMIF -- DATA
ED31 AB2 Y3
ED30 AC1 AA2
ED29 AA4 AB1
ED28 AD1 AA3
ED27 AC3 AB2
ED26 AD4 AE5
ED25 AF3 AD6
ED24 AE4 AC7
ED23 AD5 AE6
ED22 AF4 AD7
ED21 AE5 AC8
ED20 AD6 AD8
ED19 AE6 AC9
ED18 AD7 AF7
ED17 AC8 AD9
ED16 AF7 AC10
I
/
O
/
Z
E
x
t
e
r
n
a
l
d
a
t
a
ED15 AD9 AE9 I
/
O
/
Z E
x
ternal data
ED14 AD10 AF9
ED13 AF9 AC11
ED12 AC11 AE10
ED11 AE10 AD11
ED10 AE11 AE11
ED9 AF11 AC12
ED8 AE14 AD12
ED7 AF15 AE12
ED6 AE15 AC13
ED5 AF16 AD14
ED4 AC15 AC14
ED3 AE17 AE15
ED2 AF18 AD15
ED1 AF19 AE16
ED0 AC17 AD16
EMIF -- ASYNCHRONOUS MEMORY CONTROL
ARE Y24 V23 O/Z Asynchronous memory read enable
AOE AC24 AB25 O/Z Asynchronous memory output enable
AWE AD23 AE22 O/Z Asynchronous memory write enable
ARDY W23 Y26 IAsynchronous memory ready input
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
13
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
Signal Descriptions (Continued)
SIGN
A
LPIN NO.
T
Y
P
E
†
D
E
S
C
R
I
P
T
I
O
N
S
I
G
N
A
L
NAME GJC GJL T
Y
PE†DESCRIPTION
EMIF -- SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL
SSADS AC20 AD19 O/Z SBSRAM address strobe
SSOE AF21 AD18 O/Z SBSRAM output enable
SSWE AD19 AF18 O/Z SBSRAM write enable
SSCLK AD17 AC15 OSBSRAM clock
EMIF -- SYNCHRONOUS DRAM (SDRAM) CONTROL
SDA10 AD21 AC19 O/Z SDRAM address 10 (separate for deactivate command)
SDRAS AF24 AD21 O/Z SDRAM row-address strobe
SDCAS AD22 AC20 O/Z SDRAM column-address strobe
SDWE AF23 AE21 O/Z SDRAM write enable
SDCLK AE20 AC17 OSDRAM clock
EMIF -- BUS ARBITRATION
HOLD AA25 Y25 IHold request from the host
HOLDA A7 C9 OHold-request acknowledge to the host
TIMER1
TOUT1 H24 K23 OTimer 1 or general-purpose output
TINP1 K24 L23 ITimer 1 or general-purpose input
TIMER0
TOUT0 M4 M4 OTimer 0 or general-purpose output
TINP0 K4 H2 ITimer 0 or general-purpose input
DMA ACTION COMPLETE STATUS
DMAC3 D2 E1
DMAC2 F4 F2
O
D
M
A
a
c
t
i
o
n
c
o
m
p
l
e
t
e
DMAC1 D1 G3 ODM
A
action complete
DMAC0 E2 H4
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1 E25 F26 IExternal clock source (as opposed to internal)
CLKR1 H23 H25 I/O/Z Receive clock
CLKX1 F26 J24 I/O/Z Transmit clock
DR1 D26 H23 IReceive data
DX1 G23 G25 O/Z Transmit data
FSR1 E26 J23 I/O/Z Receive frame sync
FSX1 F25 G26 I/O/Z Transmit frame sync
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
14 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
Signal Descriptions (Continued)
SIGN
A
LPIN NO.
T
Y
P
E
†
D
E
S
C
R
I
P
T
I
O
N
S
I
G
N
A
L
NAME GJC GJL T
Y
PE†DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0 L4 L4 IExternal clock source (as opposed to internal)
CLKR0 M2 M2 I/O/Z Receive clock
CLKX0 L1 M3 I/O/Z Transmit clock
DR0 J1 J1 IReceive data
DX0 R1 P4 O/Z Transmit data
FSR0 P4 N3 I/O/Z Receive frame sync
FSX0 P3 N4 I/O/Z Transmit frame sync
RESERVED FOR TEST
RSV0 T2 T3 IReserved for testing, pullup with a dedicated 20-kΩresistor
RSV1 G2 F1 IReserved for testing, pullup with a dedicated 20-kΩresistor
RSV2 C11 C11 IReserved for testing, pullup with a dedicated 20-kΩresistor
RSV3 B9 D10 IReserved for testing, pullup with a dedicated 20-kΩresistor
RSV4 A6 D9 IReserved for testing, pulldown with a dedicated 20-kΩresistor
RSV5 C8 A7 OReserved (leave unconnected, do not connect to power or ground)
RSV6 C21 D18 IReserved for testing, pullup with a dedicated 20-kΩresistor
RSV7 B22 C19 IReserved for testing, pullup with a dedicated 20-kΩresistor
RSV8 A23 D19 IReserved for testing, pullup with a dedicated 20-kΩresistor
RSV9 E4 F3 OReserved (leave unconnected, do not connect to power or ground)
UNCONNECTED PINS
A8 AF20
B8 AE18
C9 AE17
D10 --
D21 --
NC G1 J4 Unconnected pins
N
C
H1 J3
U
n
c
o
n
n
e
c
t
e
d
p
i
n
s
H2 G1
J2 K4
K3 J2
R2 R2
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
15
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
Signal Descriptions (Continued)
SIGN
A
LPIN NO.
T
Y
P
E
†
D
E
S
C
R
I
P
T
I
O
N
S
I
G
N
A
L
NAME GJC GJL T
Y
PE†DESCRIPTION
3.3-V SUPPLY VOLTAGE PINS
A10 A5
A15 A11
A18 A16
A21 A22
A22 B7
B7 B8
C1 B19
D17 B20
F3 C10
G24 C14
G25 C17
H25 G4
J25 G23
L25 H3
M3 H24
N3 K3
N23 K24
R26 L1
T24 L26
D
V
U24 N24
S
3
3
V
s
u
p
p
l
y
v
o
l
t
a
g
e
DVDD W24 P3 S3.3-
V
supply voltage
Y4 T1
AB3 T26
AB4 U3
AB26 U24
AC6 W3
AC10 W24
AC19 Y4
AC21 Y23
AC22 AD10
AC25 AD13
AD11 AD17
AD13 AE7
AD15 AE8
AD18 AE19
AE18 AE20
AE21 AF5
AF5 AF11
AF6 AF16
AF17 AF22
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
16 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
Signal Descriptions (Continued)
SIGN
A
LPIN NO.
T
Y
P
E
†
D
E
S
C
R
I
P
T
I
O
N
S
I
G
N
A
L
NAME GJC GJL T
Y
PE†DESCRIPTION
1.8-V SUPPLY VOLTAGE PINS
A5 A1
A12 A2
A16 A3
A20 A24
B2 A25
B6 A26
B11 B1
B12 B2
B25 B3
C3 B24
C15 B25
C20 B26
C24 C1
D4 C2
D6 C3
D7 C4
D9 C23
D14 C24
C
V
D18 C25
S
1
8
V
s
u
p
p
l
y
v
o
l
t
a
g
e
CVDD D20 C26 S1.8-
V
supply voltage
D23 D3
E1 D4
F1 D5
H4 D22
J4 D23
J23 D24
K1 E4
K23 E23
M1 AB4
M24 AB23
N4 AC3
N25 AC4
P2 AC5
P23 AC22
T3 AC23
T4 AC24
U1 AD1
V4 AD2
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
17
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
Signal Descriptions (Continued)
SIGN
A
LPIN NO.
T
Y
P
E
†
D
E
S
C
R
I
P
T
I
O
N
S
I
G
N
A
L
NAME GJC GJL T
Y
PE†DESCRIPTION
1.8-V SUPPLY VOLTAGE PINS (CONTINUED)
V23 AD3
AC4 AD4
AC9 AD23
AC12 AD24
AC13 AD25
AC18 AD26
AC23 AE1
AD3 AE2
C
V
AD8 AE3
S
1
8
V
s
u
p
p
l
y
v
o
l
t
a
g
e
CVDD AD14 AE24 S1.8-
V
supply voltage
AD24 AE25
AE2 AE26
AE8 AF1
AE12 AF2
AE25 AF3
AF12 AF24
-- AF25
-- AF26
GROUND PINS
A1 A4
A2 A6
A4 A8
A13 A10
A14 A13
A25 A14
A26 A15
B1 A17
B3 A19
VSS B5 A21 GND Ground pins
V
S
S
B24 A23
G
N
D
G
r
o
u
n
d
p
i
n
s
B26 B4
C2 B12
C7 B13
C13 B14
C16 B23
C17 C5
C25 C22
D13 D1
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
18 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
Signal Descriptions (Continued)
SIGN
A
LPIN NO.
T
Y
P
E
†
D
E
S
C
R
I
P
T
I
O
N
S
I
G
N
A
L
NAME GJC GJL T
Y
PE†DESCRIPTION
GROUND PINS (CONTINUED)
D19 D2
E3 D6
E24 D21
F2 D25
F24 D26
G3 E3
G4 E24
G26 F4
J3 F23
L23 H1
L26 H26
M23 K1
N1 K26
N2 M1
N24 M26
N26 N1
P1 N2
P26 N25
V
R24 N26
G
N
D
G
r
o
u
n
d
p
i
n
s
VSS T25 P1 GND Ground pins
U2 P2
U23 P25
V1 P26
V3 R1
Y3 R26
Y25 U1
AA3 U26
AA23 W1
AB23 W26
AC2 AA4
AC5 AA23
AC7 AB3
AC14 AB24
AC16 AC1
AD2 AC2
AD12 AC6
AD16 AC21
AD20 AC25
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
19
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
Signal Descriptions (Continued)
SIGN
A
LPIN NO.
T
Y
P
E
†
D
E
S
C
R
I
P
T
I
O
N
S
I
G
N
A
L
NAME GJC GJL T
Y
PE†DESCRIPTION
GROUND PINS (CONTINUED)
AD25 AC26
AE1 AD5
AE3 AD22
AE7 AE4
AE9 AE13
AE13 AE14
AE16 AE23
AE19 AF4
AE23 AF6
VSS AE24 AF8 GND Ground pins
V
S
S
AE26 AF10
G
N
D
G
r
o
u
n
d
p
i
n
s
AF1 AF12
AF2 AF13
AF8 AF14
AF10 AF15
AF13 AF17
AF14 AF19
AF25 AF21
AF26 AF23
†I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
20 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
development support
TI offers an extensive line of development tools for the TMS320C6000™DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of C6000™DSP-based applications:
Software Development Tools:
Code Composer Studio™Integrated Development Environment (IDE) including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software
needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS™) Emulator (supports C6000™DSP multiprocessor system debug)
EVM (Evaluation Module)
The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about
development-support products for all TMS320™DSP family member devices, including documentation. See
this document for further information on TMS320™DSP documentation or any TMS320™DSP support products
from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide
(SPRU052), contains information about TMS320™DSP-related products from other companies in the industry.
To receive TMS320™DSP literature, contact the Literature Response Center at 800/477-8924.
For a complete listing of development-support tools for the TMS320C6000™DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and under
“Development Tools”, select “Digital Signal Processors”. For information on pricing and availability, contact the
nearest TI field sales office or authorized distributor.
Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments.