Texas Instruments TMS320TCI6482 Guide

Application ReportSPRAAC7B – April 2006
TMS320TCI6482 Design Guide and Migration fromTMS320TCI100Rick Hennessy and Douglas Harrington.................................................. Digital Signal Processing Solutions
ABSTRACT
This document describes system design considerations for the TMS320TCI6482(TCI6482). It also gives comparisons to designing with the TMS320TCI100 (TCI100) forthose familiar with that device. The objective of this document is to cover systemdesign considerations for the TCI6482. Those familiar with the TCI100 can use thecomparisons to migrate a TCI100 design to the TCI6482. In some cases there isinformation overlapping with the TCI6482 data manual. If the information does notmatch the data manual information takes precedence.
Contents1 TCI6482 Documentation ........................................................................... 32 Device Overview with Comparison to the TCI100 .............................................. 33 Device Identification (ID) ........................................................................... 54 Pin and Package Compatibility ................................................................... 55 Device Configurations and Initialization ......................................................... 66 Clocking .............................................................................................. 87 Power Supply ..................................................................................... 148 I/O Buffers .......................................................................................... 219 Peripheral Section ................................................................................ 22Appendix A TCI6482 RGMII 1.5V/1.8V to 2.5V/3.3V Translation ............................... 40
List of Figures
1 CLKIN1, CLKIN2 Single Device Clock Solution ............................................... 102 PLL1, PLL2 Multiple Device Clock Solution ................................................... 113 RIOCLK Single Device LVDS Clock Solution ................................................. 124 RIOCLK Multiple Devices LVDS Clock Solution .............................................. 125 RIOCLK Multiple Devices LVDS Clock Solution .............................................. 136 RIOCLK Multiple Devices LVPECL Clock Solution ........................................... 137 Power Supply Generation ........................................................................ 158 Recommended Power Supply Filter ............................................................ 169 Reference Voltage Generation .................................................................. 1610 Multiple DSP Remote Sense Connections .................................................... 1811 Single DSP Remote Sense Connections ...................................................... 1912 McBSP 8 Load Routing Topology .............................................................. 2713 HSTL to LVCMOS Translation .................................................................. 3514 VLYNQ Clock Divider Example ................................................................. 37A-1 RGMII Voltage Level Translation Circuit ....................................................... 40A-2 VOUT vs VIN ...................................................................................... 42A-3 125MHz Signal from A2 to B2 and From B3 to A3 ........................................... 43
List of Tables
1 TCI6482 Features, Comparison to TCI100 Processor......................................... 4
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2 TCI6482 and TCI100 JTAG (BSDL) IDs ......................................................... 53 Pin and Package Differences ..................................................................... 64 Clocking Differences between TCI6482 and TCI100 .......................................... 85 Reference Clock Requirements .................................................................. 96 Power Supply Differences ....................................................................... 147 Die Voltage Monitor Pins ......................................................................... 188 Bulk Capacitor Examples ........................................................................ 209 Capacitor Recommendations .................................................................... 2010 PTV Compensated Interfaces ................................................................... 2211 EMIFA Comparsion: TCI6482 vs TCI100 ...................................................... 2412 HPI Comparison: TCI6482 vs TCI100 .......................................................... 2513 PCI Comparison: TCI6482 vs TCI100 .......................................................... 2614 McBSP Comparison: TCI6482 vs TCI100 ..................................................... 2715 VCP2 Summary of Changes on TCI6482 ...................................................... 2816 VCP2 Usage Change on TCI6482 .............................................................. 2817 VCP2 Register Changes on TCI6482 .......................................................... 2918 TCP2 Summary of Changes on TCI6482 ...................................................... 2919 TCP2 Usage Change on TCI6482 .............................................................. 3020 TCP2 Register Changes on TCI6482 .......................................................... 3021 GPIO/Interrupt Comparison: TCI6482 vs TCI100 ............................................. 3122 Timer Comparison: TCI6482 vs TCI100 ....................................................... 3223 SRIO PLL Multiplier Settings .................................................................... 3724 JTAG/Emulation Comparison: TCI6482 vs TCI100........................................... 39
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1 TCI6482 Documentation
2 Device Overview with Comparison to the TCI100
TCI6482 Documentation
The following is a list of available documents relevant to a TCI6482 based design:•Data Manual
–TMS320TCI6482 Communications Infrastructure Digital Signal Processor, (SPRS246 ). Referred toin this document as the TCI6482 data manual.•User Guides / Reference Manuals–TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (SPRU732 )–TMS320C64x+ Megamodule Reference Guide (SPRU871 )–TMS320C64x+ DSP Cache User's Guide (SPRU862 )–TMS320C6000 Programmer's Guide (SPRU198 )–TMS320TCI648x DSP PLL Controller Reference Guide (SPRU806)–TCI648x DSP External Memory Interface (EMIF) Reference Guide (SPRU925)–TMS320TCI6482 Bootloader User's Guide–TMS320TCI6482 Preliminary Power Consumption Summary–TCI648x DSP UHPI User’s Guide (SPRU874)–TCI648x DSP PCI Reference Guide (SPRUE60)–TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (SPRU803 )–TMS320TCI648x DSP Viterbi-Decoder Coprocessor (VCP) Reference Guide (SPRUE09)–TMS320TCI648x DSP Turbo-Decoder Coprocessor (TCP) Reference Guide (SPRUE10)–TCI648x DSP General-Purpose Input/Output (GPIO) User’s Guide (SPRU725)–TMS320TCI648x DSP 64-Bit Timer User's Guide (SPRU818)–TMS320TCI648x DSP Enhanced DMA (EDMA) Controller User’s Guide (SPRU727)–TCI6482 DSP Inter-Integrated Circuit (I²C) Module User's Guide (SPRUE11)–TMS320TCI648x DSP Ethernet Media Access Controller (EMAC)/Management Data Input/Output(MDIO) User’s Guide (SPRUE12)–TMS320TCI648x DSP Universal Test and Operations PHY Interface for ATM 2 (Utopia2) User’sGuide(SPRU726)
–Serial RapidIO User’s Guide (SPRUE13 )–TMS320TCI648x DSP DDR2 Memory Controller User's Guide (SPRU894)–High Speed DSP Systems Design Reference Guide (SPRU889 )–60-Pin Emulation Header Technical Reference (SPRU655A )•Application Notes–EDMA v3.0 (EDMA3) Migration Guide for TMS320TCI648x DSP (SPRAAC1 )–Implementing Serial Rapid I/O PCB Layout on a TMS320TCI6482 Hardware Design (SPRAAB0 )–Implementing DDR2 PCB Layout on the TMS320TCI6482 (SPRAAA9 )–Using IBIS Models for Timing Analysis (SPRA839 )•Misc
– TCI6482 IBIS Model File– TMS320TCI6482 BSDL file
A high level comparison of the TCI6482 and TCI100/TCI100Q features is given in Table 1 . This table doesnot cover software differences. For more detailed comparisons of peripherals refer to the peripheralsections later in this document.
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Device Overview with Comparison to the TCI100
Table 1. TCI6482 Features, Comparison to TCI100 Processor
Hardware Features TCI6482 TCI100/TCI100Q
Peripherals EMIFA (64-bit data 1 EMIFA (64-bit data 1Not all peripheral pins bus) bus)are available at the (Clock source = (Clock source =same time. (For more AECLKIN or AECLKIN, CPU/4,details, see the SYSCLK4) CPU/6)Device Configuration (Supports SBSRAM, (Supports SBSRAM,section of the device SRAM, Sync FIFOs, SRAM, Sync FIFOs,data manual) Async memories; Async memories;SRAM, ROM, Flash) SRAM, ROM, Flash)DDR Memory 1 EMIFB (16-bit bus N/AController EMIF width)(32-bit data bus (supports SDRAMwidth) [1.8V IO] and programmable(Clock source = sync)generated from PLL2)EDMA3 (64 1 EDMA2 1independent
channels)
[CPU/3 clock rate]High-speed 1x/4x 1 N/A N/ASerial Rapid IO PortHPI (32 or 16-bit user 1 same 1selectable)
PCI (32-bit) 1 PCI (32-bit) 1[66-MHz or 33-MHz] [33-MHz]McBSP 2 McBSP 3(Internal clock sourceup to 90 MHz)UTOPIA (8-bit mode, 1 Same50-MHz, Slave-only)
10/100/1000 Ethernet 1 N/A N/AMAC (EMAC)Management Data 1 N/A N/AInput/Output (MDIO)64-bit Timers 2 - 64-bit or 32-bit Timer 3-32 bit timers(Configurable) 4-32-bit(Internal clock source:CPU Clock/6,External clock sourceup to CPU clock/24)
VLYNQ 1 N/A N/AGeneral Purpose 16 General Purpose 16Input/Output (all can Input/Output (4 canbe used as external be used as externalinterrupts) interrupts)Decoders VCP2 1 VCP 1Coprocessors
TCP2 1 TCP 1RSA 1 N/A N/AOn-Chip Memory L1P 32K-Byte L1P 16K-Byte(Configurable as (Cache only)cache and SRAM)
L1D 32K-Byte L1D 16K-Byte(Configurable as (Cache only)cache and SRAM)
L2 2048K-Byte L2 1024K-ByteCPU MegaModule Revision ID Register Read value: 0x0 N/A N/ARevision ID (MM_REVID[15:0]) (silicon revision 1.1)Byte address =0x01812000
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3 Device Identification (ID)
4 Pin and Package Compatibility
Device Identification (ID)
Table 1. TCI6482 Features, Comparison to TCI100 Processor (continued)
JTAG BSDL_ID JTAGID register Read value: 0x0008A02F JTAGID register Read value: 0x008102FFrequency Core clock Up to 1-GHz Core clock 720MHz,
850MHzVoltage Core Supply 1.2V Core Supply 1.2VIO Supplies 3.3V, 1.8V (1.5), 1.2V IO Supply 3.3VPLL and PLL PLL1 for Core Clock PLL for Core Clockcontroller Options (Software (Hardwareconfigurable) configurable)PLL2 for DDR/EMAC
ClockBGA Package 697-Pin BGA ZTZ Suffix 532-Pin BGA GLZ SuffixPackage, 0.8mm Package, 0.8mmpitch, 24mmx24mm pitch, 23x23mmProcess Technology 0.09um/7-Level Cu 0.09um/7-Level CuMetal Process Metal Process(CMOS) (CMOS)Device Part Numbers TMX320TCI6482ZTZ TMS320TCI100GLZ
The JTAG (BSDL) ID and Silicon Revision ID are different than other TMS320C64x DSP devices. TheTCI6482 device IDs are shown in the table below and are referred to as JTAG (BSDL) IDs. The JTAG(BSDL) ID is accessible via JTAG on both devices and through the JTAG ID register at address0x02A80008 on the TCI6482 device.
Table 2 identifies the JTAG (BSDL) ID differences between the TCI100 and TCI6482.
Table 2. TCI6482 and TCI100 JTAG (BSDL) IDs
JTAG (BSDL) IDDevice Variant [31:28] Part Number [27:12] Manufacturer [11:1] LSBTCI6482 xxxxb
(1)
0000000010001010b 00000010111b 1 [0]TCI100 xxxxb
(2)
0000000010000001b 00000010111b 1(1)
Variant field indicates the silicon version. Refer to the data manual and errata for current silicon versions.(2)
Variant field indicates the silicon version. Refer to the data manual and errata for current silicon versions.
The TCI6482 does not have a Silicon Revision ID as found in the TCI100.
The physical dimensions and pin out of package used for TCI6482 will be different from TCI100.Modification will be needed to account for the different physical dimensions of package and pin out.Changes in substrate may also affect the thermal characteristics of the package used for TCI6482. Seethe TMS320TCI6482 Communications Infrastructure Digital Signal Processor (SPRS246) for additionalinformation regarding package characteristics.
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5 Device Configurations and Initialization
5.1 Device Reset
5.2 Device Configuration
Device Configurations and Initialization
Table 3. Pin and Package Differences
Device Package Type (s) Pin CountTCI100 GLZ Ball Grid Array (BGA) 0.8mm pitch, 53223 x 23 mmTCI6482 ZTZ Ball Grid Array (BGA) 0.8mm pitch, 69724 x 24 mm
On the TCI6482 device, bootmode and certain device configuration/peripheral selections are determinedat device reset, while peripheral usage (enabled/disabled) is determined by the Peripheral Configurationregisters after the device reset. The peripherals on the TCI6482 device are “disabled” and need to be“enabled”. This is different than the TCI100 in which case the peripherals selected by the boot strapoptions were enabled on power-up. The basic information on configuration options, boot modes optionsand use of the Power Configuration registers can be found in the TCI6482 data manual.
There are several ways to reset the TCI6482 and these are described in the TCI6482 data manual. Thetwo external resets, POR and RESET, need to be driven to a valid logic level at all times. POR must beasserted (low) on a power-up while the clocks and power planes become stable. RESET can be usedfrom the powered up state to issue a warm reset, which performs the same as a POR except that test andemulation logic are not reset. If a warm reset is not needed, RESET can be pulled up to DVDD33.
In revision 1.1 silicon, when POR is held low the internal pull-up and pull-down resistors are disabled. Thisrequires the use of external pull-up and pull-down resistors for all pins that have their states latched byPOR. Alternatively, after POR is de-asserted long enough for the internal resistors to pull voltage levels tovalid states (> 100uS) bringing RESET low for at least 24 CLKIN1 cycles and then high again will allowre-latching the state of the configuration strapping with valid values from the internal pull-ups, pull-downs.While POR is low, large currents may be seen on the DVDD33 power plane due to floating inputs (i.e. theEMIF bus). If the user wishes to avoid these currents external pull-ups or pull-downs should be used.Refer to the TCI6482 Silicon Errata document for complete details. In revision 2.0 silicon and later theinternal pull-up and pull-down resistors will not be disabled under any conditions.
The RESETSTATz signal indicates the internal reset state. The RESETSTATz is asserted (low) on apower-on reset, warm reset, max reset, or system reset. The only reset that does not causeRESETSTATz to be asserted is a CPU reset (issued from the PCI peripheral).
The TCI6482 device configuration options are multiplexed on the EMIFA address AEA[19:0] and EMIFAbank address lines ABA[1:0]. There is one dedicated configuration pin, PCI_EN. Refer to the TCI6482data manual for details on the configuration options. All reset strapping pins have internal pull-ups orpull-downs in the range of 30K ohms. If the EMIFA bus is not used the internal pull-ups and pull-downscan be used and an external pull-up/down is only needed if the opposite setting is desired. If theconfiguration pins are routed out from the device, the internal pullup/pulldown resistor should not be reliedupon; 1K pull-ups and pull-downs are recommended for all desired settings.
The core clock PLL multiplier is not set by reset configuration strapping as it was on the TCI100. The PLLmultiplier can only be set by CPU register writes. The registers are not accessible through bootperipherals. The core clock speed when accessing the internal ROM must be not more than 750MHz. PCIand Serial RapidIO boot modes automatically change the PLL multiplier to 15X, so the CLKIN1 must beno more than 50MHz. For other boot modes it is suggested to set the multiplier early in the boot processin order to reduce boot times. For details on setting the CLKIN1 PLL multiplier and divider settings refer tosection 6.1 and the TMS320TCI648x DSP PLL Controller Reference Guide (SPRU806).
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5.3 Peripheral Configuration
5.4 Configuration Tables in I2C ROM
5.5 Boot Modes
5.6 Boot/Initialization Sequence
Device Configurations and Initialization
Other than the device reset configuration covered in Section 5.1 , all other configurations are done byregister accesses. The first step to configuring a peripheral is to enable it using Peripheral ConfigurationRegister 0 and 1. Since all peripherals not needed for the selected boot mode are disabled, a first levelboot loader may be needed to enable interfaces needed during the full boot load. For example, if theapplication code to be loaded (.OUT file) loads data into an external memory, a first level boot loader mustbe loaded and executed to enable the EMIF interface. If the Boot Mode selection specifies a particularinterface for boot, it is automatically enabled and configured. Note that Peripheral Configuration Register 0and 1 are only accessible by the CPU, therefore, it is not possible to configure these registers directlythrough a host interface like the HPI and PCI. For more details on peripheral configuration refer to theDevice Configuration section of the TCI6482 data manual.
The EMAC interface requires some PLL2 configurations. The specific settings are dependent on the MIImode. For details on PLL2 configuration refer to the TMS320TCI648x DSP PLL Controller ReferenceGuide (SPRU806).
For some peripherals, the peripheral operating frequency is dependent on the CPU core clock frequency.This should be accounted for when configuring the peripheral.
All other peripheral configurations are done within the peripheral module. For configuring the peripheralmodule refer to the specific peripheral’s user guide.
I2C ROM contents can contain Configuration Tables which allow customer defined memory map accessesduring the I2C boot mode. These accesses can be used to configure peripherals during the boot process.For details refer to the TMS320TCI6482 Bootloader User's Guide document.
The interfaces which support a boot loading process are: I2C, HPI, PCI, Serial RapidIO and EMIF (8-bitROM). In addition, a first level boot loader (loaded using one of those interfaces) can configure theEthernet or Utopia interfaces for a secondary boot load. For a summary of the boot modes supported referto the TCI6482 data manual. For details regarding boot modes, refer to the TMS320TCI6482 BootloaderUser's Guide document.
Regardless of the boot mode selected, an emulator connection can always reset the device to acquirecontrol.
If the PCI interface is enabled, it supports an optional auto-initialization feature which will load the PCIconfig registers from an I2C ROM before the boot load is performed.
Generic bring up procedure:1. Follow power-up and reset sequencing per the TCI6482 data manual.2. When the POR (or RESET on a warm boot) signal is de-asserted the boot strapping options arelatched and the boot mode selection controls what happens next:a. If the PCI interface is selected and auto-initialization is enabled, the auto-initialization is performedb. Booting over I2C loads code contents into L2, code is executed after last code section is copiedc. Booting over EMIF starts executing from the base address of CE3 spaced. Booting over HPI, PCI or Serial RapidIO puts the device in a state that waits for code to be copiedthrough those interfaces into L2 and an interrupt to initiate the execution of that code.3. Boot code (at a minimum) should configure the PLL1 core clock frequency and also enable andconfigure the required peripherals and:a. PCI and SerialRapidIO boot modes configure the PLL1 for a 15x multiplier to allow properoperation of those interfaces. After the boot load is completed, application code should change thePLL1 to final desired multiplier. Due to the use of the 15x multiplier, the CLKIN1 should be nogreater than 50MHz when selecting the PCI or SerialRapidIO boot modes.
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6 Clocking
6.1 PLLs
6.1.1 Clock PLL and PLL Controller
6.1.2 PLL Operation
6.1.3 PLL Configuration after Power-Up
Clocking
A description of the PLLs and PLL controllers along with register definitions can be found in theTMS320TCI6482 Communications Infrastructure Digital Signal Processor (SPRS246). Table 4 shows theclocking differences between the TCI6482 and the TCI100.
Table 4. Clocking Differences between TCI6482 and TCI100
Device PLL Type Input Clock Frequency Program Clock Input PurposeRange Multiplication Multiplier via SourceFactorsTCI100 Analog PLL 42MHz - x1, x6, x12, x20 HW config External clock CPU clock75MHz
(1)
inputTCI6482 Analog PLL 33 MHz - x15, x20, x25, SW config External clock CPU clock(Main device 66MHz
(2) (1)
x30, x32 inputclock)TCI6482 Analog PLL 12.5MHz - x10 N/A External clock DDR2 and(Used for DDR2 26MHz input Ethernet (exceptand EMAC MII)
(3)
clocking)
(1)
Supported frequency range and multipliers may change. Refer to the data manual for the latest information.(2)
Clock range is limited to 50MHz if using PCI or SerialRapidIO boot modes.(3)
In silicon version 2.0 and all subsequent versions this PLL is not required for RMII operation.
The PLL1 controller powers up in bypass (x1) mode with PLL1 in reset. Some boot modes change thismultiplier (see Section 5.6 ). After the PLL1 is out of reset and running, changing the PLL1 controllermultiplier and divider values (or the reference clock frequency) involves using the PLL reset mode to clearthe lock condition.
The PLL reset mode is used under the following conditions:•After power is applied, the PLL is automatically placed in reset mode•To change the input frequency (CLKIN1)•To change the value in any divider or multiplier register
The procedures for changing the PLL are described in Section 6.1.3 and Section 6.2 .
The following process should be followed to set the PLL multiplier after power-on reset. The wait times areconservative durations to guarantee proper operation.1. Allow PLL1 to become stable, see the device data manual for stabilization time.2. Program PLLCTL.PLLENSRC=0 to enable the PLLCTL.PLLEN bit.3. Program PREDIV, PLLM for the desired multiplier and divider.4. Set PLLRST=0 to de-assert PLL reset.5. Wait for 3000 CLKIN1 cycles for the PLL to lock.6. Set PLLEN=1 to switch from Bypass mode to PLL mode.
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6.2 PLL Configuration During Operation
6.3 PLL1, PLL2, and SRIO Reference Clock Solutions
6.3.1 Clock Requirement
6.3.2 CLKIN1/CLKIN2 Solutions
6.3.2.1 Single Device Solution
Clocking
The following process should be followed to change the PLL after it has been operating. The wait timesare conservative durations to guarantee proper operation.1. Program PLLCTL.PLLENSRC=0 to enable the PLLTL.PLLEN bit.2. Program PLLEN=0 (PLL bypass mode) and PLLRST=1 (reset PLL) in PLLCTL register.3. Program PREDIV, PLLM for the desired multiplier and divider.4. Wait for at least 256 CLKIN1 cycles for the PLL to reset.5. Set PLLRST=0 to de-assert PLL reset.6. Wait for 3000 CLKIN1 cycles for the PLL to lock.7. Set PLLEN=1 to switch from Bypass mode to PLL mode.
This section describes the clock requirements and a system solution for the input clocks to the TCI6482device that require special consideration. CLKIN1 is the reference clock to PLL1 which is used to generatethe core clock (up to 1GHz). This clock requires a low jitter clock source. CLKIN2 is the reference clock toPLL2 which is used to generate the clock for the DDR2 and EMAC subsystems. This clock, when used asthe reference clock to the DDR2 subsystem, must be low jitter. The SRIO reference clock (RIOCLK,RIOCLK) requires a differential low jitter clock source and proper termination.
It is also assumed that multiple TMS320TCI6482 devices may be used on a board so the proposedsystem solutions include clock fanout buffers.
The clock requirements are given in Table 5 .
Table 5. Reference Clock Requirements
Logic Input Jitter
(1)
Trise/Tfall Duty Cycle Stability Freq
(2)
PLL Freq
CLKIN1 LVCMOS or LVTTL 100pS pk-pk Max 1.2nS 40/60% 50PPM 50MHz 1GHzCLKIN2 LVCMOS or LVTTL 100pS pk-pk Max 1.2nS 40/60% 50PPM 25MHz 250MHzRIOCLK, Differential LVDS or 4pS RMS 50pS - 45/55% 50PPM 125MHz, 3.125GHzRIOCLK LVPECL 56ps pk-pk @ 700pS 156.25MHz1x10E
-12
BER
(1)
Assumes a Gaussian distribution. Peak-peak jitter assumes 100,000 points.(2)
Recommended operating frequencies based on component availability and supported PLL multipliers.
Trise/Tfall values are given for CLKIN1 and CLKIN2 transitions from 0.8V to 2.0V. This is equivalent to amax Trise/Tfall of 2nS from 20% to 80% of 3.3V. RIOCLK Trise/Tfall values are given for 20% to 80% ofthe voltage swing. These rise/fall times assume the maximum jitter values. Slower rise/fall times can beused if the jitter is lower.
CLKIN1 and CLKIN2 have similar requirements for a clock source so the same clocking solutions (exceptfor frequency) can be used for both.
It is assumed that the source clock for each of these clocks is an oscillator on the same board as theTMS320TCI6482. Use of distributed clocks may require a jitter cleaner device such as the CDCM7005(refer to http://focus.ti.com/docs/prod/folders/print/cdcm7005.html ). Most PLL based clock generators donot meet the input jitter requirement. If an on-board oscillator is used with one TMS320TCI6482 no othercomponents should be needed except for termination resistors.
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6.3.2.2 Fanout Solutions
Clocking
For CLKIN1 and CLKIN2, a low jitter CMOS oscillator would be sufficient. A series termination resistor(nominally 22 ohms) at the source is suggested (refer to Figure 1 ). An example of an appropriate oscillatoris:
•Vectron VCC1 series 3.3V CMOS oscillator–http://www.vectron.com/products/xo/vcc1.pdf
This oscillator has not been tested but is an example of an oscillator that meet the specificationrequirements for CLKIN1 and CLKIN2.
Figure 1. CLKIN1, CLKIN2 Single Device Clock Solution
For systems with multiple TMS320TCI6482 devices it may be preferred to use one oscillator and a fanoutbuffer instead of multiple oscillators. This would allow for fewer components as well as lower cost. Thefanout buffer increases the jitter at the clock input so care must be taken in selecting the combination ofoscillator and fanout buffer.
In most cases the same oscillators described in Section 6.3.2.1 can be used for the fan out case. Theoscillator output specifications should be compared to the fanout buffer input specifications to make surethey are compatible.
A low jitter fanout buffer is required which generally means a non-PLL based fanout buffer should be used.Suggested solutions for fanout buffers are:•TI CDCV304 1:4 Clock buffer–http://focus.ti.com/lit/ds/symlink/cscv304.pdf
•TI CDCVF2310 1:10 Clock buffer–http://focus.ti.com/lit/ds/symlink/cdcvf2310.pdf
•CDCV304 jitter information: http://focus.ti.com/lit/an/scaa052/scaa052.pdf
•CDCVF2310 jitter information: http://focus.ti.com/lit/an/scaa064/scaa064.pdf
Figure 2 shows a diagram of a solution that allows an oscillator and a fanout buffer to provide CLKIN1 orCLKIN2 for up to 4 DSPs. Up to 10 DSPs could be supported with the CDCVF2310 which would be thesame circuit without the series resistors since the CDCVF2310 has built-in 22ohm resistors. The bufferoutputs should not be used to drive additional fanout buffers since the jitter will accumulate.
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6.3.2.3 Layout Recommendations
6.3.3 RIOCLK/ RIOCLK Solutions
Clocking
Figure 2. PLL1, PLL2 Multiple Device Clock Solution
Another solution would be to use very low jitter PLL clock generators/buffers. TI’s CDCE706 andCDCE906 have been tested with at 25MHz and 50MHz and shown to meet the required jitterspecifications.
Placement, Terminations
•The oscillator should be placed close to the destination.•Series termination should be placed close to clock source.•The value of the series termination resistor should be optimized to reduce over-shoot and under-shootwhile not violating the Trise/Tfall input specification. TI suggests the customer use IBIS simulations todetermine the correct value of the termination resistor.
Trace Routing
•A GND plane should be placed below the oscillator.•Digital signals should not be routed near or under the clock sources.•Maintain at least 25 mil spacing to other traces.
The SerialRapidIO reference clock requires special considerations because it is differential, must be lowjitter, and requires termination. Either an LVDS or LVPECL clock source can be used but they requiredifferent terminations. The input buffer sets its own common mode voltage so AC coupling is necessary. Italso includes a 100ohm differential termination resistor, eliminating the need for an external 100ohmtermination when using an LVDS driver. For generation information on AC termination schemes, refer toAC Coupling Between Differential LVPECL, LVDS, HSTL and CML (scaa059 ). For information on DCcoupling refer to DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML (scaa062 ) .
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6.3.3.1 Single Device Solution
LOWJITTER
OSCILLATOR
Example:
Pletronics
LV77D
RIOCLK
DSP
RIOCLK
0.01uF
0.01uF
RIOCLK
DSP
LOWJITTER
OSCILLATOR
Example:
Pletronics
PE77D
150ohm
150ohm
0.01uF
0.01uF
RIOCLK
6.3.3.2 Fanout Solutions
Clocking
It is assumed that the source clock is an oscillator on the same board as the TMS320TCI6482. Use ofdistributed clocks may require a jitter cleaner device such as the CDCM7005 (refer tohttp://focus.ti.com/docs/prod/folders/print/cdcm7005.html ) or the CDCL6010. If an on-board oscillator isused with one TMS320TCI6482 no other components should be needed except for terminations.
For the Serial rapid IO reference clock examples of appropriate oscillators are:•Pletronics LVDS LV77D oscillator–http://www.pletronics.com/pdf/LV77D%203.3v.pdf
•Pletronics LVPECL PE77D oscillator–http://www.pletronics.com/pdf/PE77D%203.3v.pdf
These oscillators have not been tested but are examples of oscillators that meet the specificationrequirements for RIOCLK/ RIOCLK.
Figure 3 shows an LVDS based solution including terminations. Figure 4 shows an LVPECL basedsolution including terminations. The terminations shown are still being investigated and should beconsidered preliminary.
Figure 3. RIOCLK Single Device LVDS Clock Solution
Figure 4. RIOCLK Multiple Devices LVDS Clock Solution
For systems with multiple TMS320TCI6482 devices it may be preferred to use one oscillator and a fanoutbuffer instead of multiple oscillators. This would allow for fewer components as well as lower cost. Thefanout buffer increases the jitter at the clock input so care must be taken in selecting the combination ofoscillator and fanout buffer.
In most cases the same oscillators described in Section 6.3.3.1 can be used for the fan out case. Theoscillator output specifications should be compared to the fanout buffer input specifications to make surethey are compatible.
A low jitter fanout buffer is required which generally means a non-PLL based fanout buffers should beused. Suggested solutions for a fanout buffers are:
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LOWJITTER
OSCILLATOR
Example:
Pletronics
LV77D
RIOCLK
SN65LVDS108
RIOCLK
DSP1
RIOCLK
DSP8
CLK0
CLK0#
CLKN
CLK7#
100ohms
0.01uF
0.01uF
0.01uF
0.01uF
R I O C L K
R I O C L K
R I O C L K
LOWJITTER
OSCILLATOR
Example:
Pletronics
PE77D
RIOCLK
CDCLVP110
RIOCLK#
RIOCLK
DSP1
RIOCLK#
RIOCLK
DSP10
RIOCLK#
CLK0
CLK0#
CLKN
CLK9#
50ohm50ohm
50ohm
150
ohm
150
ohm
150
ohm
150
ohm
0.01uF
0.01uF
0.01uF
0.01uF
Clocking
•TI SN65LVDS108 LVDS 1:8 Clock fanout buffer–http://focus.ti.com/lit/ds/symlink/sn65lvds108.pdf
•TI CDCLVP110 LVPECL 2:10 Clock fanout buffer–http://focus.ti.com/lit/ds/symlink/cdclvp110.pdf
There are also 4-port and 16-port versions of the SN65LVDS108. For an integrated jitter cleaner andmultiple clock output buffer the CDCL6010 can be used.
These buffers have not been tested but are examples of buffers that meet the specification requirementsfor RIOCLK / RIOCLK.
Jitter performance for the SN65LVDS108 is found in its datasheet. For the CDCLVP110 the jittercharacteristics of these parts refer to:•CDCLVP110 Jitter Info: http://focus.ti.com/lit/an/scaa068/scaa068.pdf
Figure 5 shows a diagram of a solution that allows an LVDS oscillator and an LVDS fanout buffer toprovide RIOCLK / RIOCLK for up to 8 DSPs. Figure 6 shows an LVPECL solution for up to 10 DSPs. Thefanout buffer outputs should not be used to drive additional fanout buffers since the jitter will accumulate.
Figure 5. RIOCLK Multiple Devices LVDS Clock Solution
Figure 6. RIOCLK Multiple Devices LVPECL Clock Solution
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6.3.3.3 Layout Recommendation (LVDS and LVPECL)
7 Power Supply
7.1 Power Plane Generation
Power Supply
Placement:
•The oscillator, buffer, and DSPs should be placed as close to each other as practical•Fanout buffers should be placed in a central area to equalize the trace lengths to each DSP•AC coupling capacitors should be placed near the receivers•50ohm resistors used in LVPECL DC termination should be placed near the receiver•150ohm resistors used in LVPECL AC termination should be placed near the driver•100ohm resistors used in LVDS terminations should be placed near the receiver
Trace routing:
•A GND plane should be placed below the oscillator•Digital signals should not be routed near or under the clock sources.•Traces should be 100 ohm differential impedance and 50 ohm single ended impedance•Clock routes should be routed as differential pairs with no more than 2 vias per connection (notcounting pin escapes)•The number of vias on each side of a differential pair should match•Differential clock routes must be length matched to within 10 mils•Maintain at least 25 mil spacing to other traces
A comparison of the voltages needed for the TCI6482 vs. the TCI100 is shown in Table 6 . For definitionsfor the power supplies refer to the TCI6482 data manual.
Table 6. Power Supply Differences
Core Supply Voltage I/O Supply Voltages (Tolerances are +/-5%) Analog Supply Voltages(Tolerances are +/-5%)Device CVDD TOL DVDD33 DVDD18 DVDD15 DVDD12 PLL DDR2 SRIO(SRIO) DLLTCI6482 1.2V ±3% 3.3V 1.8V 1.5V 1.2V 1.8V 1.8V 1.2Vor
1.8VTCI100 1.1V ±3% 3.3V N/A N/A N/A 3.3V N/A N/A1.2V ±3%
All power supplies may be generated from switching supplies with the exception of the SRIO 1.2Vsupplies (DVDD12, AVDDA and AVDDT). Due to the noise sensitivity of the SRIO SERDES links a linearregulator with proper filtering is recommended. A switching regulator plus filtering can be used if the ACnoise is guaranteed to be less than +/-25mV. One solution for a suitable 1.8V to 1.2V linear regulator isthe UC385-ADJ (http://focus.ti.com/lit/ds/symlink/uc385-adj.pdf ) which can support multiple DSPs. Filtersare also recommended for some other voltage planes. An overview of the recommended power supplygeneration architecture is shown in Figure 7 .
The DVDD15 supply can be operated at either 1.5V or 1.8V. Operation at 1.8V will consume somewhatmore power than 1.5V operation but eliminates the need for a 1.5V supply. Most Ethernet PHYs thatsupport RGMII v2.0 operation support the HSTL interface at either 1.5V or 1.8V.
The optional power supplies are noted with dashed lines. These are power pins that can be connecteddirectly to VSS if the associated peripheral is not used and is disabled. If power supplies for SRIO orRGMII are to be connected to VSS, care should be taken that all associated power for that interface mustbe connected to VSS. Removing power from these interfaces will result in the inability to boundary scantest these interfaces. Refer to the data manual for details.
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Switching
regulator
3.3 V
(RGMII)
Switching
regulator
1.5 V
Switching
regulator
1.8 V
1.5 V HSTL used
1.8 V
HSTL
used
Filter
Filter
Filter
Filter
Filter
Adjustable
switching
regulator
1.2 V
(SRIO)
Linear
regulator
1.2 V
Filter
Filter
Board voltage
(i.e. 5 V or 12 V)
DVDD33
DVDD15 (RGMII)
DVDD18
DVDDR (SRIO)
AVDLL1 (DDR2)
AVDLL2 (DDR2)
PLLV1
PLLV2
CVDD
DVDDRM (SRIO)
DVDD12 (SRIO)
AVDDA (SRIO)
AVDDT (SRIO)
DVDD18
Required
Optional
TCI6482
voltage planes
Power Supply
Figure 7. Power Supply Generation
Filters on AVDLL1 and AVDLL2 are not needed if the DDR2 interface is not used.
The recommended filter circuit from Figure 7 is given in Figure 8 . The filter component shown is a fromMurata part. If a different part is cross-referenced, the frequency envelope must be considered. Thissolution has been tested.
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NFM18CC222R1C3
0.1uF560pF
1K1%
1K1%
DVDD18
VREFSSTL(DDR2)
DVDD15
VREFHSTL(RGMII)
0.1uF
0.1uF
1K1%
1K1%0.1uF
0.1uF
7.2 Power Supply Sequencing [D]
Power Supply
Figure 8. Recommended Power Supply Filter
The reference voltages used for the SSTL (DDR2) and HSTL (RGMII) interfaces are intended to operateat half the voltage supplied to those I/Os. This is done through a simple voltage divider as shown inFigure 9 . More details on VREFSSTL can be found in: Implementing DDR2 PCB Layout on theTMS320TCI6482 (SPRAAA9 ). Note that if the RGMII interface is not used and is disabled, VREFHSTLcan be connected to directly to VSS.
Figure 9. Reference Voltage Generation
The recommended power sequence is described in the TCI6482 data manual. This is the sequence whichis used for manufacturing device test. Other sequences may work but have not been verified at this time.Therefore, it is strongly recommended that this sequence be followed.
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7.3 Voltage Plane Power Requirements
7.4 Power Supply Layout Recommendations
7.5 Voltage Tolerances, Noise, and Transients
7.5.1 Using Remote Sense Power Supplies
Power Supply
Although the power sequence has 3.3V I/O ramping before the core voltage, bus contention will not occurin this case due to special circuitry that has been added that hold the 3.3V I/Os in tri-state during thepower ramp-up period.
There are multiple ways to generate a controlled power sequence. A microcontroller or PLD can be usedto control power supply sequencing. Alternatively, TI has power management products that can be usedsuch as the TPS3808 (http://focus.ti.com/lit/ds/symlink/tps3808g33.pdf ).
Power requirements are highly dependent on the usage of the device. This includes which peripherals areused as well as the operating frequencies. In order to generate an estimate of the TCI6482 power for aparticular application, refer to the TMS320TCI6482 Preliminary Power Consumption Summary.
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimizeinductance and resistance in the power delivery path. Additionally, when designing for high-performanceapplications utilizing the C6000 platform of DSPs, the PCB should include separate power planes for core,I/O and ground, all bypassed with high-quality low-ESL/ESR capacitors.
For VREFHSTL and VREFSSTL, one reference voltage divider should be used for both the TCI6482 andthe reference voltage input on the attached device. The same supply should also be used for the I/Ovoltages between the 2 parts. The VREF resistor divider should be placed between the 2 devices and theroutes made as directly as possible with a minimum 20 mil wide trace. There should be a 2x trace widthclearance between the routing of the reference voltage and any switching signals.
The DLL signals (AVDLL1 and AVDLL2) can be routed using minimum 15 mil wide traces. There shouldbe a 2x trace width clearance between this and any switching signals.
The filter circuits should be placed as close to the corresponding TCI6482 power supply pin(s) aspossible. No digital switching signals should be routed near or directly under the filter circuits.
The voltage tolerances specified in the datasheet include all DC tolerances and the transient response ofthe power supply. These specify the absolute maximum and minimum levels that must be maintained atthe pins of the TCI6482 under all conditions. Special attention to the power supply solution is needed toachieve this level of performance, especially the 3% tolerance on the core power plane (CVDD).
In order to maintain the 3% tolerance at the pins, the tolerance must be a combination of the power supplyDC output accuracy, the voltage drop from the supply to the load and the effect of transients. Areasonable goal for the DC power supply output accuracy is 1.5%, leaving 1.5% for the transients. At 1.2Va 3% tolerance is +/-36mV. This allows 18mV of DC accuracy from the output of the power supply andanother 18mV due to transients.
Power plane IR drop is another factor to consider, especially if there are multiple DSPs in a group on aboard. Power planes, even if no splits are present, have impedance. With large currents running acrossthe power planes the voltage drop must be considered. This same issue also applies to ground planeswith heavy currents.
Use of a power supply that supports the remote sense capability allows the power supply to control thevoltage at the load. Special layout care must be used to keep this sense trace from being lost during PCBlayout. One solution is placement of a small resistor at the load and connecting the sense trace to thevoltage plane through it. If a group of DSPs on the board are supplied by a single core power supply, thesense resistor should be placed at the center of this group. If a negative sense pin is supported by thevoltage regulator it should be handled in a similar way. An example of this type of implementation isshown in Figure 10 .
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TCI6482
#1
VDD
VSS
TCI6482
#3
VDD
VSS
TCI6482
#2
VDD
VSS
TCI6482
#4
VDD
VSS
+SENSE
VSS
-SENSE
VOUT
0ohms
0ohms
VDD
VSS
REGULATOR
Routedasasignal
Routedasasignal
VCCVDD
VDD
VDD
VSSVSS
VSSVSS
VDDandVSS
routedasplanes
VDD
VSS
Power Supply
Figure 10. Multiple DSP Remote Sense Connections
If the connection is between one DSP and one voltage regulator, there are voltage monitor pins that canbe used for this case. The monitor pins indicate the voltage on the die and therefore provide the bestremote sense voltage. Early TCI6482 data manuals have these pins grouped with their respective powersupplies. The voltage monitor pins are described in Table 7 .
Table 7. Die Voltage Monitor Pins
Voltage Plane Pin Number Description
CVDDMON N1 Die side core voltage monitorDVDD33MON L6 Die side 3.3V (DVDD33) voltage monitorDVDD18MON A26 Die side 1.8V (DVDD18) voltage monitorDVDD15MON F3 Die side 1.5V or 1.8V (DVDD15) voltagemonitor
These monitor pins should be connected directly to the positive side sense pin of the voltage regulator.This may not be needed if the regulator used has a low impedance path between its VOUT and +SENSEpins. Since the voltage regulator output could become unstable and drive to a high voltage if the positivesense line does not receive the correct voltage it is recommended to place a 100 ohm resistor near theDSP between the voltage plane and the monitor pin. If the VDDMON connection to the DSP is not presentfor some reason the positive sense will still regulate to the proper voltage. If a negative sense pin isprovided by the regulator this should be connected to the GND plane near the DSP using a 0 ohmresistor. The single DSP remote sense connections are shown in Figure 11 .
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VDDMON
VDD
VSS
100ohms
0ohms
+SENSE
VSS
-SENSE
VOUT
Routedasasignal
Routedasasignal
REGULATORTCI6482
VDDVDD
VSSVSS
VDDandVSS
routedasplanes
7.5.2 Voltage Plane IR Drop
7.6 Power-Supply Decoupling and Bulk Capacitors
Power Supply
Figure 11. Single DSP Remote Sense Connections
The voltage gradient (IR drop) needs to be considered whether or not a supply with the remote sensecapability is used. The DSPs closer to the supply will have a slightly higher voltage and the DSPs fartherfrom the supply will have a slightly lower voltage. This voltage differential can be minimized by making thecopper planes thicker or by spacing the DSPs across a wider area of the plane. Be sure to consider boththe core power plane(s) and the ground plane(s). The resistance of the plane can be determined by thefollowing formula:
R = rho * length / (width * thickness)
where rho is the resistivity of copper equal to 1.72E-8 ohm-meters. PCB layer thickness is normally statedin “ounces”. One ounce of copper is about 0.012 inches or 30.5E-6 meters thick. The width must bederated to account for vias and other obstructions. A 50mm wide strip of 1oz copper plane derated 50%for vias will have a resistance of 0.57mohms per inch.
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) aspossible close to the DSP. Assuming 0402 caps, the user should be able to fit the number of capacitorsgiven in Table 9 . These caps need to be close to the DSP, no more than 1.25 cm maximum distance to beeffective. Ideally, these caps should be connected directly to the via attached to the BGA power pin.Parasitic inductance limits the effectiveness of the decoupling capacitors; therefore the physically smaller0402 capacitors are recommended. As with selection of any component, verification of capacitoravailability over the product’s production lifetime should be considered.
Proper capacitance values are also important. Small bypass caps (near 560 pF) should be placed closestto the power pins. Medium bypass caps ( 100 nF or as large as can be obtained in a small package)should be the next closest. TI recommends placing decoupling capacitors immediately next to the BGAvias, using the “interior” BGA space and at least the corners of the “exterior”. The inductance of the viaconnect can eliminate the effectiveness of the capacitor so proper via connections are important. Tracelength from the pad to the via should be no more than 10 mils and the width of the trace should be thesame width as the pad.
Larger caps can be placed further away for bulk decoupling. Large bulk caps should be furthest away (butstill as close as possible).
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7.6.1 Selecting Bulk Capacitance
7.6.2 Recommended Capacitance
Power Supply
There are 2 factors that need to be considered when selecting the bulk capacitance: the effective ESR forthe power plane capacitors, and the amount of capacitance needed to provide power during periods whenthe voltage regulator cannot respond.
The overall impedance of the core power plane is determined by:
(Allowable Voltage Deviation due to Current Transients) / (Max Current)
In Section 7.5 , it was suggested that the allowable voltage deviation allowed due to transient response is18mV. The max transient current is estimated at 1.5A. So the impedance requirement is 18mV / 1.5Amps= 12mohms. The power plane also has some impedance. An estimate of 2mohms will require a totaleffective ESR of 10mohms. So the effective ESR of the bulk capacitors should not exceed this value.Multiple bulk capacitors in parallel will help achieve this overall ESR.
The amount of the bulk capacitance is determined by the amount of time that the power regulator cannotrespond to the power demand and the amount of power that needs to be delivered during this time. Themaximum current change measurements have been made which show:
•Max current swing: 1.5Amp
The decoupling caps provide the immediate current through the transition but the bulk capacitors need tosupply this current until the voltage regulator can respond. A typical power regulator would have about a10KHz bandwidth with a large capacitive load (needed to maintain the 18mV deviation). Assuming thisbandwidth and a 1.5A current transient, the minimum bulk capacitance needed is estimated at 1500uF. Sofor this case the bulk capacitance needs to add up to 1500uF and create an effective ESR of 10mohms.The capacitance may need to be further increased to cover temperature derating. Examples of suitablecapacitors are shown in Table 8 .
Table 8. Bulk Capacitor Examples
Manufacturer Type Part Number C Vmax ESR QTYAVX Tantalum TPSD337K004R0035 330uF 4V 35m Ω5KEMET Tantalum T530X687M004ASE005 680uF 4V 5m Ω3SANYO POS-CAP 2R5TPD1000M5 1000uF 2.5V 5m Ω2
Capacitor selection should be done as shown above for the specific power supply implementation. Ifmultiple TCI6482 devices are used on a single core power plane the total capacitance could be reducedper device if the expectation was that the transients would not occur on all devices simultaneously.
Recommended capacitor selection is given in Table 9 where it is also compared with the TCI100 capacitorrecommendations. The TCI6482 capacitor selection does not necessarily include power supply outputcapacitance. Output capacitors are provided along with the power supply reference designs.
Table 9. Capacitor Recommendations
TCI6482 TCI100Voltage Capacitors Total Description Voltage Capacitors Total DescriptionSupply Capacitance Supply CapacitanceCVDD 10 * 560pF 2084uF 1.2V Core CVDD 1 * 330uF 333.2 uF Core20 * 100nF 32 * 100nF3 * 680uF
2 * 22uFDVDD33 16 * 560pF 330uF 3.3V I/O DVDD 1 * 330uF 333.2 uF I/O24 * 100nF 32 * 100nF1 * 330uF
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