GC5328
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SLWS218A –OCTOBER 2009–REVISED OCTOBER 2009
CREST FACTOR REDUCTION (CFR)
The GC5328 CFR block selectively reduces the peak-to-average ratio (PAR) of wideband digital signals. There
are four peak detection cancellation sections in series in the CFR block. Each stage compares the estimated
peak at the stage input with the target, and subtracts a scaled cancellation peak from the signal. There are 24
cancellers pooled among the four stages. The CFR interpolation filter must have at least 1.6× bandwidth, typical
is 2× BBClock to signal bandwidth.
There are four canceller memories and an update shadow memory that can be used for the auto-IPDL UMTS
select cancellation filter. The shadow memory allows the user to update one of the four filter banks during
operation. The CFR block has a composite RMS meter that can select the CFR input or output for monitoring.
The CFR block for WCDMA reduces TM1, TM3 signals for four adjacent carriers to 6.5 db PAR within the 3GPP
limit. The Wimax 10 reduction for two adjacent carriers is to 8.5 db PAR. TDSCDMA and CDMA performance is
limited by the carrier allocations and carrier coding.The CFR processing complex BW is limited to 62.5% of the
baseband clock rate.
FRACTIONAL FARROW RESAMPLER (FR)
The fractional resampler block takes the peak-reduced composite signals from CFR and resamples this through
fractional interpolation to the DPD processing rate. The user-programmable Farrow resampler supports
upsampling rates from 1× to 64×, with 16-bit precision on the interpolation ratio. After the fractional interpolation,
a complex mixer is available to provide a composite carrier IF offset frequency. A peak I or Q monitor is
provided.
DIGITAL PREDISTORTION (DPD)
The DPD block provides predistortion for up to Nth-order nonlinearities, and can correct multiple orders and
lengths of PA memory effects. The circular hard limiter provides a circular clipper that limits the
magnitude-squared value to –6 dbFS. This is optimized for hardware, and for the allowed gain expansion in the
nonlinear DPD correction.
The DPD has an RMS power meter, and a peak I or Q monitor.
The predistortion is performed for the nonlinear correction in the DPD section. The linear correction is performed
in the Tx equalizer. The predistortion correction terms are computed by an external processor (TMS320C6727
DSP) based on capture buffer information and the DPD software.
The DSP sets up the condition for collecting capture buffer data, retrieves the captured data over the EMIF bus,
and then performs calculations to compute the error and corrections to be used for the transmit path.
The host interface controls the mode of operation of the software in the TI DSP. TI provides a base delivery of
'C6727 software to GC5328 customers that achieves a typical ACLR improvement of 20 dB or more when
compared to a PA without DPD.
DPD CLOCK INPUT
The DPD clock input is an LVDS, low-jitter clock.
BULK UPCONVERTER (BUC)
The bulk upconverter block can interpolate the DPD block output by 1×, 1.5×, 2×, or 3× with a complex output.
The BUC interpolation blocks of 2 and 1.5 can provide 1×, 2×, or 3× interpolation for complex signals. The 1.5×
interpolation after DPD is performed by interpolating by 3 in the BUC and decimating by 2 in the OFMT block.
The BUC mixer can translate the composite IQ predistorted Tx output if the BUC Interpolation is > 1. Note: the
BUC interpolation of 1, 1.5, or 2 is recommended.
OUTPUT FORMATTER AND DAC INTERFACE (OFMT)
The output format and DAC interface presents the GC5328 output in the proper format for the different output
interfaces. The output formatter supports a test pattern for testing the DAC5682Z interface. The two output
interfaces supported for the GC5328 are:
• DAC5682 interleaved IQ
• DAC5688 parallel IQ or interleaved IQ
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Product Folder Link(s): GC5328
