Texas Instruments PCM4222EVM User manual

User's GuideSBAU124 – December 2006
PCM4222EVM User's Guide
This document serves as a reference for the PCM4222EVM evaluation module. Whenused in conjunction with commonly available audio test equipment, the PCM4222EVMprovides a complete environment for evaluating the functionality and performance ofthe PCM4222 integrated circuit. Indirectly, the PCM4222EVM serves as an evaluationplatform for the PCM4220 integrated circuit; the PCM4220 is a subset derivative of thePCM4222 device.
This document includes information regarding absolute operating conditions,power-supply requirements, and hardware configuration for the evaluation module. Theelectrical schematics and bill of materials are also included for reference purposes.Throughout this document, the acronym EVM and the phrase evaluation module aresynonymous with the PCM4222EVM.
Contents1 Introduction .......................................................................................... 32 Hardware Configuration ............................................................................ 63 Hardware Reference .............................................................................. 16
List of Figures
1 PCM4222 Functional Block Diagram ............................................................ 32 Simplified Block Diagram for the PCM4222EVM Evaluation Module ........................ 53 Power Supply Jumper Configuration ............................................................. 74 PCM4222EVM Schematics, Page 1 of 2 ...................................................... 175 PCM4222EVM Schematics, Page 2 of 2 ...................................................... 18
List of Tables
1 Absolute Operating Conditions ................................................................... 62 Recommended Power Supply Range............................................................ 73 Master Clock Source Selection ................................................................... 94 Master Clock Frequencies for Common Output Sampling and Data Rates ................ 95 PCM Output Mode Configuration ............................................................... 106 PCM Sampling Mode Selection ................................................................. 107 Audio Serial Port Header Configuration ........................................................ 118 Audio Serial Port Slave/Master Mode Selection .............................................. 119 Audio Serial Port Data Format Selection ...................................................... 1110 TDM Sub-frame Assignment .................................................................... 1211 PCM Output Word Length Selection ........................................................... 1212 Digital Decimation Filter Configuration ......................................................... 1213 Digital High-Pass Filter Switch Operation ...................................................... 1314 DIT4192 Serial Data and Clock Enable Operation ........................................... 1315 DIT4192 Master Clock Divider Configuration .................................................. 1316 DIT4192 Data Format Selection ................................................................ 1417 DIT4192 Transmission Mode Configuration ................................................... 1418 DSD Data Port Header Pin Configuration ..................................................... 15
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19 DSD Output Mode Configuration ................................................................ 1520 DSD Output Rate Selection ...................................................................... 1521 Modulator Data Port Header Pin Configuration ............................................... 1622 Multi-Bit Modulator (MBM) Output Mode Configuration ...................................... 1623 Bill of Materials .................................................................................... 19
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1 Introduction
Reference
Multi-Bit
Delta-Sigma
Multi-Bit
Delta-Sigma
Digital
Filters
Audio
Serial
Port
DSD
Engine
Reset
Logic
Control
and
Status
Master Clock
and Timing
VINL+
VCOML
REFGNDL
VREFL
S/M
FMT0
FMT1
OWL0
OWL1
SUB0 (WCK0)
SUB1 (MCK0)
PCMEN
FS0 (MOD3)
FS1 (MOD4)
OVFL
OVFR
MODEN
DSDEN (MOD6)
DSDCLK
DSDL
DSDR
DSDMODE
VCC1
VCC2
AGND
AGND
AGND
AGND
AGND
AGND
DGND
DGND
DGND
VDD
RST
LRCK
BCK
DATA
DF (MOD5)
HPFDR (MOD1)
HPFDL (MOD2)
VREFR
MCKI
REFGNDR
VCOMR
VINL-
VINR+
VINR-
Introduction
The PCM4222EVM evaluation module from Texas Instruments provides a convenient platform for testingthe PCM4222 , a high-performance, stereo audio analog-to-digital (A/D) converter integrated circuit.Figure 1 shows a block diagram of the PCM4222 device. Refer to the PCM4222 product datasheet foradditional information and details regarding this product. The PCM4222EVM evaluation module includesanalog input and digital output circuitry with common audio connectors, providing a direct interface toaudio test systems for measurement and evaluation.
Figure 1. PCM4222 Functional Block Diagram
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Introduction
The primary features of the PCM4222EVM include:•Simple configuration using switches and power-supply jumpers.•Two differential input buffer/filter circuits employing the Texas Instruments OPA1632 fully differentialamplifer integrated circuit.•Two Texas Instruments DIT4192 digital audio interface transmitters, providing AES3-encoded outputdata. Transformer coupled 110 Ωbalanced and 75 Ωunbalanced outputs are provided. Single-Channel,Double Sampling Frequency operation is supported.•A buffered audio serial port header supports connection to external hardware or test equipmentsupporting Philips' I
2
S™, Left Justified, or Time Division Multiplexed (TDM) audio interface formats forPCM output data.•A buffered data port header provides one-bit Direct Stream Digital (DSD) output data and theassociated bit clock for the DSD output.•A buffered modulator output port header provides access to the PCM4222 6-bit modulator data outputsand clocks.•Support for onboard or external clock generation. Two onboard crystal oscillators provide support forcommon audio sampling rates, including 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, and 192kHz.•Light emitting diode (LED) overflow indicators for the left and right audio channels.•Minimum power-supply requirements: ±6V to ±15V for the analog section, and +5V for the digitalsection.
•The PCM4222 analog supply may be generated from an onboard +4.0 linear voltage regulator, or anexternal regulated dc power source.•A +3.3V supply, used to power the majority of the digital circuitry and the PCM4222 digital section,may be generated from the +5.0V digital supply using an onboard linear voltage regulator.Alternatively, an external regulated dc power source may be selected, supporting digital supplyvoltages as low as +2.4V.
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S/M
FDA
FDA
DIT
DIT
Analog
Power
Audio
Serial
Port
Digital
Power
DSD
Data
Port
Modulator
Output
Port
J6
J5
J4
J12
J1
Left Cha lnne
Analog I tnpu
J2
Right Channel
Analog I tnpu
U1
PCM4222 FP B
SW6
SW1
and
SW2
AES3
Out #1
AES3
Out #2
J7
J8
J9
J10
J11
Ext Clock
X1
X2
Clock
Select
SW3
SW5
SW4
ADC
Reset
DIT
Reset
To DIT
J3
Introduction
Figure 2 shows a simplified block diagram for the PCM4222EVM circuit functions. The blocks labeled FDAare the OPA1632 fully differential amplifier input circuits (U4 and U5). The blocks labeled DIT are theDIT4192 digital audio interface transmitters (U13 and U14). Two transmitters are required to support AES3Single-Channel, Double Sampling Frequency applications.
Figure 2. Simplified Block Diagram for the PCM4222EVM Evaluation Module
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2 Hardware Configuration
2.1 Electrostatic Discharge Warning
2.2 Absolute Operating Conditions
Hardware Configuration
This section provides information on the PCM4222EVM hardware configuration, including power suppliesand switch settings. Evaluation module handling information and absolute operating conditions are alsoprovided.
CAUTION
Failure to observe proper ESD handling procedures may result in damage toPCM4222EVM components.
Many of the components used in the assembly of the evaluation module are susceptible to damage byelectrostatic discharge (ESD). Customers are advised to observe proper ESD handling procedure whenunpacking and handling the EVM. All handling should be performed at an approved ESD workstation ortest bench while wearing an appropriate grounding device. Failure to observe ESD handling proceduresmay result in damage to EVM components.
CAUTION
Exceeding the absolute operating conditions may result in improper operationor damage to the evaluation module and/or the equipment connected to it.
Table 1 summarizes the critical data points for the PCM4222EVM absolute operating conditions.
Table 1. Absolute Operating Conditions
PARAMETER MIN MAX UNIT
Analog Power Supplies
+15V -0.3 +16.0 VDC-15V +0.3 -16.0 VDCEXT VCC -0.3 +6.0 VDC
Digital Power Supplies
+5V -0.3 +5.5 VDCEXT VDD -0.3 +4.0 VDC
Analog Input Voltage (Measured Differentially at J1 or J2)
Left Channel Analog Input (J1) 4 x VCC V
PP (DIFF)
Right Channel Analog Input (J2) 4 x VCC V
PP (DIFF)
Digital Input Voltage
Audio Serial Port (J6) -0.3 +4.0 VEXT CLOCK (J11) -0.3 +6.5 V
Digital Output Voltage
Connectors J4, J5, and J6 -0.3 VDD + 0.3Connector J7, J9 (terminated with 110 ohms) 4.5 V
PP (DIFF)
Connector J8, J10 (terminated with 75 ohms) 3.6 V
PP
Temperature
Ambient Operating Range 0 +70 °C
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2.3 Power Supplies
VCC +5V +3.3V VDD
+5V DGND
+15V
+15V
-15V
-15V
AGND
EXT
VCC
EXT
VDD
+3.3V
Regulator
+4.0V
Regulator
J12
Digital Power
J3
Analog Power
REG
1
3
2
4
EXT
JMP6
REG
1
3
2
4
EXT
JMP5
U23 U22
Hardware Configuration
The PCM4222EVM includes two terminal blocks for connection of external power supplies. Terminal blockJ3 supports analog power supplies, while terminal block J12 supports digital power supplies. Refer toTable 1 for absolute operating conditions. Table 2 shows the recommended power supply range for thePCM4222EVM.
Table 2. Recommended Power Supply Range
PARAMETER MIN MAX UNIT
Analog Power Supplies (J3)
+15V +6.0 +15.0 VDC-15V -6.0 -15 VDCEXT VCC +3.8 +4.2 VDC
Digital Power Supplies (J12)
+5V +4.5 +5.5 VDCEXT VDD +2.4 +3.6 VDC
The PCM4222EVM requires a minimum of two external dc power supplies for the analog functions. Thetwo power supplies are labeled as +15V and –15V on terminal block J3. The +15V and –15V suppliesshould be regulated and capable of providing a minimum of 200mA of current each.
The PCM4222 requires a +4.0V nominal dc supply for operation of the internal analog circuitry.Designated as VCC, this supply may be derived from the +15V analog power supply using an onboardlinear regulator circuit, comprised of U23 and the associated components. The regulator circuit isprotected in the event that a short-circuit occurs between the +15V supply and ground. The EVM alsosupports an external +4.0V power supply, which may be connected at the EXT VCC terminal of J3.Jumper JMP6 is used to select the onboard regulated supply or an external power source. Figure 3illustrates the jumper options.
Figure 3. Power Supply Jumper Configuration
In addition to the analog supplies, the PCM4222EVM requires at least one digital power supply, connectedat the +5V terminal of J12. This supply is nominally +5V dc, and should be provided by a regulatedvoltage source capable of sourcing a minimum of 200mA. The +3.3V required for the PCM4222 digitalsection and external support logic may be derived from the +5V supply using an onboard linear voltageregulator (U22). Alternatively, an external regulated VDD supply may be connected via the EXT VDDterminal of J12. Refer to Figure 3 for the configuration of jumper JMP5, which is used to select the sourceof the VDD power supply.
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2.4 Analog Inputs
Hardware Configuration
The left and right channel analog input sources for the PCM4222 are provided through connectors J1 andJ2, respectively. The J1 and J2 connectors accommodate both 3-pin balanced XLR and 1/4-inch balancedTRS input connections. Pin 1 for both connector J1 and J2 include a ground lift jumper.
Each analog input is buffered by an input circuit employing the OPA1632 fully differential audio amplifier,selected for its low noise and distortion, and fully-differential input-to-output architecture. The buffer circuitprovides attenuation (nominal gain = 0.482, or –6.34dB) and low-pass antialiasing filter functions. Theprinted circuit board (PCB) layout supports limited board stuff options for experimentation. The full-scaleinput voltage for the input buffer circuit is approximately 4.2V
RMS
(or +14.6845dBu) differential, given anominal VCC supply of +4.0V for the PCM4222 and a source impedance of 40 Ω. Due to the full-scaleinput voltage varying slightly from one PCM4222 device to another, the full-scale input swing should becalibrated for each EVM individually, adjusting the input voltage level until a 0dBFS output level isindicated.
The common-mode bias for each OPA1632 is provided by the corresponding VCOML or VCOMR outputsfrom the PCM4222. The VCOML and VCOMR outputs are buffered by OPA227 low-noise precision opamps, configured as voltage followers. A buffer is required because of the low input impedance of theOPA1632 V
OCM
pin.
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2.5 Master Clock Source
Hardware Configuration
The PCM4222 and the DIT4192 transmitters require a master clock source for operation. The masterclock can be generated using one of two crystal oscillators (designated as X1 or X2), or from an externalclock source connected at the BNC input connector J11. The clock generated by the crystal oscillators orexternal source is used directly by the DIT4192 transmitters. However, this clock must be divided by twowhen used by the PCM4222. A D-type flip-flop (U21) performs this function.
Oscillator X1 is fixed at 22.5792MHz, and may provide the master clock for 44.1kHz and related samplingrates, including 88.2kHz and 176.4kHz. Oscillator X2 is fixed at 24.576MHz, and may provide the masterclock for 48kHz and related sampling rates, including 96kHz and 192kHz.
An external clock source (EXT CLOCK), may be input at BNC connector J11 and is buffered by U19. Thebuffer includes a tri-state output, so that it may be disabled when one of the crystal oscillators is used asthe master clock source. Buffer U19 is always operated from the +3.3V supply generated by voltageregulator U22, and is tolerant to +5V input logic levels. The maximum external master clock frequency is27.648MHz.
Table 3 summarizes the master clock source selection using switch SW6. Note that the user should notenable oscillators X1 and X2 simultaneously, because it will result in output contention and improperoperation. Table 4 lists the master clock rate requirements for commonly used digital audio samplingrates.
Table 3. Master Clock Source Selection
Switch SW6,EXTCLK Switch SW6, X2 Switch SW6, X1 Master Clock Selection
LO LO LO External Clock connected at BNC input J11HI LO HI Oscillator X1, 22.5792MHz ±50ppmHI HI LO Oscillator X2, 24.576MHz ±50ppmHI HI HI Not allowed due to oscillator output contention
Table 4. Master Clock Frequencies for Common Output Sampling and Data Rates
EVM Master Clock Rate PCM4222 MCKI Clock RatePCM4222 Output Mode Output Rate (MHz) (MHz)
8kHz 4.096 2.04832kHz 16.384 8.192PCM Normal
44.1kHz 22.5792 11.289648kHz 24.576 12.28888.2kHz 22.5792 11.2896PCM Double Speed
96kHz 24.576 12.288176.4kHz 22.5792 11.2896PCM Quad Speed
192kHz 24.576 12.288DSD, 64x Oversampling 2.8224MHz 22.5792 11.2896DSD, 128x Oversampling 5.6448MHz 22.5792 11.2896Multi-Bit Modulator 6.144MHz 24.576 12.288
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2.6 Manual Reset Operation
2.7 PCM Output Mode Configuration
2.7.1 Sampling Mode
Hardware Configuration
The PCM4222EVM includes two momentary-contact, normally open, push-button switches that are usedfor manual reset functions. Switch SW4 can be used to reset the PCM4222, while switch SW5 can beused to reset the DIT4192 transmitters. In each case, simply press and then release the correspondingpush-button switch to force an external reset for these devices.
The PCM4222 outputs linear encoded PCM data at the audio serial port output, header J6, or via theDIT4192 AES3 transmitters. The PCM data is binary two’s complement, with the most significant bit of thedata transmitted first. The audio data word length may be 24, 20, 18, or 16 bits. Several audio formats aresupported. See section Section 2.7.2 (Audio Serial Port ) of this document and the PCM4222 datasheet fordetails.
The PCMEN input (pin 16) is used to enable and disable the PCM output mode. Table 5 summarizes theoperation of the PCMEN element on switch SW1. When the PCM output is disabled, the DATA (pin 32)output is forced low. If the PCM4222 is set to Master mode, the BCK (pin 33) and LRCK (pin 34) clockoutputs are also forced low when the PCM output is disabled.
Table 5. PCM Output Mode Configuration
Switch SW1, PCMEN PCM Output Mode
LO PCM Output DisabledHI PCM Output Enabled
The PCM output operates in one three sampling modes: Normal, Double Speed, or Quad Speed. Normalmode supports 128x oversampling with output sampling rates up to 54kHz. Double Speed mode supports64x oversampling with output sampling rates from 54kHz to 108kHz. Quad Speed mode supports 32xoversampling with output sampling rates from 108kHz to 216kHz.
The sampling mode is determined by the state of the FS0 and FS1 inputs (pins 19 and 20, respectively).FS0 and FS1 are configured using the like named elements of switch SW1. Table 6 summarizes theavailable settings for FS0 and FS1.
Table 6. PCM Sampling Mode Selection
Switch SW1, FS1 Switch SW1, FS0 PCM Sampling Mode
LO LO NormalLO HI Double SpeedHI LO Quad SpeedHI HI Reserved
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