Texas Instruments PCM4222EVM User manual

User's GuideSBAU124 – December 2006
PCM4222EVM User's Guide
This document serves as a reference for the PCM4222EVM evaluation module. Whenused in conjunction with commonly available audio test equipment, the PCM4222EVMprovides a complete environment for evaluating the functionality and performance ofthe PCM4222 integrated circuit. Indirectly, the PCM4222EVM serves as an evaluationplatform for the PCM4220 integrated circuit; the PCM4220 is a subset derivative of thePCM4222 device.
This document includes information regarding absolute operating conditions,power-supply requirements, and hardware configuration for the evaluation module. Theelectrical schematics and bill of materials are also included for reference purposes.Throughout this document, the acronym EVM and the phrase evaluation module aresynonymous with the PCM4222EVM.
Contents1 Introduction .......................................................................................... 32 Hardware Configuration ............................................................................ 63 Hardware Reference .............................................................................. 16
List of Figures
1 PCM4222 Functional Block Diagram ............................................................ 32 Simplified Block Diagram for the PCM4222EVM Evaluation Module ........................ 53 Power Supply Jumper Configuration ............................................................. 74 PCM4222EVM Schematics, Page 1 of 2 ...................................................... 175 PCM4222EVM Schematics, Page 2 of 2 ...................................................... 18
List of Tables
1 Absolute Operating Conditions ................................................................... 62 Recommended Power Supply Range............................................................ 73 Master Clock Source Selection ................................................................... 94 Master Clock Frequencies for Common Output Sampling and Data Rates ................ 95 PCM Output Mode Configuration ............................................................... 106 PCM Sampling Mode Selection ................................................................. 107 Audio Serial Port Header Configuration ........................................................ 118 Audio Serial Port Slave/Master Mode Selection .............................................. 119 Audio Serial Port Data Format Selection ...................................................... 1110 TDM Sub-frame Assignment .................................................................... 1211 PCM Output Word Length Selection ........................................................... 1212 Digital Decimation Filter Configuration ......................................................... 1213 Digital High-Pass Filter Switch Operation ...................................................... 1314 DIT4192 Serial Data and Clock Enable Operation ........................................... 1315 DIT4192 Master Clock Divider Configuration .................................................. 1316 DIT4192 Data Format Selection ................................................................ 1417 DIT4192 Transmission Mode Configuration ................................................... 1418 DSD Data Port Header Pin Configuration ..................................................... 15
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19 DSD Output Mode Configuration ................................................................ 1520 DSD Output Rate Selection ...................................................................... 1521 Modulator Data Port Header Pin Configuration ............................................... 1622 Multi-Bit Modulator (MBM) Output Mode Configuration ...................................... 1623 Bill of Materials .................................................................................... 19
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1 Introduction
Reference
Multi-Bit
Delta-Sigma
Multi-Bit
Delta-Sigma
Digital
Filters
Audio
Serial
Port
DSD
Engine
Reset
Logic
Control
and
Status
Master Clock
and Timing
VINL+
VCOML
REFGNDL
VREFL
S/M
FMT0
FMT1
OWL0
OWL1
SUB0 (WCK0)
SUB1 (MCK0)
PCMEN
FS0 (MOD3)
FS1 (MOD4)
OVFL
OVFR
MODEN
DSDEN (MOD6)
DSDCLK
DSDL
DSDR
DSDMODE
VCC1
VCC2
AGND
AGND
AGND
AGND
AGND
AGND
DGND
DGND
DGND
VDD
RST
LRCK
BCK
DATA
DF (MOD5)
HPFDR (MOD1)
HPFDL (MOD2)
VREFR
MCKI
REFGNDR
VCOMR
VINL-
VINR+
VINR-
Introduction
The PCM4222EVM evaluation module from Texas Instruments provides a convenient platform for testingthe PCM4222 , a high-performance, stereo audio analog-to-digital (A/D) converter integrated circuit.Figure 1 shows a block diagram of the PCM4222 device. Refer to the PCM4222 product datasheet foradditional information and details regarding this product. The PCM4222EVM evaluation module includesanalog input and digital output circuitry with common audio connectors, providing a direct interface toaudio test systems for measurement and evaluation.
Figure 1. PCM4222 Functional Block Diagram
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Introduction
The primary features of the PCM4222EVM include:•Simple configuration using switches and power-supply jumpers.•Two differential input buffer/filter circuits employing the Texas Instruments OPA1632 fully differentialamplifer integrated circuit.•Two Texas Instruments DIT4192 digital audio interface transmitters, providing AES3-encoded outputdata. Transformer coupled 110 Ωbalanced and 75 Ωunbalanced outputs are provided. Single-Channel,Double Sampling Frequency operation is supported.•A buffered audio serial port header supports connection to external hardware or test equipmentsupporting Philips' I
2
S™, Left Justified, or Time Division Multiplexed (TDM) audio interface formats forPCM output data.•A buffered data port header provides one-bit Direct Stream Digital (DSD) output data and theassociated bit clock for the DSD output.•A buffered modulator output port header provides access to the PCM4222 6-bit modulator data outputsand clocks.•Support for onboard or external clock generation. Two onboard crystal oscillators provide support forcommon audio sampling rates, including 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, and 192kHz.•Light emitting diode (LED) overflow indicators for the left and right audio channels.•Minimum power-supply requirements: ±6V to ±15V for the analog section, and +5V for the digitalsection.
•The PCM4222 analog supply may be generated from an onboard +4.0 linear voltage regulator, or anexternal regulated dc power source.•A +3.3V supply, used to power the majority of the digital circuitry and the PCM4222 digital section,may be generated from the +5.0V digital supply using an onboard linear voltage regulator.Alternatively, an external regulated dc power source may be selected, supporting digital supplyvoltages as low as +2.4V.
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S/M
FDA
FDA
DIT
DIT
Analog
Power
Audio
Serial
Port
Digital
Power
DSD
Data
Port
Modulator
Output
Port
J6
J5
J4
J12
J1
Left Cha lnne
Analog I tnpu
J2
Right Channel
Analog I tnpu
U1
PCM4222 FP B
SW6
SW1
and
SW2
AES3
Out #1
AES3
Out #2
J7
J8
J9
J10
J11
Ext Clock
X1
X2
Clock
Select
SW3
SW5
SW4
ADC
Reset
DIT
Reset
To DIT
J3
Introduction
Figure 2 shows a simplified block diagram for the PCM4222EVM circuit functions. The blocks labeled FDAare the OPA1632 fully differential amplifier input circuits (U4 and U5). The blocks labeled DIT are theDIT4192 digital audio interface transmitters (U13 and U14). Two transmitters are required to support AES3Single-Channel, Double Sampling Frequency applications.
Figure 2. Simplified Block Diagram for the PCM4222EVM Evaluation Module
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2 Hardware Configuration
2.1 Electrostatic Discharge Warning
2.2 Absolute Operating Conditions
Hardware Configuration
This section provides information on the PCM4222EVM hardware configuration, including power suppliesand switch settings. Evaluation module handling information and absolute operating conditions are alsoprovided.
CAUTION
Failure to observe proper ESD handling procedures may result in damage toPCM4222EVM components.
Many of the components used in the assembly of the evaluation module are susceptible to damage byelectrostatic discharge (ESD). Customers are advised to observe proper ESD handling procedure whenunpacking and handling the EVM. All handling should be performed at an approved ESD workstation ortest bench while wearing an appropriate grounding device. Failure to observe ESD handling proceduresmay result in damage to EVM components.
CAUTION
Exceeding the absolute operating conditions may result in improper operationor damage to the evaluation module and/or the equipment connected to it.
Table 1 summarizes the critical data points for the PCM4222EVM absolute operating conditions.
Table 1. Absolute Operating Conditions
PARAMETER MIN MAX UNIT
Analog Power Supplies
+15V -0.3 +16.0 VDC-15V +0.3 -16.0 VDCEXT VCC -0.3 +6.0 VDC
Digital Power Supplies
+5V -0.3 +5.5 VDCEXT VDD -0.3 +4.0 VDC
Analog Input Voltage (Measured Differentially at J1 or J2)
Left Channel Analog Input (J1) 4 x VCC V
PP (DIFF)
Right Channel Analog Input (J2) 4 x VCC V
PP (DIFF)
Digital Input Voltage
Audio Serial Port (J6) -0.3 +4.0 VEXT CLOCK (J11) -0.3 +6.5 V
Digital Output Voltage
Connectors J4, J5, and J6 -0.3 VDD + 0.3Connector J7, J9 (terminated with 110 ohms) 4.5 V
PP (DIFF)
Connector J8, J10 (terminated with 75 ohms) 3.6 V
PP
Temperature
Ambient Operating Range 0 +70 °C
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2.3 Power Supplies
VCC +5V +3.3V VDD
+5V DGND
+15V
+15V
-15V
-15V
AGND
EXT
VCC
EXT
VDD
+3.3V
Regulator
+4.0V
Regulator
J12
Digital Power
J3
Analog Power
REG
1
3
2
4
EXT
JMP6
REG
1
3
2
4
EXT
JMP5
U23 U22
Hardware Configuration
The PCM4222EVM includes two terminal blocks for connection of external power supplies. Terminal blockJ3 supports analog power supplies, while terminal block J12 supports digital power supplies. Refer toTable 1 for absolute operating conditions. Table 2 shows the recommended power supply range for thePCM4222EVM.
Table 2. Recommended Power Supply Range
PARAMETER MIN MAX UNIT
Analog Power Supplies (J3)
+15V +6.0 +15.0 VDC-15V -6.0 -15 VDCEXT VCC +3.8 +4.2 VDC
Digital Power Supplies (J12)
+5V +4.5 +5.5 VDCEXT VDD +2.4 +3.6 VDC
The PCM4222EVM requires a minimum of two external dc power supplies for the analog functions. Thetwo power supplies are labeled as +15V and –15V on terminal block J3. The +15V and –15V suppliesshould be regulated and capable of providing a minimum of 200mA of current each.
The PCM4222 requires a +4.0V nominal dc supply for operation of the internal analog circuitry.Designated as VCC, this supply may be derived from the +15V analog power supply using an onboardlinear regulator circuit, comprised of U23 and the associated components. The regulator circuit isprotected in the event that a short-circuit occurs between the +15V supply and ground. The EVM alsosupports an external +4.0V power supply, which may be connected at the EXT VCC terminal of J3.Jumper JMP6 is used to select the onboard regulated supply or an external power source. Figure 3illustrates the jumper options.
Figure 3. Power Supply Jumper Configuration
In addition to the analog supplies, the PCM4222EVM requires at least one digital power supply, connectedat the +5V terminal of J12. This supply is nominally +5V dc, and should be provided by a regulatedvoltage source capable of sourcing a minimum of 200mA. The +3.3V required for the PCM4222 digitalsection and external support logic may be derived from the +5V supply using an onboard linear voltageregulator (U22). Alternatively, an external regulated VDD supply may be connected via the EXT VDDterminal of J12. Refer to Figure 3 for the configuration of jumper JMP5, which is used to select the sourceof the VDD power supply.
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2.4 Analog Inputs
Hardware Configuration
The left and right channel analog input sources for the PCM4222 are provided through connectors J1 andJ2, respectively. The J1 and J2 connectors accommodate both 3-pin balanced XLR and 1/4-inch balancedTRS input connections. Pin 1 for both connector J1 and J2 include a ground lift jumper.
Each analog input is buffered by an input circuit employing the OPA1632 fully differential audio amplifier,selected for its low noise and distortion, and fully-differential input-to-output architecture. The buffer circuitprovides attenuation (nominal gain = 0.482, or –6.34dB) and low-pass antialiasing filter functions. Theprinted circuit board (PCB) layout supports limited board stuff options for experimentation. The full-scaleinput voltage for the input buffer circuit is approximately 4.2V
RMS
(or +14.6845dBu) differential, given anominal VCC supply of +4.0V for the PCM4222 and a source impedance of 40 Ω. Due to the full-scaleinput voltage varying slightly from one PCM4222 device to another, the full-scale input swing should becalibrated for each EVM individually, adjusting the input voltage level until a 0dBFS output level isindicated.
The common-mode bias for each OPA1632 is provided by the corresponding VCOML or VCOMR outputsfrom the PCM4222. The VCOML and VCOMR outputs are buffered by OPA227 low-noise precision opamps, configured as voltage followers. A buffer is required because of the low input impedance of theOPA1632 V
OCM
pin.
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2.5 Master Clock Source
Hardware Configuration
The PCM4222 and the DIT4192 transmitters require a master clock source for operation. The masterclock can be generated using one of two crystal oscillators (designated as X1 or X2), or from an externalclock source connected at the BNC input connector J11. The clock generated by the crystal oscillators orexternal source is used directly by the DIT4192 transmitters. However, this clock must be divided by twowhen used by the PCM4222. A D-type flip-flop (U21) performs this function.
Oscillator X1 is fixed at 22.5792MHz, and may provide the master clock for 44.1kHz and related samplingrates, including 88.2kHz and 176.4kHz. Oscillator X2 is fixed at 24.576MHz, and may provide the masterclock for 48kHz and related sampling rates, including 96kHz and 192kHz.
An external clock source (EXT CLOCK), may be input at BNC connector J11 and is buffered by U19. Thebuffer includes a tri-state output, so that it may be disabled when one of the crystal oscillators is used asthe master clock source. Buffer U19 is always operated from the +3.3V supply generated by voltageregulator U22, and is tolerant to +5V input logic levels. The maximum external master clock frequency is27.648MHz.
Table 3 summarizes the master clock source selection using switch SW6. Note that the user should notenable oscillators X1 and X2 simultaneously, because it will result in output contention and improperoperation. Table 4 lists the master clock rate requirements for commonly used digital audio samplingrates.
Table 3. Master Clock Source Selection
Switch SW6,EXTCLK Switch SW6, X2 Switch SW6, X1 Master Clock Selection
LO LO LO External Clock connected at BNC input J11HI LO HI Oscillator X1, 22.5792MHz ±50ppmHI HI LO Oscillator X2, 24.576MHz ±50ppmHI HI HI Not allowed due to oscillator output contention
Table 4. Master Clock Frequencies for Common Output Sampling and Data Rates
EVM Master Clock Rate PCM4222 MCKI Clock RatePCM4222 Output Mode Output Rate (MHz) (MHz)
8kHz 4.096 2.04832kHz 16.384 8.192PCM Normal
44.1kHz 22.5792 11.289648kHz 24.576 12.28888.2kHz 22.5792 11.2896PCM Double Speed
96kHz 24.576 12.288176.4kHz 22.5792 11.2896PCM Quad Speed
192kHz 24.576 12.288DSD, 64x Oversampling 2.8224MHz 22.5792 11.2896DSD, 128x Oversampling 5.6448MHz 22.5792 11.2896Multi-Bit Modulator 6.144MHz 24.576 12.288
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2.6 Manual Reset Operation
2.7 PCM Output Mode Configuration
2.7.1 Sampling Mode
Hardware Configuration
The PCM4222EVM includes two momentary-contact, normally open, push-button switches that are usedfor manual reset functions. Switch SW4 can be used to reset the PCM4222, while switch SW5 can beused to reset the DIT4192 transmitters. In each case, simply press and then release the correspondingpush-button switch to force an external reset for these devices.
The PCM4222 outputs linear encoded PCM data at the audio serial port output, header J6, or via theDIT4192 AES3 transmitters. The PCM data is binary two’s complement, with the most significant bit of thedata transmitted first. The audio data word length may be 24, 20, 18, or 16 bits. Several audio formats aresupported. See section Section 2.7.2 (Audio Serial Port ) of this document and the PCM4222 datasheet fordetails.
The PCMEN input (pin 16) is used to enable and disable the PCM output mode. Table 5 summarizes theoperation of the PCMEN element on switch SW1. When the PCM output is disabled, the DATA (pin 32)output is forced low. If the PCM4222 is set to Master mode, the BCK (pin 33) and LRCK (pin 34) clockoutputs are also forced low when the PCM output is disabled.
Table 5. PCM Output Mode Configuration
Switch SW1, PCMEN PCM Output Mode
LO PCM Output DisabledHI PCM Output Enabled
The PCM output operates in one three sampling modes: Normal, Double Speed, or Quad Speed. Normalmode supports 128x oversampling with output sampling rates up to 54kHz. Double Speed mode supports64x oversampling with output sampling rates from 54kHz to 108kHz. Quad Speed mode supports 32xoversampling with output sampling rates from 108kHz to 216kHz.
The sampling mode is determined by the state of the FS0 and FS1 inputs (pins 19 and 20, respectively).FS0 and FS1 are configured using the like named elements of switch SW1. Table 6 summarizes theavailable settings for FS0 and FS1.
Table 6. PCM Sampling Mode Selection
Switch SW1, FS1 Switch SW1, FS0 PCM Sampling Mode
LO LO NormalLO HI Double SpeedHI LO Quad SpeedHI HI Reserved
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2.7.2 Audio Serial Port
Hardware Configuration
For PCM mode, the audio data may be output via the audio serial port, which is buffered and routed toheader J6. The audio serial port header pin configuration is shown in Table 7 . The BCK and LRCK clocksmay be outputs or inputs, depending upon the Master or Slave mode configuration of the port
Table 7. Audio Serial Port Header Configuration
Header J6 Pin Number Audio Serial Port Signal Name, Description
1 SCKO, System Clock Output (same as PCM4222 MCKI clock)3 BCK, Audio Data Bit Clock Input or Output5 LRCK, Audio Left/Right Word Clock Input or Output7 DATA, PCM Audio Data Output2,4,6,8,9,10 Ground
In Master mode, the BCK and LRCK clocks are output pins, and are derived from the PCM4222 MCKIclock input (pin 35). The BCK clock rate depends on the audio data format selection. The LRCK clock rateis always equal to the output sampling rate. In Slave mode, the BCK and LRCK clocks are input pins,sourced from an external audio serial port master, such as a digital signal processor serial port, a serialtiming generator, or a programmable logic device. Once again, the LRCK clock rate is always equal to thedesired output sampling rate. The BCK clock rate depends on the audio data format selected. Refer to thePCM4222 datasheet for audio serial port operational details.
The Slave/Master mode operation is determined by the state of the S/ M input (pin 39), which is controlledvia the S/ M element on switch SW3. Table 8 summarizes the operation of the S/ M switch.
Table 8. Audio Serial Port Slave/Master Mode Selection
Switch SW3, S/ M Slave or Master Mode
LO MasterHI Slave
The audio data format is selected using the FMT0 and FMT1 inputs (pins 44 and 43, respectively), whichare controlled by the FMT0 and FMT1 elements on switch SW3. Table 9 summarizes the operation for theFMT0 and FMT1 switches.
Table 9. Audio Serial Port Data Format Selection
Switch SW3, FMT1 Switch SW3, FMT0 Audio Data Format
LO LO Left JustifiedLO HI I
2
SHI LO TDMHI HI TDM with One BCK Period Delay
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2.7.3 Digital Decimation Filter
Hardware Configuration
When selecting a TDM data format, it is necessary to select a sub-frame assignment for the PCM4222 sothat the device is set to transmit data during the appropriate time slots in the TDM frame. When thePCM4222 is not transmitting, the DATA output (pin 32) is forced to a high impedance state so that anotherPCM4222 device may transmit on the TDM data bus. The sub-frame assignment is selected using theSUB0 and SUB1 inputs (pins 26 and 25, respectively). These inputs are controlled using the SUB0 andSUB1 elements on switch SW2. Table 10 summarizes the operation for the SUB0 and SUB1 switches.
Table 10. TDM Sub-frame Assignment
Switch SW2, SUB1 Switch SW2, SUB0 Sub-Frame Assignment
LO LO Sub-Frame 0LO HI Sub-Frame 1HI LO Sub-Frame 2HI HI Sub-Frame 3
Typically, the PCM4222 will be configured to output 24-bit PCM data. However, the PCM4222 supportsdata word length reduction using Triangular PDF dithering. This architecture allows the device to output20, 18, or 16 bits of audio data when needed. The output word length is determined by the OWL0 andOWL1 inputs (pins 42 and 41, respectively). These pins are controlled by the OWL0 and OWL1 elementswitch SW3. Table 11 summarizes the operation of the OWL0 and OWL1 switches.
Table 11. PCM Output Word Length Selection
Switch SW3, OWL1 Switch SW3, OWL0 Output Data Word Length
LO LO 24 bitsLO HI 18 bitsHI LO 20 bitsHI HI 16 bits
The PCM4222 includes a linear phase digital decimation filter that is used to downsample the delta-sigmamodulator output and provide low-pass antialiasing filtering. The decimation filter includes two selectablefrequency responses: Classic and Low Group Delay. Refer to the PCM4222 datasheet for plots andspecifications related to each filter response. The DF input (pin 21) is used to select the desired frequencyresponse. This input is controlled using the DF element on switch SW1. Table 12 summarizes theoperation of the DF switch.
Table 12. Digital Decimation Filter Configuration
Switch SW1, DF Digital Decimation Filter Response
LO ClassicHI Low Group Delay
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2.7.4 Digital High-Pass Filter
2.7.5 Overflow Output Indicators
2.7.6 AES3 Transmitter Operation
Hardware Configuration
The PCM4222 includes digital high-pass filtering that removes the dc component from the output signal.The right and left channel filters can be enabled and disabled individually, using the HPFDR (pin 17) andHPFDL (pin 18) inputs, respectively. These inputs are controlled via the HPFDR and HPFDL elements onswitch SW1. Table 13 summarizes the operation for these switches.
Table 13. Digital High-Pass Filter Switch Operation
Switch SW1, HPFDR or HPFDL Digital High-Pass Filter Function
LO EnabledHI Disabled
The PCM4222 includes two active-high overflow indicators, one each for the left and right channels. Theoverflow indicators are provided at the OVFL (pin 37) and OVFR (pin 38) outputs. These outputs arebuffered by U17 and U18. The buffers drive light emitting diodes LED1 and LED2 on the EVM, providingvisual overflow indication for the left and right channels, respectively.
The EVM includes two Texas Instruments DIT4192 digital audio interface transmitters, U13 and U14. Thetransmitters accept either Left Justified or I
2
S formatted PCM output data from the PCM4222 and thenencode it into an AES3 data stream, which is output at connectors J7 through J10. A tri-state buffer (U11)is used to enable/disable the clock and data flow from the PCM4222 to the DIT4192 devices. The DITswitch on SW3 is used to enable or disable the buffer. Table 14 summarizes the DIT switch settings.
Table 14. DIT4192 Serial Data and Clock Enable Operation
Switch SW3, DIT DIT4192 Input Data/Clock Enable
LO Enabled. Data and clocks flow from the PCM4222 to U13 and U14.Disabled. The tri-state buffer outputs are high impedance, with noHI
clocks or data supplied to U13 and U14.
The DIT4192 includes an on-chip master clock divider, which is used to generate the output frame rateclock for the AES3-encoded data. For PCM data, the output frame rate is normally the same as thePCM4222 output sampling rate. The exception is for Single-Channel, Double Sampling Frequencytransmission, when the DIT4192 Mono mode operation is invoked (this topic is discussed later in thissection).
The DITCLK0 and DITCLK1 elements on switch SW3 determine the master clock divider settings for thetransmitters. Table 15 summarizes the operation for the DITCLK0 and DITCLK1 switches, and indicatesthe selections corresponding to the three sampling modes for the PCM4222.
Table 15. DIT4192 Master Clock Divider Configuration
Switch SW3, DITCLK1 Switch SW3, DITCLK0 DIT4192 Master Clock Divider
LO LO Divide by 128 (PCM4222 Quad Speed mode)LO HI Divide by 256 (PCM4222 Dual Speed mode)HI LO Divide by 384 (Not Used)HI HI Divide by 512 (PCM4222 Normal mode)
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Hardware Configuration
The DIT4192 input serial port supports Left Justified and I
2
S formatted PCM data from the PCM4222audio serial port. The TDM data formats are not supported by the DIT4192 input serial port. The DITFMTelement on switch SW3 is used to select the proper data format for the DIT4192, and must match the dataformat that is selected using the FMT0 and FMT1 elements on switch SW3. Table 16 summarizes theoperation for and relationship between the DIT4192 and PCM4222 data format switches.
Table 16. DIT4192 Data Format Selection
Switch SW3, FMT1 Switch SW3, FMT0 Switch SW3, DITFMT Audio Data Format
LO LO LO Left JustifiedLO HI HI I
2
SHI X X TDM formats are not supported
Although one DIT4192 transmitter supports transmission of two-channels of PCM audio data atsampling/frame rates up to and including 216kHz, it is sometimes desirable to use two DIT4192 devices,each carrying data for only a single channel (left or right, respectively) at a frame rate equal to one-half thePCM4222 output sampling rate. This is referred to as Single-Channel, Double Sampling Frequencytransmission in the AES3-2003 standard. The DIT4192 Mono mode is used to implement this form oftransmission.
Mono mode is enabled or disabled using the MONO input (pin 21) of the DIT4192 transmitters. TheDITMONO element on switch SW3 is used to control the MONO pin. Table 17 demonstrates the operationof the DITMONO switch.
Table 17. DIT4192 Transmission Mode Configuration
Switch SW3, DITMONO DIT4192 Transmission Mode
LO Two-channelHI Single-Channel Double Sampling Frequency
The MDAT input (pin 20) of the DIT4192 transmitters is used to select left or right channel for transmissionin Mono mode. The MDAT pin of transmitter U13 is connected to ground, selecting the left input channel.The MDAT pin of transmitter U14 is connected to VDD, selecting the right input channel. In Mono mode,the left channel is transmitted from AES3 Output #1 (connectors J7 and J8), while the right channel istransmitted on AES3 Output #2 (connectors J9 and J10).
When Mono mode is disabled, both the left and right channels are output on both AES3 Output #1 and #2.This allows for simultaneous balanced and unbalanced transmission of the AES3-encoded output data.
Mono Mode Example: Assume that you are transmitting 192kHz two-channel data using the AES3transmitters, with a 24.576MHz master clock and the clock dividers set to divide by 128. By simplyenabling Mono mode (setting the DITMONO switch to HI), the transmission converts to Single-Channel,Double Sampling Frequency mode with an output frame rate equal to 96kHz. There is no need to changethe master clock divider or frequency, because the DIT4192 manages the change in output frame rateautomatically.
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2.8 DSD Output Mode Configuration
Hardware Configuration
The PCM4222 supports a one-bit Direct Stream Digital (DSD) data output, which operates at either 64x or128x the base PCM output sampling rate. The PCM4222 allows both the DSD and PCM output modes tobe enabled simultaneously. The DSD data for the left and right channels and the associated bit clock areoutput at the DSD data port, or header J5. Table 18 lists the pin configuration for header J5.
Table 18. DSD Data Port Header Pin Configuration
Header J5 Pin Number DSD Data Port Signal Name, Description
1 DSDCLK, DSD Bit Clock Output3 DSDL, One-bit DSD Data Output for the Left Channel5 DSDR, One-bit DSD Data Output for the Right Channel2,4,6,7,8,9,10 Ground
The DSD output mode is enabled or disabled using the DSDEN input (pin 22). This input is controlled viathe DSDEN element on switch SW1. Table 19 summarizes the operation of this switch. When the DSDoutput is disabled, DSDCLK (pin 27), DSDL (pin 28), and DSDR (pin 29) are forced low.
Table 19. DSD Output Mode Configuration
Switch SW1, DSDEN DSD Output Mode
LO DisabledHI Enabled
The DSD output data rate may be set to 64x or 128x the base PCM rate (typically 44.1kHz). The outputrate is selected via the DSDMODE input (pin 24). This input is controlled via the DSDMODE element onswitch SW1. Table 20 summarizes the operation of this switch.
Table 20. DSD Output Rate Selection
Switch SW1, DSDMODE DSD Output Data Rate
LO 64x Oversampled Data with Output Rate = MCKI ÷4HI 128x Oversampled Data with Output Rate = MCKI ÷2
For more information regarding DSD output mode operation, timing, and specifications, see the PCM4222datasheet .
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2.9 Modulator Output Operations
3 Hardware Reference
Hardware Reference
The PCM4222 supports a multi-bit modulator (MBM) output mode, where the 6-bit data for the left andright channels are output directly from the delta-sigma modulators. The MBM output data are buffered androuted to the modulator data port, or header J4. Table 21 lists the pin configuration for header J4.
Table 21. Modulator Data Port Header Pin Configuration
Header J4 Pin Name Modulator Data Port Signal Name, Description
1 MOD1, Modulator Data Output 1 (LSB)3 MOD2, Modulator Data Output 25 MOD3, Modulator Data Output 37 MOD4, Modulator Data Output 49 MOD5, Modulator Data Output 511 MOD6, Modulator Data Output 6 (MSB)13 MCKO, Modulator Data Clock Output (Rate = MCKI)15 WCKO, Modulator Word Clock Output (Rate = MCKI ÷2)2,4,6,8,10,12,14,16,17,18,19,20 Ground
The MBM output mode is enabled or disabled using the MODEN input (pin 23). This input is controlled viathe MODEN element on switch SW1. Table 22 summarizes the operation of this switch. When MBM modeis enabled, the PCM and DSD output modes are disabled, because some of the pins used for thesemodes are remapped as modulator data and clock outputs. The PCMEN input (pin 16) must be set to theLO position when the MBM output is enabled. When MBM mode is disabled, all data and clock outputsassociated with the interface are driven low (assumes PCM and DSD modes are also disabled).
Table 22. Multi-Bit Modulator (MBM) Output Mode Configuration
Switch SW1, MODEN Switch SW1, PCMEN Switch SW1, DSDEN MBM Output Mode
LO X X DisabledHI LO X Enabled
Referring to the electrical schematic in Figure 4 , when MODEN is set to a LO state, the outputs of tri-statebuffer U6 are enabled, allowing the elements of switch SW1 and SW2 that are related to the PCM andDSD output modes to control the configuration of the PCM4222. When MODEN is HI, the outputs of bufferU6 are disabled and set to a high-impedance state. In addition, when MODEN is HI, tri-state buffer U7 isenabled, allowing the modulator output data and clocks to be routed to the modulator data port (headerJ4).
For more information regarding Multi-Bit Modulator output mode operation, timing, and specifications, seethe PCM4222 datasheet .
This section provides the electrical schematics and the Bill of Materials for the PCM4222EVM evaluationboard. The components shown in the schematic are listed in Table 23 , the Bill of Materials, for reference.
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3.1 Electrical Schematics
R T S 2 3 1 G
J2
RIGHT CH. ANALOG IN
R T S 2 3 1 G
J1
LEFT CH. ANALOG IN
R5
0
R11
560
R6
0
R12
560
R18
270
C21 0.1uF
R17
270
C7
1nF
LED1
C54
NI
LED2
8
2
1
36
4 5
VOCM
7
+
_
+
_
EN U4
OPA1632DGN
R22
40.2
R21
40.2
12
JMP1
R7
0
R8
0
C62
2.7nF
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
B1 18 B2 17 B3 16 B4 15 B5 14 B6 13 B7 12 B8 11
GND
10
DIR
1VCC 20
OE 19
U7 SN74ALVC245PW
A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9
B1
18
B2
17
B3
16
B4
15
B5
14
B6
13
B7
12
B8
11
GND 10
DIR 1
VCC
20
OE
19
U6 SN74ALVC245PW
C8
1nF
RN1
10K
C55
NI
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
SW1
1 2
JMP3
C51
22uF
R15
270
RN2
10K
-15V
R16
270
TP2
VINL- TP3
VINL+
2 3
6
7
4 1
8
U2
OPA227UA
C31
0.1uF
C30
0.1uF
-15V
+15V
C3
NI
C4
NI
C32
0.1uF
R24
1k
1
4
2
3
SW2
VDD
C12
0.1uF
VDD
2 4 6
1 3 5 78 910 11 12 13 14 15 16 17 18 19 20
J4
MODULATOR OUTPUT PORT
RN3 100 RN4 100
RN5 100 RN6 100
C20
0.1uF
VDD
24
53
U8
SN74LVC1G04DBV
C28
0.1uFVDD
2 4 6
1 3 5 78 910
J5
DSD DATA PORT
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
B1 18 B2 17 B3 16 B4 15 B5 14 B6 13 B7 12 B8 11
GND
10
DIR
1VCC 20
OE 19
U15 SN74ALVC245PW
VDD C29
0.1uF
RN14 100
RN15 100
VDD
C19
0.1uF
C25
0.1uF
C24
0.1uF
+15V C50
22uF
C22 0.1uF
R1
0
R9
560
R2
0
R10
560
C10
0.1uF
C5
1nF
C52
NI
8
2
1
36
4 5
VOCM
7
+
_
+
_EN U5
OPA1632DGN
R20
40.2
R19
40.2
R3
0
R4
0
C61
2.7nF
C6
1nF
C53
NI
1 2
JMP4 C49
22uF
R13
270
-15V
R14
270
TP5
VINR-
TP6
VINR+
2 3
6
7
4 1
8
U3
OPA227UA
C14
0.1uF
C13
0.1uF
-15V
+15V
C1
NI
C2
NI
C15
0.1uF
R23
1K
C26
0.1uF
C18
0.1uF
C17
0.1uF
C16
0.1uF
+15V C48
22uF
C9 0.1uF
12
JMP2
VCC
FMT1 FMT0 S/M
VDD
OWL1 OWL0 LRCK SCKI DATA BCK /RST
24
1
5 3
U17
SN74LVC1G125DBV
24
1
5 3
U18
SN74LVC1G125DBV
VDD C27
0.1uF
VDD C33
0.1uF
VDD
VDD
C63
100
C64
NI
C68
NI
C67
100
C65
100
C69
100
C66
100
HPFDL 18
FS0 19 FS1 20
LRCK 34 SUB1 25
DSDMODE 24
SUB0 26 DSDL 28
DSDCLK 27
HPFDR 17
VINL-
10
VINL+
11
AGND
12
REFGNDL
14
VCOML
13
VDD 31
DATA 32
VREFL
15
DSDR 29
DGND 30
AGND
8
VCC2
9
DGND 40
MODEN 23
DSDEN 22
OWL1 41
VCOMR
48
FMT0 44
AGND
6
FMT1 43
VCC1
4
VINR+
3
AGND
5
REFGNDR
47
AGND
1
VINR-
2
SCKI 35 /RST 36
OVFL 37
OVFR 38
S/M 39
DGND 45
FMODE 21
VREFR
46
BGND
7
PCMEN 16
BCK 33
OWL0 42
U1
PCM4222PFB
TP1
AGND
TP4
AGND
Hardware Reference
The electrical schematics for the PCM4222EVM are shown in Figure 4 and Figure 5 .
Figure 4. PCM4222EVM Schematics, Page 1 of 2
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C37 0.1uF
VDD
SW5
/DITRST
SW4
/ADCRST
C72
0.01uF
R28 10K
C71
0.01uF
R27 10K
/RST
RN12 10K
120 219 318 417 516 615 714 813 912
10 11
SW3
FMT1
OWL0
FMT0
OWL1
S/M
DITCLK1 DITCLK0
/DIT
DITFMT
RN13 10K
VDD
EN 1
OUT 3
VCC
4
GND
2
X1 SM7745HSV-22.5792M
EN 1
OUT 3
VCC
4
GND
2
X2 SM7745HSV-24.576M
C70 0.01uF C73 0.01uF
+3.3V +3.3V
24
1
53
U19
SN74LVC1G125DBV
J11
EXT CLOCK
R25 75
C34 0.1uF
24
1
53
U20
SN74LVC1G125DBV
C36 0.1uF
1CLR 1
1D 2
1CLK 3
1PRE 4
1Q 5 1Q 6
GND 7
2Q
82Q 92PRE
10 2CLK 11 2D
12 2CLR
13 VDD 14
U21
SN74LVC74APW
VDD
A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9
B1
18 B2
17 B3
16 B4 15 B5 14 B6 13 B7 12 B8 11 GND 10
DIR 1
VCC
20
OE
19
U9
SN74ALVC245PW
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
B1 18 B2 17 B3 16 B4 15 B5 14 B6 13 B7 12 B8 11
GND
10
DIR
1VCC 20
OE 19
U11 SN74ALVC245PW
VDD
RN7 100
RN8 100
RN9 100 RN10
100
2 4 6
1 3 5 78 910
J6
AUDIO SERIAL PORT
24
1
53
U10
SN74LVC1G125DBV
C41
0.1uF
C42
0.1uF
S/M
VDD
VDD C43
0.1uF
VDD
/DIT
CSS
1
COPY/C
2
L
3
CLK1
4
CLK0
5
MCLK
6
VIO
7
DGND
8
FMT0
9
FMT1
10
SCLK
11
SYNC
12
SDATA
13
M/S
14
MODE 28
U27
V26
BLS 25
BLSM 24
EMPH 23
AUDIO 22
MONO 21
MDAT 20
VDD 19
TX+ 18
TX- 17
DGND 16
RST 15
U13
DIT4192IPW
CSS
1
COPY/C
2
L
3
CLK1
4
CLK0
5
MCLK
6
VIO
7
DGND
8
FMT0
9
FMT1
10
SCLK
11
SYNC
12
SDATA
13
M/S
14
MODE 28
U27
V26
BLS 25
BLSM 24
EMPH 23
AUDIO 22
MONO 21
MDAT 20
VDD 19
TX+ 18
TX- 17
DGND 16
RST 15
U14
DIT4192IPW
VDD
C79 10uF
C80 10uF
C38 0.1uF
C39 0.1uF
C46 0.1uF
C82 10uF
+5V +5V
C40 0.1uF
R29 110
C47 0.1uF
R30
110
REG
J8
AES3 OUTPUT #175ohms
J10
AES3 OUTPUT #2 75 ohms
LRCK
BCK
SCKI
DATA
C45 0.1uF
VDD
C81 10uF
+3.3V
C35
0.1uF
VDD
C56 NI
R26 75
C75
0.01uF
C76
0.01uF
C74
0.01uF
C78 0.01uF
C77 0.01uF
C89 100uF
C88 100uF
C85
100uF
C86
100uF
C87
100uF
+15V +5V
+3.3V
C83 10uF C84
10uF
12 34
JMP5 EXT
EXT VCC
-15V
1
2
3
4
J12 DIGITAL POWER
1
2
3
4
J3 ANALOG POWER
TP7
+5V VDD
DIT_SYNC
DIT_SCLK
DIT_SDATA
DIT_MCLK
EXT VDD
1A
1
1Y
2
2A
3
2Y
4
3A
5
3Y
6
GND
74Y 8
4A 9
5Y 10
5A 11
6Y 12
6A 13
VCC 14
U16
SN74AHC14PW
18 27 36 45
SW6
DIPSWITCH-4
RN16 10K
+3.3V
1 4
5 6 8 7
PRI
SEC 1 SEC 2
T2
SC939-06
1 4
5 6 8 7
PRI
SEC 1 SEC 2
T1
SC939-06
VIN
3VOUT 2
GND
1
VOUT 4
U22
REG1117-3.3
C90 100pF C91 100pF
2
3
1
G
J7
AES3 OUTPUT #1 110 ohm
s
2
3
1
G
J9
AES3 OUTPUT #2 110 ohm
s
REG
12 34
JMP6 EXT
+15V
VCC
R31 240
R32 200
R33 324
C94 1uF
C92 NI C93
10uF
D2
DL4002
D1 DL4002
+4V
24
1
53
U24
SN74LVC1G125DBV
C95 0.1uF
VDD
VIN
3VOUT 2
GND
1
VOUT 4
U23
LM317M
Hardware Reference
Figure 5. PCM4222EVM Schematics, Page 2 of 2
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3.2 Bill of Materials
Hardware Reference
The Bill of Materials is provided as a cross-reference for the components shown in Figure 4 and Figure 5 .
Table 23. Bill of MaterialsREFERENCEITEM QTY VALUE DESIGNATOR DESCRIPTION VENDOR PART NUMBER
1 NI C1-C4 Optional AC Coupling Capacitor N/A N/A
Chip Capacitor, C0G Ceramic, 100pF2 2 100pF C90, C91 TDK C1608C0G1H101±5%, 50WV, Size = 0603
3 NI C57-C60 Item Removed from Design N/A N/A
Chip Capacitor, PPS Film, 1nF ±2%,
Panasonic ECH-U1H102GX550WV, Size = 0805
4 4 1nF C5-C8 or or or
Chip Capacitor, C0G Ceramic, 1nF
TDK C2012C0G1H102J±5%, 50WV, Size = 0805
Chip Capacitor, PPS Film, 2.7nF ±2%,
Panasonic ECH-U1H272GX550WV, Size = 0805
5 2 2.7nF C61, C62 or or or
Chip Capacitor, C0G Ceramic, 2.7nF
TDK C2012C0G272J±5%, 50WV, Size = 0805
Chip Capacitor, X7R Ceramic, 0.01 µF6 9 0.01 µF C70-C78 TDK C1608X7R1H103K±10%, 50WV, Size = 0603
C9, C10, C12-22,
Chip Capacitor, X7R Ceramic, 0.1 µF7 37 0.1 µF C24-29, C30-C43, TDK C1608X7R1H104K±10%, 50WV, Size = 0603C45-C47, C95
Chip Capacitor, X7R Ceramic, 0.1 µF8 NI C92 TDK C1608X7R1H104K±10%, 50WV, Size = 0603
Chip Capacitor, X7R Ceramic, 1 µF9 1 1 µF C94 TDK C1608X7R1C105K±10%, 16WV, Size = 0603
Chip Capacitor, Solid Tantalum, 10 µF10 6 10 µF C79-C84 Kemet T491A106K010AT±10%, 10WV, Size = A
Chip Capacitor, Low ESR Tantalum,11 1 10 µF C93 Kemet T494B106K016AT10 µF±10%, 16WV, Size = B
Chip Capacitor, Solid Tantalum, 22 µF12 NI 22 µF C48-C51 Kemet T491D226K025AT±10%, 25WV, Size = D
C63, C65-C67, Chip Capacitor, Polymer Tantalum,13 5 100 µF Kemet T520B107M006ATE070C69 100 µF±20%, 6.3WV, Size = B
Chip Capacitor, Polymer Tantalum,14 NI 100 µF C64, C68 Kemet T520B107M006ATE070100 µF±20%, 6.3WV, Size = B
15 NI C11, C23 Item Removed from Design N/A N/A
Capacitor, Alum Electrolytic, SMT,16 5 100 µF C85-C89 Panasonic EEV-FK1E101XP100 µF±20%, 25WV
Rectifier, Passivated, 1A, 100V, SMD Micro Commerical17 2 D1, D2 DL4002-TPMELF Components
18 2 LED1, LED2 LED, SMT, Red Clear, Size = 1206 Lumex SML-LX1206IC-TR
Combo Connector, Female XLR and19 2 J1, J2 Neutrik NCJ6FI-HTRS, Vertical PC Mount
20 2 J3, J12 3.5mm PCB Terminal Block, 4 poles Weidmuller 996770
21 1 J4 Terminal Strip, 20-Pin (10x2) Samtec TSW-110-07-T-D
22 2 J5, J6 Terminal Strip, 10-Pin (5x2) Samtec TSW-105-07-T-D
3-Pin Male XLR Chassis23 2 J7, J9 Neutrik NC3MAH-0Connector,Horizontal PC Mount
24 2 J8, J10 RCA Phono Jack, Black Shell CUI Stack RCJ-041
25 1 J11 Vertical PCB Mount BNC Connector Tyco/AMP 5414305-1
JMP1, JMP2,26 4 Terminal Strip, 2 pin (2x1) Samtec TSW-102-07-T-SJMP3, JMP4
27 2 JMP5, JMP6 Terminal Strip, 4 pin (2x2) Samtec TSW-102-07-T-D
28 8 0 ΩR1-R8 Chip Resistor, 0 ΩShunt, Size = 0805 Panasonic ERJ-6EY0R00V
Chip Resistor, Thick Film, 1%29 4 40.2 ΩR19-R22 Panasonic ERJ-14NF40R2UTolerance, 40.2 Ω, 1/4W, Size = 1210
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Hardware Reference
Table 23. Bill of Materials (continued)REFERENCEITEM QTY VALUE DESIGNATOR DESCRIPTION VENDOR PART NUMBER
Chip Resistor, Thick Film, 1%30 NI 75 ΩR25 Panasonic ERJ-6ENF75R0VTolerance, 75 Ω, 1/10W, Size = 0805
Chip Resistor, Thick Film, 1%31 1 75 ΩR26 Panasonic ERJ-6ENF75R0VTolerance, 75 Ω, 1/10W, Size = 0805
Chip Resistor, Thick Film, 1%32 2 110 ΩR29, R30 Panasonic ERJ-6ENF1100VTolerance, 110 Ω, 1/10W, Size = 0805
Susumu RR1220P-201-B-T5Chip Resistor, Thin Film, 0.1%33 1 200 ΩR32 or orTolerance, 200 Ω, 1/10W, Size = 0805
Digi-Key RR12P200BCT-ND
Susumu RR1220P-241-B-T5Chip Resistor, Thin Film, 0.1%34 1 240 ΩR31 or orTolerance, 240 Ω, 1/10W, Size = 0805
Digi-Key RR12P240BCT-ND
Chip Resistor, Metal Film, 0.1%35 6 270 ΩR13-R18 Panasonic ERA-6YEB271VTolerance, 270 Ω, 1/10W, Size = 0805
Susumu RR1220P-3240-B-M-T5Chip Resistor, Thin Film, 0.1%36 1 324 ΩR33 or orTolerance, 324 Ω, 1/10W, Size = 0805
Digi-Key RR12P324BCT-ND
Chip Resistor, Metal Film, 0.1%37 4 560 R9-R12 Panasonic ERA-6YEB561VTolerance, 560 Ω, 1/10W, Size = 0805
Chip Resistor, Thick Film, 1%38 2 1k R23, R24 Panasonic ERJ-6ENF1001VTolerance, 1k Ω, 1/10W, Size = 0805
Chip Resistor, Thick Film, 1%39 2 10k R27, R28 Panasonic ERJ-6ENF1002VTolerance, 10k Ω, 1/10W, Size = 0805
RN3-RN10, RN14, Thick Film Chip Resistor Array 100 Ω,40 10 100 CTS 742C083101JPRN15 8 Terminal, 4 Resistors
RN1, RN2, RN12, Thick Film Chip Resistor Array 10k Ω,41 5 10k CTS 742C163103JPRN13, RN16 16 Terminal, 8 Resistors
RN11, RN14,42 NI Item Removed from Design N/A N/ARN15
DIP Switch, 10 Element, Half Pitch43 2 SW1, SW3 ITT C&K Switch TDA10H0SB1Surface-Mount, Tape Sealed
DIP Switch, 2 Element, Half Pitch44 1 SW2 ITT C&K Switch TDA02H0SB1Surface-Mount, Tape Sealed
Momentary Tact Switch SMT w/o45 2 SW4, SW5 Omron B3S-1000Ground Terminal
DIP Switch, 4 Element, Half Pitch ITT Cannon46 1 SW6 TDA04H0SB1Surface-Mount, Tape Sealed (formerly C&K)
47 2 T1, T2 Dual Zo Digital Audio Transformer Scientific Conversion SC939-06LF
PCB Test Point, Compact,48 7 TP1-TP7 Keystone Electronics 5006Through-Hole
High-Performance, 24-Bit/216kHz49 1 U1 Texas Instruments PCM4222PFBStereo Audio A/D Converter
Texas Instruments OPA227UAG450 2 U2, U3 Low-Noise Precision Op Amp or orTexas Instruments OPA27GU
51 2 U4, U5 Fully-Differential Audio Amplifier Texas Instruments OPA1632DGNG4
SN74ALVC245PWG4U6, U7, U9, U11, Octal Bus Transceiver w/ Tri-State52 5 Texas Instruments orU15 Output
SN74ALVC245PWRG4
53 1 U8 Single Inverter Texas Instruments SN74LVC1G04DBVRG4
U10, U17-U20,54 6 Single Buffer w/ Tri-State Output Texas Instruments SN74LVC1G125DBVRG4U24
55 NI U12 Item Removed from Design N/A N/A
56 2 U13, U14 Digital Audio Interface Transmitter Texas Instruments DIT4192IPWRG4
SN74AHC14PWG457 1 U16 Hex Schmitt Trigger Inverter Texas Instruments orSN74AHC14PWRG4
Dual Positive Edge Triggered D-Type58 1 U21 Texas Instruments SN74LVC74APWRG4Flip-Flops with Clear and Preset
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