Texas Instruments LM76005QEVM User manual

User’s Guide
LM76005QEVM User’s Guide
1 LM76005QEVM User’s Guide
The Texas Instruments LM76005QEVM evaluation modules (EVM) help designers evaluate the operation and
performance of the LM76005-Q1 wide-input voltage buck regulator. The output voltage for the device offers
configurability from 1-V to 95% of VIN, synchronous rectification, PFM, and forced PWM mode and a 200-kHz to
500-kHz adjustable frequency range with a 400-kHz default frequency. It also offers external frequency
synchronization, power-good (PG) flag, and a precision enable to program undervoltage lockout (UVLO) and
internal compensation. Built-in protection includes current limit, overvoltage and undervoltage protection, and
thermal shutdown. The LM76005QEVM is configured for an output voltage of 3.3 V and a switching frequency of
400 kHz. Refer to the LM76005-Q1 3.5-V to 60-V, 5-A Synchronous Step-Down Voltage Regulator Data Sheet
for additional features, detailed description, and available options.
The EVM contains one DC-DC converter (see Table 1-1).
Table 1-1. Device and Package Configurations
CONVERTER IC PACKAGE
U1 LM76005-Q1 (RNP) WQFN-30
Table of Contents
1 LM76005QEVM User’s Guide.................................................................................................................................................1
2 Setup........................................................................................................................................................................................2
2.1 Input/Output (I/O) Connector Description...........................................................................................................................2
2.2 Voltage Setup.....................................................................................................................................................................3
2.3 Operation........................................................................................................................................................................... 3
3 Schematic................................................................................................................................................................................4
4 Board Layout...........................................................................................................................................................................5
5 Bill of Materials......................................................................................................................................................................11
6 Application Curves............................................................................................................................................................... 12
7 Revision History................................................................................................................................................................... 12
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2 Setup
This section describes the test points and connectors on the EVM and how to properly connect, set up, and use
the LM76005QEVM. Refer to Figure 2-1 for a top view of the EVM and relative placement of the different test
points and connectors.
Figure 2-1. Top View of LM76005QEVM
2.1 Input/Output (I/O) Connector Description
VIN – Terminal on
J1
The power input terminal for the converter
VOUT – Terminal
on J2
The regulated output voltage for the converter
VIN_EMI – Terminal
on J6
Used to supply the input voltage through an on board LC filter (if one is needed for
conducted EMI/EMC measurement). The L1 and CBULK component pads are located on
the bottom side of the EVM. Refer to Figure 3-1 for initial suggestion of component
values. J6 and LC filter are not populated on this EVM.
GND – Terminal on
J1, J2 and J6
The ground reference for the converter
EN – Testpoint Used to enable the converter by supplying a voltage greater than 1.2 V (typ) or just to
monitor the voltage on this pin whenever a resistor divider is in place (for precision enable
applications). The regulator is enabled when VIN > 3.5 V. This threshold can be calculated
by:
RENT
Enable _ Voltage VIH_EN 1 RENB
§ ·
˜ 
¨ ¸
© ¹
(1)
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PG – Testpoint Used to monitor the power-good flag. This flag indicates whether the output voltage has
reached its regulation point. This pin is an open-drain output that requires a pullup resistor
to the appropriate logic voltage (any voltage less than 20 V).
PG_PU – Testpoint The top connection of an optional 100-kΩ pullup resistor that ties directly to the open-
drain PG pin. Supply an appropriate voltage to this test point, or tie it directly to the VOUT
test point to observe the PG flag operation if the output voltage is set less than 20 V.
SYNC – Testpoint The input terminal for an optional external input clock to the converter as well a mode pin
for converter. If used, the external clock frequency must be between 200 kHz and 500
kHz.
2.2 Voltage Setup
Set the input voltage (VIN) range for the converter between the operating voltage range of 3.5 V to 60 V. If a load
is driven, it must be applied to the VOUT terminal and must not exceed the maximum load current of 5 A for
LM76005-Q1.
Note
Please remove R3 and tie BIAS pin to ground if output voltage is set higher than 24 V.
2.3 Operation
For proper operation of the LM76005-Q1, VIN, GND, and VOUT must be properly configured as stated above. In
this configuration, the device starts up when power is applied, and the output voltage of the regulator (VOUT)
comes up to the proper value. The default setting for output voltage of the LM76005-Q1 is 3.3 V. Other output
voltages can be set by replacing the feedback pin resistor dividers R7 and R8; consult the data sheet for proper
selection of these resistor values.
The default frequency for the LM76005QEVM is 400 kHz. If other frequencies are desired within the frequency
range of 200 kHz and 500 kHz, the RT resistor value can be changed. See the LM76005-Q1 3.5-V to 60-V, 5-A
Synchronous Step-Down Voltage Regulator Data Sheet for proper selection of the RT resistor. Change inductor
L2 and total output capacitance for proper control loop operation.
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3 Schematic
Figure 3-1. LM76005QEVM Schematic
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4 Board Layout
Figure 4-1 through Figure 4-5 show the board layout for the LM76005QEVM. The EVM offers resistors,
capacitors, and test points to configure the output voltage and precision enable pin, and set frequency and
external clock synchronization.
The RNP WQFN-30 package offers an exposed thermal pad which must be soldered to the copper landing on
the PCB for optimal thermal performance. The PCB consists of a 4-layer design. There are 2-oz copper planes
on the top and bottom and 1-oz copper mid-layer planes to dissipate heat with an array of thermal vias under the
thermal pad to connect to all four layers.
Test points have been provided for ease of use to connect the power supply and required load, and monitor
critical signals.
Figure 4-1. Top Silkscreen Layer
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Figure 4-2. Top Layer Routing
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Figure 4-3. Mid Layer 1 Ground Plane
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Figure 4-4. Mid Layer 2 Routing
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Figure 4-5. Bottom Layer Routing
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Figure 4-6. Bottom Layer Routing
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