Texas Instruments TPS2410EVM User manual

Using the TPS2410EVM
User's Guide
Literature Number: SLVU181B
October 2006–Revised September 2019

LOAD
GND
GND
One TPS2410 and
N-Channel MOSFET
Replaces One Diode
TPS2410
A2 C2
A1 C1
PS1
PS2
+V1
D1
D2
GND
+V1
+V
TPS2410
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TPS2410 EVM (HPA204)
User's Guide
SLVU181B–October 2006–Revised September 2019
TPS2410 EVM (HPA204)
This user's guide is to facilitate operation of the TPS2410 and TPS2411 evaluation module. It is used by
an engineer or technician, and supplements the TPS2410, TPS2411 data sheets, schematics, and circuit
board labeling. Two variant of EVM exists for two different package options. TPS2410EVM and
TPS2411EVM are used in evaluation of the 14 Pin TSSOP (PW) packaged device and TPS2411EVM-096
can be used to evaluate 14 Pin UQFN (RMS) packaged device. Schematic of both EVM remains the
same, however PCB and BOM files differ due to different package option.
1 Introduction
The TPS2410 controls an N-channel MOSFET to operate in circuit as an ideal diode. The MOSFET
source and drain voltages are monitored by TPS2410 pins A and C. The TPS2410 drives the MOSFET
gate high if VAC exceeds 10 mV, and turns the MOSFET off if VAC falls below a threshold that is both
programmable and dependent on the choice of TPS2410 or TPS2411.
The TPS2410 has a turn-off point of 2.5-mv VAC.
TPS2411 is similar to TPS2410 when RSET is open and has a resistor programmable MOSFET turn-off
point. The TPS2411 can even be set to a slightly negative shutdown allowing for some voltage back
current.
Figure 1 shows the conventional wire-OR of power supplies with diodes. Each diode D1 and D2 is
replaced by a TPS2410 and MOSFET eliminating the voltage and power loss in the diode.
The evaluation module is set up to wire-OR two power supplies for redundant power to a load using two
TPS2410s and MOSFETs. This document contains setup and user information about this evaluation
module to assist with the operation of TPS2410.
Figure 1. Conventional Wire-OR Power Supplies

Channel 1
TPS2410
UV
OV
Glitch
Maker
STATUS
STATUS
Output
FET
Output
FET
Load
PS 2
PS 1
+ 5 V PS
RSET
RSET
FILTER
FILTER
Channel 2
TPS2410
V
Protect
AC
UV
OV
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Reference Figure 2, a block diagram of the TPS2410EVM and TPS2411EVM.
• The 5-V supply is used to power status LEDs. It is jumper selected to power VDD on the TPS2410s
and the glitch circuit if the control voltage is less than 3.0 V.
• The status outputs turn on LEDs to give a visual condition of the system Fault, power good and gate
status are displayed.
• The Glitch maker, discussed in the Test Methods Section applies a 1-Ωload to the input supply for
100 μs. This disruption allows the user to scope test points and observe system recovery.
• The RSET resistor is used to program the turn-off point of the TPS2411.
• The Filter compensates for system noise.
• The UV and OV circuits set permissible limits for input operating voltage.
Figure 2. EVM Block Diagram

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2 MOSFET Configurations
The TPS2410 EVM is supplied with IRL3713 MOSFETS. These MOSFETs can be replaced with user
selected parts if desired as there are alternative MOSFET footprints that accept N-channel parts in
D2PACK, DPACK, and SOIC packages. The schematic is shown in Section 4.
The MOSFETs are configured to operate as singles with only Q6 and Q13 populated as supplied. They
may be configured to operate in parallel on the PS1 channel by populating Q6 and Q5 and shorting drain
to source on Q4. Similarly, for parallel operation on the PS2 channel, populate Q13 and Q12 and short
drain to source on Q11. MOSFETs can be configured back-to-back by populating only Q4 and Q5 on
channel 1, and Q12 and Q11 on channel 2.
In single or parallel configurations, the body diode of the MOSFET limits VAC to 0.7 V. For back to back
MOSFETs, there could be a danger of exceeding the VAC operating maximum 5 V. The VAC protect circuit
is a low powered FET that is turned on when VAC approaches the maximum.
3 LED Indicators
Each channel has LED indicators for fault (FLTB), gate status (STAT), and power good (PG). Table 1
summarizes the indicators. Each indicator is labeled on the circuit board for easy reference.
Table 1. LED Indicators
Indicator Channel 1 Channel 2 LED On
Fault (FLTB) D3 D8 Fault = on
Gate Status (STAT) D2 D7 Bad gate = on
Power Good (PG) D1 D6 Power good = on
3.1 User Circuits
There are two sections of the circuit board with plated through holes for user defined circuits.
3.2 Materials Needed – TI Supplied
• TPS2410 evaluation module
• TPS2410 reference design documentation
• TPS2410 data sheet
3.3 User Supplied
• 2 – power supplies for wire-OR to load, up to 25 A
• 1 – 5-V power supply to supply EVM
• Power supply cables
• Load – active load, power resistors or actual load
• Oscilloscope
• Current probe
• Differential probe

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3.4 Jumper Description
Jumpers J1, J2, J13, J14
VDD can be powered by the input power supply pin A, Jump J2-2, 3 and J14-2, 3. When it is powered by
the load, pin C, jump J2-1, 2 and J14-1, 2. If A and C are less than 3 V, connect the 5 V to VDD, jumper
J1-1 to J2 -2 and J13-1 to J14-2.
J3, J15
Jumpers J3 and J15 connect a pot to the RSET pin when testing the TPS2411. These jumpers are
normally left open when testing the TPS2410.
J4, J17
Jumpers J4 and J17 are open to enable the UV and OV inputs to the TPS2410.
J6
Jumper J6 is on to connect the STAT pins together on both TPS2410 channels. When the STAT pin is
low, the turn off of the channel powering the load is de-sensitized.
J8
Jumper J8 is the gate voltage for the Glitch FET. Jump J8-2, 3 when the PS1 voltage is greater than 5 V.
Jump J8-1, 2 to use the 5-V supply when PS1 is less than 5 V.
J16
Jumper J16-2, 3 connects pin C to the load for single or parallel FETs. Connect J16-1, 2 to protect the pin
A and C inputs when output FETs are configured back-to-back.
3.5 Procedure – Jumper Set-Up
An initial jumper setup is recommended in Table 2. The module has flexibility to operate in other modes.
Change jumpers to operate in other configurations as required after getting started. After the initial setup,
reference the schematic and set jumpers as required for testing. Other J reference designators on the
schematic are simple connectors.
Table 2. Initial Jumper Settings
Jumper Function Selection Comment
J1 5 V to VDD, CH1 Open
J2 A or C to VDD, CH1 Jumper 2 - 3 Connects A
J3 Install to use RSET, CH1 Open
J4 In to disable OV channel 1 Open
J6 In to OR STAT lines Open
J8 5 V or PS1 to gate of PS1 pulse Jumper 2 - 3 Connects PS1
J13 5 V to VDD, CH1 Open
J14 A or C to Vdd, CH2 Jumper 2 - 3 Connects A
J15 Install to use RSET, CH2 Open
J16 Connects the load to CH2 C or FET Jumper 2 - 3 Connects C
J17 In to disable OV Channel 2 Open

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3.6 Power Supply Connection
Connect the power supplies and load to the TPS2410 test card as shown in Table 3. Loading less than 30
A is safe for IRl3713S. The load can be a test load or the actual system load.
Table 3. Power Supply Connection
Connection Supply Terminal
PS1 +V PS1, J12
PS1 PS1, J312 IN1, J5
PS1 GND PS1GND, J10
PS2 +V PS2, J18
PS2 GND PS2GND, J19
5 V 5 V J20-2
5GND GND J20-1
Load + Load, +V J7
Load – GND J11
3.7 OV and UV Setup
Set the OV and UV pots for each input voltage selected and re-adjust these pots when the input voltage
range is changed.
For this example, PS1 and PS2 are 12 V ±20 %. Set PS1 to the undervoltage set point, 9.6 V, and adjust
R13 until TP7 measures 0.6 V, reference Table 4. Set PS1 to the overvoltage set point, 14.4 V, and adjust
R12 until TP10 measures 0.6 V.
Complete this procedure for channel 2. Set the power supply voltages, PS1 and PS2, to the typical input,
12 V.
Table 4. UV and OV Setup
Supply Setting Potentiometer Test Point
PS1-UV R13 TP7
PS1-OV R12 TP10
PS2-UV R32 TP24
PS2-OV R31 TP26
3.8 Test Points
Table 5 lists some common test points for observation. There are more test points shown on the
schematic.
Table 5. Common Test Points
Function TP Channel 1 TP Channel 2
A TP2 TP18
C TP9 –
GATE TP11 TP22
OV INPUT TP10 TP26
UV INPUT TP7 TP24
FAULT TP8 TP25
PG TP4 TP20

RSET
OFF
470.02
R
V 0.00314
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3.9 RSET
RSET is usually used in TPS2411 and sometimes in the TPS2410 to program the MOSFET turn-off point.
The RSET calculation from the data sheet is:
(1)
Calculate the RSET resistor. For the PS1 channel, remove jumper J3 and connect an ohm-meter from J3-
2 to GND. Adjust pot R8 for the calculated resistance value. Install the jumper J3-1, 2. Repeat for the PS2
channel RSET Pot R26 and jumper J15. The component reference designators for each channel is
summarized in Table 6.
Table 6. RESET Resistor Setting
RSET Pot Jumper Measure
R8 J3 J3-2
R26 J15 J15-2
3.10 Test Methods
The EVM has many operating configurations to view the system response. The user can make
modifications to the EVM jumpers and test other set ups.
3.11 Adjust Input Power Supplies
Vary the input voltages to observe system behavior. Jumpers can be set as in Table 2. Turn the power
supplies to the application typical volts; for this paper, we will use 12 V. The load is shared between the
supplies. Both gates will be on and the power supply current meters show output. Decrease one supply
voltage slightly and note the gate on that channel pass FET turn off and the other channel FET gate
increases to keep the FET on to supply the load. Observe the FET gates with a scope. With a voltmeter,
verify VDS for the on channel to be tens of millivolts.
3.12 Glitch Maker
Remove the jumper from J5 to J12 and connect the power supply to J12. This reduces the bulk
capacitance at the PCB power supply input. Set power supplies up for equal or slight differential voltage
so that the PS1 supply is contributing to the load. Press momentary switch S1, labeled PULSE. The switch
closure places a 1-Ωload across the input power supply for 100 μs. Observe the effect of an input power
supply glitch. Scope on the MOSFET gates, load voltage, TPS2410 fault output, STAT and PG.
3.13 Load Change
A dynamic change to the load can be made by switching additional load on or off with an external switch.
Some power load test equipment can be used to dynamically change the load.

GATE2 - 5 V/div
PSI - 100 mV/div
GATE1 - 10 V/div
LOAD - 500 mV/div
GATE1 - 10 V/div
PSI - 1 V/div
GATE2 - 10 V/div
LOAD - 1 V/div
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4 Scope Traces
Figure 3. PSI Shorted, Loaded
Figure 4. PSI Glitched

GATE1 - 10 V/div
FAULT - 5 V/div
STAT - 5 V/div
PG - 5 V/div
PSI - 100 mV/div
GATE2 - 10 V/div
GATE1 - 10 V/div
LOAD - 200 mV/div
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Figure 5. PSI Set to Standby
Figure 6. PSI Set to Standby

STAT - 5 V/div
FAULT - 5 V/div
PG - 5 V/div
GATE1 - 10 V/div
GATE1 - 10 V/div
STAT - 5 V/div
FAULT - 5 V/div
PG - 5 V/div
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Figure 7. PS2 On - PSI Turned On From Standby
Figure 8. PSI Turned On From Standby

+
+
5 Volts
+
+
+
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5 Schematics
Schematics of TPS2410EVM and TPS2411EVM is shown in Figure 9,Figure 10 and Figure 11.
Schematics of TPS2411EVM-096 is shown in Figure 12,Figure 13 and Figure 14.
Figure 9.

+
+
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Figure 10.

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Figure 11.

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Figure 12. TPS2411EVM-096 Schematic Sheet 1

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Figure 13. TPS2411EVM-096 Schematic Sheet 2

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Figure 14. TPS2411EVM-096 Schematic Sheet 3
6 EVM Assembly Drawings and PCB Layout
Assembly Drawings and PCB Layout for TPS2410EVM and TPS2411EVM are shown in Figure 15 through
Figure 18. Assembly Drawings and PCB Layout for TPS2411EVM-096 are shown in Figure 19 through
Figure 24.

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Figure 15. TPS2410EVM Top Overlay

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Figure 16. TPS2410EVM Internal Layer 1

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Figure 17. TPS2410EVM Internal Layer 2

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Figure 18. TPS2410EVM Bottom Layer