Texas Instruments ADS1 7 EVM-PDK Series User manual

User's Guide
SBAU197–February 2012
ADS1x7xEVM-PDK
ADS1x7xEVM-PDK
This user's guide describes the characteristics, operation, and use of the ADS1x7xEVM-PDK. These
evaluation modules kits (EVM-PDK) are an evaluation system for the ADS1278, a 24-bit, 8 channel,
delta-sigma analog-to-digital converter (ADC), the ADS1178, a 16-bit version of the ADS1278 and the
ADS1274 and ADS1174, which are 4 channel versions of the ADS1278 and ADS1178, respectively. The
EVM-PDK allows evaluation of all aspects of the ADS1x7x devices.
This document includes an EVM QuickStart, hardware and software details, bill of materials, and
schematic.
The following related documents are available through the Texas Instruments web site at
http://www.ti.com.
Table 1. EVM-Compatible Device Data Sheets
Device Literature Number Device Literature Number
ADS1278 SBAS367 OPA1632 SBOS286
ADS1274 SBAS367 SN74LVC2G157 SCES207
ADS1178 SBAS373 TPS73018 SBVS054
ADS1174 SBAS373 TPS65131 SLVS493
REF5025 SBOS410 PCA9535 SCPS129
OPA2350 SBOS099
ADCPro is a trademark of Texas Instruments.
I2C is a trademark of NXP Semiconductors, Inc.
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Contents
1 EVM Overview ............................................................................................................... 3
2 Quick Start ................................................................................................................... 4
3 Quick Reference ............................................................................................................ 6
4 Using the ADS1178EVM-PDK/ADS1278EVM-PDK Plug-in ADCPro ................................................ 7
5 ADS1278EVM Hardware Details ........................................................................................ 11
6 Schematic and Bill of Materials .......................................................................................... 16
List of Figures
1 ADS1x7xEVM Default Jumper Locations................................................................................ 4
2 Channel Enable ............................................................................................................. 8
3 Clock Settings and Mode .................................................................................................. 9
List of Tables
1 EVM-Compatible Device Data Sheets ................................................................................... 1
2 Default Jumper/Switch Configuration..................................................................................... 4
3 Critical Connections ........................................................................................................ 6
4 Operating Modes: Clock Frequency .................................................................................... 10
5 Jumper and Switch Descriptions ........................................................................................ 11
6 J3: Primary Analog Interface Pinout .................................................................................... 13
7 J1: Secondary Analog Interface Pinout................................................................................. 13
8 J5, Serial Interface Header............................................................................................... 14
9 J2, DOUTx Header........................................................................................................ 15
10 J3 Configuration: Power-Supply Input .................................................................................. 15
11 ADS1x7xEVM Bill of Materials .......................................................................................... 16
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1 EVM Overview
The ADS1x7xEVM-PDK is an evaluation module kit that includes an EVM, MMB0 motherboard and
software. As a stand-alone PCB, the ADS1x7xEVM is useful for prototyping designs and firmware. It can
be connected to any modular EVM system interface card.
1.1 Features
ADS1x7xEVM Features:
•Contains all support circuitry needed for the ADS1178/ADS1278/ADS1174/ADS1274
•Voltage reference options: external or onboard
•Clock options: External clock source (PLL or DSP supplied) or 27MHz onboard crystal oscillator
•GPIO access
•Compatible with the TI Modular EVM System
ADS1x7xEVM-PDK includes the ADS1x7xEVM board with the DSP-based MMB0 motherboard, that can
be used with ADCPro™to quickly evaluate the device.
This manual covers the operation of the ADS1x7xEVM-PDK. Throughout this document, the abbreviation
EVM and the term evaluation module are synonymous with the
ADS1178EVM/ADS1278EVM/ADS1174EVM/ADS1274EVM. For clarity of reading, this manual will refer
only to the ADS1278EVM or ADS1x7xEVM-PDK, but operation of the EVM and kit for the
ADS1178/ADS1274/ASD1174 is identical, unless otherwise noted.
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2 Quick Start
This section provides a QuickStart guide to quickly begin evaluating the ADS1x7xEVM with ADCPro.
2.1 Default Jumper/Switch Configuration
Figure 1 shows the jumpers found on the EVM and the respective factory default conditions for each.
Figure 1. ADS1x7xEVM Default Jumper Locations
Table 2 lists the jumpers and switches and the factory default conditions.
Table 2. Default Jumper/Switch Configuration
Switch Default Position Switch Description
S1 All OFF (Down) Powerdown channel DIP switches (Hardware control)
Mode, Format, and CLKDIV DIP switches(Hardware
S2 All OFF (Down) control)
S3 INT (Right) On-board Voltage Reference Selected
Channel 4 header connected to converter (not
S4 Header connected to converter (Left) buffered)
Channel 3 header connected to converter (not
S5 Header connected to converter (Left) buffered)
S6 FS (Down) FS serial interface format
Channel 2 header connected to converter (not
S7 Header connected to converter (Left) buffered)
Channel 1 header connected to converter (not
S8 Header connected to converter (Left) buffered)
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Table 2. Default Jumper/Switch Configuration (continued)
Switch Default Position Switch Description
Jumper
J1 Open FSX NOT connected to SYNC/DRDY
J2 Short FSR connected to SYNC/DRDY
J3 Short Input buffer op-amps are powered down
J4 Short Clock source selection using software control
External clock source selected (invalid since using
J5 Short software control)
2.2 ADS1x7xEVM-PDK Kit Operation
To prepare to evaluate the ADS1278 with the ADS1x7xEVM-PDK, complete the following steps:
1. Verify the jumpers on the ADS1x7xEVM are as shown in Figure 1 (note that these settings are the
factory-configured settings for the EVM).
2. Using ADCPro HW/SW Installation Manual, verify the MMB0 jumpers are in the default position and
install ADCPro and ADS1278EVM plug-in software. Complete hardware connection and driver
installation as part of ADCPro HW/SW Installation Manual using the below settings.
•MMB0 J13A →Open
•MMB0 J13B →Short
•No additional power connections are required
3. Plug the ADS1278EVM onto the MMB0 (if not already connected). The female portion of J3, J5 and J4
on the EVM align with male connectors J7, J4, and J5 respective on the MMB0.
4. Connect the included AC adapter to the MMB0.
CAUTION
Do not misalign the pins when plugging the ADS1278EVM into the MMB0.
Check the pin alignment of J3, J5, and J4 carefully before applying power to
the PDK.
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3 Quick Reference
Table 3 provides a quick summary of the connections required for operation of the EVM as a stand-alone
Table 3. Critical Connections
Function Header/Pin Pin Name Description
CS N/A N/A N/A
SCLK J5.3 CLKX SCLK
SPI DIN J5.11 DX Data In
DOUT J5.13 DR Data Out
Interrupt J5.15 INT FSYNC
1.8V J3.7 +1.8VD Digital supply
Power 3.3V J3.9 +3.3VD Digital supply
5.0V J3.3 +5VA Analog supply
Channels 1-4 J1.1-8 Analog Inputs
Analog Inputs Analog Inputs (ADS1278 and
Channels 5-8 J3.3-10 ADSADS1178 only)
CAUTION
When using the EVM as part of the ADS1278EVM-PDK, the DIP switches S1
and S2 must all be switched so that they are down, toward the center of the
board. Failure to do so may damage the EVM.
3.1 Analog Inputs
The analog inputs for the ADS1278EVM are connected to J1 and J3. Channels 1-4 connect to J1 and
provisions are provided to buffer these signals before being connected to the converter. Switches S4-S5
and S7-S8 control whether the buffered or unbuffered signal is connected to the ADS1278. Channels 5-8
connect to J3 and have an RC filter available to filter the input before connecting to the converter.
Channels 5-8 do not have provisions for buffering the signal.
3.2 Digital Control
The digital control signals can be applied directly to J4 (top or bottom side).
3.3 Power Supply
The ADS1278EVM requires power rails as follows:
•5.0V analog supply - supplied by MMB0 motherboard via J13B
•3.3V digital supply - supplied by MMB0 motherboard
•1.8V digital supply - supplied by MMB0 motherboard
3.4 Voltage Reference
The ADS1278EVM has two options for the reference voltage. Switch S3 selects the reference voltage
from either the buffered REF5025 or a external reference voltage that is connected to the reference pins
of J3.
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4 Using the ADS1178EVM-PDK/ADS1278EVM-PDK Plug-in ADCPro
The ADS1278EVM-PDK plug-in for ADCPro provides complete control over all settings of the ADS1278. It
consists of a tabbed interface (see Figure 2), with different functions available on different tabs. The tabs
are:
•Channel Enable
•Settings
•About
The user can adjust the ADS1178EVM/ADS1278EVM settings when not acquiring data. During
acquisition, all controls are disabled and settings may not be changed. When a setting is changed on the
ADS1178EVM/ADS1278EVM plug-in, the setting immediately updates on the board.
Settings on the ADS1178EVM/ADS1278EVM correspond to settings described in the ADS1278 product
data sheet product data sheet.
4.1 Top Level Controls
You can adjust the ADS1278EVM settings when you are not acquiring data. During acquisition, all
controls are disabled and settings may not be changed.
The effective data rate of the ADS1278 depends upon settings of the Clock Freq and Operating Mode.
The Data Rate indicator in the upper right corner of the plug-in interface (see Figure 2) is always visible
and updates whenever a setting changes that affects the data rate.
4.2 Channel Enable Tab
The ADS1278 can acquire data from one to eight channels simultaneously. The Channel Enable tab (as
shown in Figure 2) provides the control to power on or off each channel.
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Figure 2. Channel Enable
The Master (All) Enable control allows for the selection of channels to convert. Manual Control allows
channel enable control via CH1 through CH8 selector switches. All Channels Enabled and All Channels
Disabled turn all the selector switches either ON or OFF.
4.3 Settings Tab
The Settings tab allows for the selection of the various clock frequencies, operating mode, data format,
and other settings.
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Figure 3. Clock Settings and Mode
The Clock Source control selects the input clock source for the ADS1278. The clock can be selected
from the MMB0 PLL, an External source, or use the On-board oscillator.
The Modulator Frequency indicator shows the ADS1278 modulator frequency based on the clock
source.
The Clock Frequency control allows the user to input the desired clock frequency when the PLL clock
source is selected. Once the frequency is entered, the software finds the closest frequency for the PLL to
synthesize (and which is within the maximum allowable frequency for the mode selected). This clock
frequency is configured in the PLL and overwrites the user entered value in the Clock Frequency
indicator.
The Operating Mode control allows selection of the converter operating mode: High-Speed,
High-Resolution,Low-Power, or Low-Speed.
The CLKDIV control can be set to 0or 1.
The Data Output Format allows selection of the data output formats. For the ADS1278EVM software, the
formats are limited to the Frame Sync, TDM Format. The available options select whether the software
collects data for all channels Fixed Mode or only channels that are powered up Dynamic Mode.
The Vref control allows the user to input the current Vref value being used by the data converter. This
control does not change the actual reference voltage, but is required for the software to process the data
correctly for display.
The maximum clock frequency is shown for the different converter options in Table 4.
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Table 4. Operating Modes: Clock Frequency
Operating Mode CLKDIV Frequency (MHz)
High-Speed 1 32.768
High-Resolution 1 27
Low-Power 1 27
Low-Power 0 13.5
Low-Speed 1 27
Low-Speed 0 5.4
4.4 About Tab
The About tab provides information on the EVM hardware and software versions.
Plug-in Version is software version of ADCPro plug-in.
Firmware Version is firmware version loaded and running on the processor.
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5 ADS1278EVM Hardware Details
The ADS1278EVM is designed to easily interface with multiple control platforms. Dual-row, header/socket
combinations at J3, J4, and J5 allow connection to external circuitry for evaluation and debug.
5.1 Jumpers and Switches
Jumpers and Switches function shown in table below
Table 5. Jumper and Switch Descriptions
Jumper/Switch Functions Descriptions
J1 FSYNC/DRDY Source Short to select FSR as the source(1)
J2 FSYNC/DRDY Source Short to select FSX as the source(1)
Short - input buffers powered down
J3 Analog Input Buffers Powerdown Open - input buffers powered up
Short - Software control
J4 Hardware/Software Control of Clock Source Open - Hardware control
Internal/External Clock Select (Hardware Short - External clock source selected
J5 control) Open - Internal clock source selected
Hardware control for GPIO2 (set to OFF position for use with
GPIO2 software)
Hardware control for GPIO3 (set to OFF position for use with
GPIO3 software)
Hardware control for GPIO4 (set to OFF position for use with
GPIO4 software)
S1 Hardware control for CLKDIV (set to OFF position for use with
CLKDIV software)
Hardware control for GPIO0 (set to OFF position for use with
GPIO0 software)
Hardware control for GPIO1 (set to OFF position for use with
GPIO1 software)
Hardware control for PWDN1 (set to OFF position for use with
Powerdown Channel 1 software)
Hardware control for PWDN2 (set to OFF position for use with
Powerdown Channel 2 software)
Hardware control for PWDN3 (set to OFF position for use with
Powerdown Channel 3 software)
Hardware control for PWDN4 (set to OFF position for use with
Powerdown Channel 4 software)
S2 Hardware control for PWDN5 (set to OFF position for use with
Powerdown Channel 5(2) software)
Hardware control for PWDN6 (set to OFF position for use with
Powerdown Channel 6(2) software)
Hardware control for PWDN7 (set to OFF position for use with
Powerdown Channel 7(2) software)
Hardware control for PWDN8 (set to OFF position for use with
Powerdown Channel 8(2) software)
Selects source for reference - buffered on-board ref or header
S3 Converter Reference source selector (external)
Selects Channel 4 input source - header or input buffer
S4 Channel 4 Input source selector Left - header
Right - input buffer
Selects Channel 3 input source - header or input buffer
S5 Channel 3 Input source selector Left - header
Right - input buffer
(1) Only one of FSYNC/DRDY signals should be connected at a time (J1 or J2).
(2) Channels 4-8 only available for ADS1278 and ADS1178.
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Table 5. Jumper and Switch Descriptions (continued)
Jumper/Switch Functions Descriptions
FS - Frame Sync format(3)
S6 Serial Interface format SPI - SPI-compatible mode(3)
Selects Channel 2 input source - header or input buffer
S7 Channel 2 Input source selector Left - header
Right - input buffer
Selects Channel 1 input source - header or input buffer
S8 Channel 1 Input source selector Left - header
Right - input buffer
(3) Refer to Section 5.5.1 for more details.
5.2 Power-Down, Mode, and Format Control
The ADS1278 has several pins to control the power-down of individual channels, and select the mode and
format for the digital interface.
For users of the ADS1278EVM as a stand-alone module, these pins may be pulled high or low through
DIP switches S1 and S2 (see Table 5). Refer to the ADS1278 product data sheet for complete details on
these pins and which state sets which options.
For use in the ADS1x7xEVM-PDK, the state of these pins is controlled by software, using the I2C port
expander on the EVM. When using the EVM with the EVM-PDK, the DIP switches S1 and S2 must all be
switched down (toward the center of the board). The ADS1278EVM-PDK software checks at startup to
verify that these switches are set correctly, and generates an error message for incorrect settings. The
software cannot detect if the switches are changed after startup.
CAUTION
When using the ADS1x7xEVM-PDK, the DIP switches S1 and S2 must all be
switched down (toward the center of the board). Failure to do so may damage
the EVM.
5.3 Clock Source
The ADS1278 clock can come from one of several sources: the onboard 27MHz crystal oscillator, a clock
supplied by a processor on the TOUT pin (J4.17), or an external clock source connected between J4.17
(TOUT) and J4.18 (DGND).
If the onboard 27MHz oscillator is selected, the device can be run in high-speed mode, high-resolution
mode, low-power mode, or low-speed modes with CLKDIV set to 1.
If the performance of the device must be explored with CLKDIV set to 0 in the low-power and low-speed
modes, an external clock must be provided to the board, either using the TOUT connection or having an
external clock source connected to J18. The same condition is true if frequencies other than the 27MHz
provided by the onboard oscillator must be investigated.
5.4 Analog Headers, J1 and J3
For maximum flexibility, the ADS1278EVM is designed for easy interfacing to multiple analog sources.
These headers/socket provide access to the analog input pins of the ADS1278.
Four of the analog input sources (Channels 1–4) connect directly to J3 (top or bottom side) or through
signal-conditioning modules available for the modular EVM system. These inputs have provisions to buffer
the inputs using THS4521 before connecting to the converter. Switches S4-5 and S7-8 provide the
capability to connect either the header directly or through a buffer. When the buffers are not selected, the
op-amps used for buffering can be powered down by shorting JP3.
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Analog input sources (Channels 5-8) are connected directly to J1. These inputs can be filtered by
installing passive components in the option filter circuitry. By default, the resistors are populated with 0Ω
resistors and the capacitors are not installed. No circuitry is provided to buffer these signals before
connecting to the converter.
Table 6. J3: Primary Analog Interface Pinout
Description Signal Pin Number Signal Description
Analog Input Channel 4 Negative ANN4 J3.1(1) J3.2 ANP4 Analog Input Channel
4 Positive
Analog Input Channel 3 Negative ANN3 J3.3 J3.4 ANP3 Analog Input Channel
3 Positive
Analog Input Channel 2 Negative ANN2 J3.5 J3.6 ANP2 Analog Input Channel
2 Positive
Analog Input Channel 1 Negative ANN1 J3.7 J3.8 ANP1 Analog Input Channel
1 Positive
Analog Ground AGND J3.9 J3.10 Not Connected Not used for this
design
Analog Ground AGND J3.11 J3.12 Analog Ground AGND
Analog Ground AGND J3.13 J3.14 Not Connected Not used for this
design
Not used for this design Not Connected J3.15 J3.16 Not Connected Not used for this
design
Analog Ground AGND J3.17 J3.18 EXTREFN External Reference
negative input
Analog Ground AGND J3.19 J3.20 EXTREFP External Reference
positive input
(1) Pin 1 is top left-hand corner, located next to reference designator.
Table 7. J1: Secondary Analog Interface Pinout
Description Signal Pin Number Signal Description
Not used for this design Not Connected J3.1(1) J3.2 Not Connected Not used for this
design
Analog Input Channel 8 Negative ANN8 J3.3 J3.4 ANP8 Analog Input Channel
8 Positive
Analog Input Channel 7 Negative ANN7 J3.5 J3.6 ANP7 Analog Input Channel
7 Positive
Analog Input Channel 6 Negative ANN6 J3.7 J3.8 ANP6 Analog Input Channel
6 Positive
Analog Input Channel 5 Negative ANN5 J3.9 J3.10 ANP5 Analog Input Channel
5 Positive
(1) Pin 1 is top right-hand corner, located next to reference designator.
5.5 Digital Interface
The digital signals are controlled via DSP interface or I2C ICs on the EVM. Some of the digital control pins
allow control via hardware or software methods. See Section 5.2 for details on these pins and their
operation. The digital control signals can be applied directly to the EVM or by connecting the EVM to a
DSP or micro controller interface board, such as the MMB0 if purchased as part of the
ADS1278EVM-PDK, the 5-6K Interface or HPA-MCUInterface boards which are available from Texas
Instruments. For a list of compatible interface and/or accessory boards for the EVM or the ADS1278, see
the relevant product folder on the TI web site.
5.5.1 Digital Format Control
The ADS1278 allows the serial interface to be used in two different formats: an SPI-compatible mode and
a frame-sync format. Switch S6 switches between these two formats:
•SPI format configures the signals as follows:
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– The SCLK input of the converter is driven by the serial port signal CLKX, pin J5.3.
–The signal from the selected source for the clock (see Section 5.3,Clock Source) is connected to
the CLKR pin (J5.5) allowing the serial port of a processor to be synchronized to the converters
master clock.
–The signal from the selected clock source is routed to the CLK input of the converter.
–Port P10 of the I2C port expander U18 is connected to a logic high level, so that the position of
switch S12 can be read back by software.
•FS format configures the signals as follows:
–The SCLK input of the converter is driven by the serial port signal CLKR, pin J5.5.
–The signal from the selected clock source is connected to the CLKX pin (J5.3), allowing the serial
port of a processor to be synchronized to the converter's master clock.
–The CLK input of the converter is driven by the CLKR signal (J5.5). This ensures that the CLK and
SCLK signals have the same phase and the correct ratio as outlined in the data sheet of the
device.
–Port P10 of the I2C port expander U18 is connected to a logic low level, so that the position of
switch S12 can be read back by software.
For use in the ADS1278EVM-PDK, S6 must be in the FS position, which is the factory default setting.
Switching to SPI format will allow users to connect the EVM to any SPI-compatible processor not
supporting the frame-sync mode. If this format is selected, keep in mind that the high-speed mode will not
operate at full speed (32.768MHz) because of the limitations outlined in the device product data sheet.
5.5.2 Serial Data Interface, J5
This header/socket provides access to the digital control and serial data pins of the ADC.
All logic levels on J5 are 3.3V CMOS, except for the I2C™pins. These pins conform to 3.3V I2C rules.
Table 8 describes the J5 serial interface pins.
Table 8. J5, Serial Interface Header
Pin
Number
Signal Name (J4) Signal Name Function
Synchronize channels input SYNC 1(1) 2 MODE0 Select bit 0 of converter
MODE
SPI clock SCLK 3 4 DGND Digital ground
SCLK clock CLKR 5 6 MODE1 Select bit 1 of converter
MODE
DRDY/FSYNC source 1 DRDY/FSYNC 7 8 FORMAT0 Select bit 0 of FORMAT
to select Frame-Sync/SPI
Protocol
DRDY/FSYNC source 2 DRDY/FSYNC 9 10 DGND Digital ground
ADS1278 SPI data in DIN 11 12 FORMAT1 Select bit 1 of FORMAT
to select Frame-Sync/SPI
Protocol
ADS1278 data out DOUT1(2) 13 14 FORMAT2 Select bit 2 of FORMAT
to select Frame-Sync/SPI
Protocol
DRDY/FSYNC to DSP DRDY/FSYNC 15 16 SCL I2C clock
(interrupt)
Can be used to provide a clock CLK 17 18 DGND Digital ground
from a processor
Clock source select (SW CLK Select 19 20 SDA I2C data
mode)
(1) Pin 1 is top left-hand corner, located next to reference designator.
(2) DOUT1 buffered through a D flip-flop. See Section 5.5.3.1 below.
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Some pins on J5 have weak pull-up/down resistors. These resistors provide default settings for many of
the control pins. Many pins on J5 correspond directly to ADS1278 pins. See the ADS1278 product data
sheet for complete details on these pins.
5.5.3 Data Output Signals
5.5.3.1 DOUT on Digital Interface J5
In TDM mode, the data from all eight channels can be observed on the DOUT1 pin of the converter. The
DOUT1 signal is used by the ADS1x7xEVM-PDK to read back and display all the channels. The digital
data output pin on the digital interface header J5 is connected to DOUT1 signal via a D flip-flop. The D
flip-flop provides a half cycle delay in order to align the data correctly to reach the higher speeds of the
device. Otherwise, the propagation delay from the MSB in Frame Sync mode may result in missing the
MSB out of the data word.
5.5.3.2 DOUTx Header, J2
All the data output signals (DOUT1 to DOUT8) can be monitored on J2. Table 9 illustrates the pinout for
J2.
Table 9. J2, DOUTx Header
Data Out Line Pin Number Data Out Line
DOUT1 1(1) 2 DOUT2
DOUT3 3 4 DOUT4
DOUT5 5 6 DOUT6
DOUT7 7 8 DOUT8
(1) Pin 1 is top right-hand corner, located next to reference designator.
5.6 Power Supply Header, J3
J3 is the power-supply input connector. Table 10 lists the configuration details for J3. Supplies of 1.8V,
3.3V, and 5.0V are required for operation of the EVM. When using the EVM as part of the EVM-PDK,
these voltages are generated by the MMB0 and no external supplies are required. For operation as a
stand-alone EVM, the power supplies should be connected as shown below.
Table 10. J3 Configuration: Power-Supply Input
Pin Number
Function Pin Name (J5) Pin Name Function
Not used for this design Not used 1(1) 2 Not used Not used for this design
+5V analog supply +5VA 3 4 Not used Not used for this design
Digital ground DGND 5 6 AGND Analog ground input
1.8V digital supply +1.8VD 7 8 Not used Not used for this design
3.3V digital supply +3.3VD 9 10 N/A Do not use
(1) Pin 1 is bottom left-hand corner, located next to reference designator.
NOTE: For monitoring the current from each supply, CM1, CM2, and CM3 (0Ωresistors) can be
removed and replaced with sense resistors or ammeters.
The ADS1278 digital supplies are connected as follows:
•IOVDD supply is connected to the +1.8VD pin of the J3 header.
•DVDD supply is connected to the +3.3VD pin of the J3 header.
The ADS1278 analog supply, AVDD, is connected to the +5VA pin of the J3 header.
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6 Schematic and Bill of Materials
A complete schematic for the ADS1x7xEVM is appended to this user's guide. The bill of materials is
provided in Table 11. Gerber files are available on request. Please e-mail [email protected] or E2E
Community Forums and ask for details on how to receive the files.
6.1 Bill of Materials
NOTE: All components should be compliant with the European Union Restriction on Use of
Hazardous Substances (RoHS) Directive. Some part numbers may be either leaded or
RoHS. Verify that purchased components are RoHS-compliant. (For more information about
TI's position on RoHS compliance, see the http://www.ti.com.)
Table 11. ADS1x7xEVM Bill of Materials
Item No. Qty Value Ref Des Description Manufacturer Part Number
1 1 100u C1 Capacitor, Ceramic, X5R, 10V Taiyo Yuden LMK325BJ107MM-T
2 1 150n C2 Capacitor, Ceramic, X7R, 25V TDK C1608X7R1E154K
3 25 0.1u C3, C11, C13, Capacitor, Ceramic, X7R, 25V TDK C1608X7R1E104K
C17, C20, C21,
C22, C27, C28,
C29, C38, C39,
C40, C41, C42,
C44, C45, C46,
C49, C50, C51,
C54, C55, C56,
C58
4 3 1.0u C4, C6, C43 Capacitor, Ceramic, X7R, 25V TDK C1608X7R1E105K
5 4 10u C5 C7 C26 C57 Capacitor, Ceramic, X5R, 10V TDK C1608X5R1A106M
6 4(1) 2.2n C8-10 C12 Capacitor, Ceramic, C0G, 50V TDK C1608COG1H222/*J
4 2.2n C16 C18 C23 C25
7 8 1.5n C14-15 C19 C24 Capacitor, Ceramic, X7R, 25V TDK C1608X7R1E152M
C47-48 C52-53
8(1) 1.5n C30-37
8 3 0 CM1-3 Resistor, Chip, 1/4W Vishay Dale CRCW06030000Z0EAHP
9 1(1) J1 (Top) Header, SMT Vert. 5x2 pin, 100mil spacing Samtec TSM-105-01-T-DV-P
10 1 J5 (Top) Header, SMT Vert. 5x2 pin, 100mil spacing Samtec TSM-105-01-T-DV-P
11 1 J5 (Bottom) Header, SMT Vert. 5x2 pin, 100mil spacing Samtec SSW-105-22-F-D-VS-K
12 1 J2 Header, SMT Vert. 4x2 pin, 100mil spacing Samtec TSW-104-07-L-S
13 2 J3 J4 Header, SMT Vert. 10x2 pin, 100mil spacing Samtec TSM-110-01-T-DV-P
14 2 J3 J4 (Bottom) Header, SMT Vert. 10x2 pin, 100mil spacing Samtec SSW-110-22-F-D-VS-K
15 5 JP1-JP5 Header, Male 2-pin, 100mil spacing Samtec TSW-102-07-L-S
16 1 2k R1 Resistor, Chip, 1/10W, 5% Rohm MCR03EZPJ202
17 18 1k R2 R17-18 R20-22 Resistor, Chip, 1/10W, 5% Rohm MCR03EZPJ102
R24 R26-27
R38-40 R42-43
R45-48
18 6 47 R3 R12-13 R16 Resistor, Chip, 1/10W, 5% Rohm MCR03EZPJ470
R25 R41
19 8(1) 0 R4-11 Resistor, Chip, 1/10W Rohm MCR03EZPJ000
20 8 49.9 R14-15 R23 R28 Resistor, Chip, 1/10W, 1% Rohm MCR03EZPJ49R9
R36-37 R49-50
21 3 100k R19 R29 R44 Resistor, Chip, 1/10W, 5% Rohm MCR03EZPJ104
22 2 470k R30-31 Resistor, Chip, 1/10W, 5% Rohm MCR03EZPJ474
23 2 100k R32-33 Resistor Pack, 8x Panasonic EXB-2HV104JV
24 1 10k R34 Resistor, Chip, 1/10W, 5% Rohm MCR03EZPJ103
25 1 4.3k R35 Resistor, Chip, 1/10W, 5% Rohm MCR03EZP432
26 2 47k R51-52 Resistor, Chip, 1/10W, 5% Rohm MCR03EZPJ473
(1) These parts are not installed for ADS1274 and ADS1174
16 ADS1x7xEVM-PDK SBAU197–February 2012
Submit Documentation Feedback
Copyright ©2012, Texas Instruments Incorporated

www.ti.com Schematic and Bill of Materials
Table 11. ADS1x7xEVM Bill of Materials (continued)
Item No. Qty Value Ref Des Description Manufacturer Part Number
27 1 S1 Switch, SMD Low Profile 08 Position CTS 218-8LPST
28 1 S2 Switch, 6 POS, SPST, Low Profile, SMT, CTS 218-8LPST
0.50 centers
29 5 S3-5 S7-8 Switch, Slide DPDT, Low Profile TE Connectivity SSB22
30 1 S6 Switch, Slide, 4 x SPDT, SMD TE Connectivity SSB42
31 4 TP1 TP4 TP7 Test Point, Black, Thru Hole Color Keyed Keystone 5001
TP11
32 2 TP6 TP8 Test Point, White, Thru Hole Color Keyed Keystone 5002
33 5 TP2 TP3 TP5 TP9 Test Point, Red, Thru Hole Color Keyed Keystone 5000
TP10
34 1 U1 IC, Precision Voltage Reference, 2.5V TI REF5025AID
35 1 U2 IC, Op Amp, High-Speed, Single-Supply, TI OPA2350DGK
R-R
36 4 U3 U5 U9 U11 IC, Negative R-R Input, R-R Output, Fully TI THS4521DGK
Differntial Amplifier
37 1(2) U4 IC, Quad/Octal, Simultaneous Sampling, TI ADS1278PAP
24-Bit A-D Converter
38 1 U6 Single 2 line To 1Line Data TI SN74LVC2G157DCT
Selector/Multiplexer
39 1 U10 IC, Single Inverter TI SN74LVC1G04DBV
40 1 U12 IC, single Positive-Edge-Triggered D-Type TI SN74LVC2G74DCU
Flip-Flop With Clear And Reset
41 1 U13 IC, Configurable Multiple-Function Gate TI SN74LVC1G97DCK
42 1 U14 IC, 256K CMOS Serial EEPROM Microchip 24AA256-I/ST
43 2 U7-8 IC, Low Voltage 16-BIT I2C and SMBus TI TCA9535RTW
Low-Power I/O Expander With Interrupt
Output and Configuration Registers
44 1 Y1 Clock Oscillator, 27MHz CTS CB3LV-3I-27M0000
45 1 PCB, 3.31 In x 2.88 In x 0.062 In Any 6492525
46 4 Shunt, 100-mil, Black 3M 929950-00
(2) Installed for ADS1278EVM-PDK. For other EVM-PDKs, the appropriate device will be installed.
17
SBAU197–February 2012 ADS1x7xEVM-PDK
Submit Documentation Feedback Copyright ©2012, Texas Instruments Incorporated

07APR11
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Texas Instruments
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4
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Filename
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2
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F
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Number
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Size
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E
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D
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C
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B
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A
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1
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3
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Title
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2
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4
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F
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of
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Sheet
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E
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Date
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C
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B
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A
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4
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C

ADS1278EVM

2/9/2012

JP5 = HW SEL (INT/EXT)

JP4 = HW/SW CTRL (HW/SW)

INT/EXT CLK SOURCE

CM1-3 are available for current monitoring

(See page -1)

(see table below)

JP4 JP5 Setting

OFF ON Hardware External

OFF OFF Hardware Internal

ON x Software Control (GPIO5)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

J4

C51

0.1u

C27

0.1u

1

A

2

B

3

Y

4

GND

5

Y

6

B_A

7

G

8

VCC

U6

R30

470k

1

2

3

4

5

6

7

8

9

10

J5

C11

.1u

C45

0.1u

C42

0.1u

C46

0.1u

C20

0.1u

R25

47

R41

47

R16

47

R13

47

R12

47

R51

47k

R31

470k

C43

1u

R40

1k

C57

10u

C26

10u

J2

1

2

JP4

R19

100k

2

4

5

3

U10

1

CLK

2

D

3

Q

7

PRE

6

CLR

5

Q

4

GND

8

VCC

U12

R44

100k

1

AINP2

2

AINN2

3

AINP1

4

AINN1

5

AVDD

6

AGND

7

DGND

8

TEST0

9

TEST1

10

CLKDIV

11

SYNC

12

DIN

13

DOUT8

14

DOUT7

15

DOUT6

16

DOUT5

17

DOUT4

18

DOUT3

19

DOUT2

20

DOUT1

21

DGND

22

IOVDD

23

IOVDD

24

DGND

25

DGND

26

DVDD

27

CLK

28

SCLK

29

FSYNC_DRDY

30

FORMAT2

31

FORMAT1

32

FORMAT0

33

MODE1

34

MODE0

35

/PWDN8

36

/PWDN7

37

/PWDN6

38

/PWDN5

39

/PWDN4

40

/PWDN3

41

/PWDN2

42

/PWDN1

43

AGND

44

AVDD

45

AINP8

46

AINN8

47

AINP7

48

AINN7

49

AINP6

50

AINN6

51

AINP5

52

AINN5

53

AVDD

54

AGND

55

VCOM

56

VREFP

57

VREFN

58

AGND

59

AGND

60

AVDD

61

AINP4

62

AINN4

63

AINP3

64

AINN3

65

PWPD

U4

REFP_HDR

REFN_HDR

REFP

REFN

AGND

AVDD

REF_CKT

7

8

9

10

11

12

4

5

6

1

2

3

S6

SW_SSB42

6

5

7

OUTB

U2-B

C54

0.1u

CM1

0

CM3

0

CM2

0

C44

0.1u

C41

0.1u

2

1

JP1

2

1

JP2

1

EOH

3

OUT

2

GND

4

VCC

Y1

C28

0.1u

1

IN1

2

GND

3

IN0

4

Y

5

VCC

6

IN2

U13

R52

47k

1

2

JP5

C56

0.1u

TP1

TP8

TP6

TP11

TP4

TP7

TP5

TP2

TP3

SYNC

DIGITAL

[3]

CM

[2]

ANALOG_IN

[1,2,3]

REFP_HDR

[2]

REFN_HDR

[2]

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

SCL

SDA

AGND

AVDD

IOVDD

ANALOG_IN

[1,2,3]

CHAN-N1

CHAN-P1

CHAN-N2

CHAN-P2

CHAN-N3

CHAN-P3

CHAN-N4

CHAN-P4

AVDD

CHAN-N5

CHAN-P5

CHAN-N6

CHAN-P6

CHAN-N7

CHAN-P7

CHAN-N8

CHAN-P8

PWDN1

PWDN2

PWDN3

PWDN4

PWDN5

PWDN6

PWDN7

PWDN8

SW_IND

AGND

AGND

AGND

AGND

AGND

DGND

AGND

DGND

IOVDD

IOVDD

IOVDD

DGND

DGND

DGND

GPIO2

GPIO3

GPIO4

AVDD_1

[1]

AVDD_1

[1]

AVDD_1

[1]

AVDD_1

[1]

DVDD_26

[1]

IOVDD_22_23

[1]

IOVDD_22_23

[1]

DVDD_26

[1]

AGND

AVDD

AGND

DGND

IOVDD

GPIO0

GPIO1

DGND

IOVDD

DGND

DGND

DGND

IOVDD

IOVDD

IOVDD

IOVDD

IOVDD

IOVDD

DGND

CLKDIV

[3]

DGND

DGND

DGND

DGND

DGND

DGND

AGND

SCLK


2/9/2012

ADS1278EVM

C

4

A

B

C
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D

Date

E
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Sheet

of
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F

4

2

1

Title

3

1

A

B

C

D

E

Size

Number

F

2

Filename

Drawn by

3

Engineer

Rev
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-1
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Texas Instruments
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07APR11
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R1

2k

R3

47

C2

150n

C3

0.1u

S3

C7

10u

R2

1k

C1

100u

1

DNC

2

VIN

3

TEMP

4

GND

5

TRIM

6

VOUT

7

NC

8

DNC

U1

C5

10u

C4

1u

2

3

1

OUTA

4

V-

8

V+

U2-A

C6

1u

AVDD

[1,2]

AGND

[1,2,3]

REFN

[1]

REFP

[1]

REFP_HDR

[1,2]

REFN_HDR

[1,2]


E
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Filename
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2

F

Number
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Size

E

D
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C
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B
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A
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1
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3
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Title

1
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2
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4
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F

of

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
E

Date

D

C

B

A

4

C

ADS1278EVM

2/9/2012

PWRDN BUFFERS

C50

0.1u

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

J3

S7

S8

C25

2.2n

C23

2.2n

8

VIN+

2

VOCM

1

VIN-

6

VS-

3

VS+

4

VOUT+

5

VOUT-

7

PD

U11

R49

49.9

R50

49.9

R47

1k

C52

1.5n

R45

1k

R46

1k

C53

1.5n

R48

1k

8

VIN+

2

VOCM

1

VIN-

6

VS-

3

VS+

4

VOUT+

5

VOUT-

7

PD

U5

R23

49.9

R28

49.9

R22

1k

C19

1.5n

R24

1k

R26

1k

C24

1.5n

R27

1k

C21

0.1u

C17

0.1u

S4

S5

C18

2.2n

C16

2.2n

8

VIN+

2

VOCM

1

VIN-

6

VS-

3

VS+

4

VOUT+

5

VOUT-

7

PD

U9

R37

49.9

R36

49.9

R39

1k

C48

1.5n

R43

1k

R42

1k

C47

1.5n

R38

1k

8

VIN+

2

VOCM

1

VIN-

6

VS-

3

VS+

4

VOUT+

5

VOUT-

7

PD

U3

R14

49.9

R15

49.9

R17

1k

C14

1.5n

R20

1k

R21

1k

C15

1.5n

R18

1k

C49

0.1u

R29

100k

1

2

JP3

C55

0.1u

C13

0.1u

C39

0.1u

C22

0.1u

TP10

TP9

ANP1

ANP2

ANN1

ANN2

CHAN-P2

CHAN-P1

ANN2

REFN_HDR

[1]

REFP_HDR

[1]

ANN1

ANALOG_IN

[1,3]

CHAN-N1

CHAN-N2

CHAN-N3

ANN3

ANP3

BRD_ANLG_IN

ANP1

ANP2

CHAN-P3

CHAN-P4

CHAN-N4

AVDD

AVDD

CM

AVDD

AVDD

ANP4

ANN4

CM

CM

ANN3

ANP3

ANP4

ANN4

AGND

AGND

AVDD

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

BUF_PDN

[2]

BUF_PDN

[2]

BUF_PDN

[2]

BUF_PDN

[2]

ANN4

ANP4

AVDD

AGND

AVDD

AGND

AVDD

AGND

AGND

AVDD
