Texas Instruments BQ24260EVM-611 User manual

User's Guide
SLUUAV8A –February 2014–Revised August 2014
User's Guide for QFN Packaged bq24260, bq24261, and
bq24262 3-A Battery Charger Evaluation Module
The bq24260, bq24261, and bq24262 evaluation module on the printed-circuit board (PCB) PWR611 is a
complete charger module for evaluating a compact, flexible, high-efficiency, USB-friendly, switch-mode
charge management solution for single-cell, Li-ion and Li-polymer batteries used in a wide range of
portable applications.
Contents
1 Introduction ................................................................................................................... 2
1.1 bq2416x IC Features............................................................................................... 2
1.2 bq24260, bq24261, bq24262 EVM Features.................................................................... 2
1.3 Schematic............................................................................................................ 3
1.4 I/O Description ...................................................................................................... 4
1.5 Test Points........................................................................................................... 4
1.6 Control and Key Parameters Setting............................................................................. 5
1.7 Recommended Operating Conditions............................................................................ 5
2 Test Summary................................................................................................................ 6
2.1 Definitions............................................................................................................ 6
2.2 Recommended Test Equipment .................................................................................. 6
2.3 Recommended Test Equipment Setup .......................................................................... 8
2.4 Recommended Test Procedure ................................................................................. 10
3 Printed-Circuit Board Layout Guideline.................................................................................. 12
4 Bill of Materials and Board Layout ...................................................................................... 13
4.1 Bill of Materials .................................................................................................... 13
4.2 Board Layout....................................................................................................... 16
List of Figures
1 bq24260, bq24261, bq24262EVM Schematic ........................................................................... 3
2 BAT_Load (PR1010) Schematic........................................................................................... 7
3 Connections of HPA172 Kit ................................................................................................ 8
4 Original Test Setup for bq24260, bq24261, bq24262 EVM............................................................ 9
5 Main Window of the bq2426xSW Evaluation Software................................................................ 10
6 Top Assembly Layer....................................................................................................... 16
7 Top Layer ................................................................................................................... 17
8 First Internal Layer ......................................................................................................... 18
9 Second Internal Layer ..................................................................................................... 19
10 Bottom Layer................................................................................................................ 20
List of Tables
1 Bill of Materials - PWR611................................................................................................ 13
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Introduction www.ti.com
1 Introduction
1.1 bq2416x IC Features
The bq24260, bq24261, and bq24262 family integrates a synchronous PWM controller, power MOSFETs,
input-current sensing, high-accuracy current and voltage regulation, charge termination, and power path
management into a QFN package. The charge parameters can be programmed through an I2C interface.
Key IC features include:
• High-efficiency, fully-integrated, NMOS-NMOS, synchronous buck charger with 1.5-MHz frequency
• Charge time optimizer
• Integrated power FETs for up to a 3-A charge rate
• 5-V, 1-A USB On-the-Go (OTG) VBUS supply
• Power path management between battery and system voltages
For details, see the bq24260, bq24261, and bq24262 data sheet (SLUSBA2).
1.2 bq24260, bq24261, bq24262 EVM Features
The bq24260, bq24261, and bq24262 evaluation modules (EVM) provide a complete charger module for
evaluating compact, flexible, high-efficiency, USB-friendly, switch-mode battery charge, and power path
management solution for single-cell, Li-ion and Li-polymer battery-powered systems used in a wide range
of portable applications. Key EVM features include:
• Terminal blocks and standard headers for IN, SYS, BAT, TS; USB connector for IN
• Programmable battery voltage, charge current, input current, and status via I2C
• PC-based GUI for reading/writing to internal parameter setting and status reporting registers
• IN operating up to 10.5 V for bq24260, 14 V for bq24261 and 6.5 V for bq24262
• LED indication for status signals
• Test points for key signals available for easy test probe hook-up
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1
2
3
4
5
6
7
8
9
10
J15
STAT
DP
200
R2
TP10
DM 1
2
J13
BAT
200
R1
TP11
BAT
BAT
1
2
J14
GND
BGATEDM 1
2
J5
1.0uF
C4
GND
INT
USB
12
JP1
DP
SW
BGATE
1
2
3
JP4
CSD25401Q3
Q1
BGATE
1
2
J4
GATE
IN
SYS (OFF)
SYS
IN
1.0uF
C9
TS
CD
1
2
J1
IN
C8
DRV
1.0uF
C2
GND
0.033uF
C3
1
2
J12
SYS
1
2
J8
GND
SYS
SW SYS
1
2
J11
GND
DRV
1
2
3
JP5
HIGH
DRV
CD
CD
1
2
J10
LOW
GND
DRVDRV
12
JP2
12
JP3
TS
D1 D2
GND
TP9
1
2
J9
EXT
TS
1
2
J6
1
2
3
JP6
EXT
DRV
TP1TP2 TP3TP4 TP5 TP7
TS
SW
SIM
BAT
1.50k
R3
1.50k
R4
DRVSTAT SYSINT
50k
R7
TP6 TP8
DRV
IN 1
2
J7
GND
1
2
J3
GND
See BOM for part usage
See User's guide for voltage ratings
STAT INT
R9
12
5.62k
R5
12
12.4k
R6
1.00M
R8
1
2
3
JP7
DRV
HIGH
PSEL
LOW
1
2
3
4
5
6 7
8 9
J2
4.7uF
C1
10uF
C5
10uF
C7
C6
1.5uH
L1
1
2
1
1
1
1
1
1
2
2
2
2
I2C
PMID
1
BOOT
2
DRV
3
CD
4
TS
5
SYS
6
SYS 7
BAT 8
BAT 9
INT 10
BGATE 11
AGND 12
STAT 13
D+ 14
D- 15
SCL 16
SDA 17
IN 18
IN
19
AGND
20
PGND
21
PGND
22
SW
23
SW
24
PAD 25
U1
BQ2426XRGE
1
www.ti.com Introduction
1.3 Schematic
The bq24260, bq24261, and bq24262 EVM schematic is shown in Figure 1.
Figure 1. bq24260, bq24261, bq24262EVM Schematic
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1.4 I/O Description
Header/Terminal Block Description
J1– IN/GND Input power positive and negative terminal
J2 – USB USB mini-connector
J3 - GND DRV linear regulator negative header
J4 - IN Input power positive header
J5 - GND Battery negative header
J6 - DRV DRV linear regulator positive output
J7 - DRV/GND DRV linear regulator positive and negative terminals
J8 - GND Input power negative header
J9 - EXT TS/GND External thermistor terminal
J10 - GND SYS output negative header
J11 - SYS/GND SYS output positive and negative terminal
J12 - SYS SYS output positive header
J13 - BAT Battery positive header
J14 - BAT/GND Battery positive and negative header
J15 - USB-to-GPIO USB-to-GPIO box keyed connector
1.5 Test Points
Test Point Description
TP1 BAT
TP2 SW
TP3 GND
TP4 SYS
TP5 IN
TP6 STAT
TP7 GND
TP8 INT
TP9 TS
TP10 SCL
TP11 SDA
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1.6 Control and Key Parameters Setting
Jumper Description Default Factory Setting
BQ24260 only: Shorting jumper for USB data lines DM (D-) and DP (D+). When
JP1 shorted, USB input current limit defaults to 1.5 A. Otherwise, USB100 mode is SHORTED
selected.
JP2 Shorting jumper to connect DRV to anode of D1 STAT LED SHORTED
JP3 Shorting jumper to connect DRV to anode of D1 INT LED SHORTED
GATE = SYS: External PFET's gate tied to SYS and therefore disabled.
JP4 GATE = BGATE: External PFET's gate tied to BGATE pin and therefore controlled by GATE = BGATE
IC.
CD = LO: Charge disable low for normal operation
JP5 CD = LO
CD = HI: Charge disable high to disable the buck converter and enter Hi-Z mode
TS = SIM(INT): Connects a potentiometer to the TS pin so that the potentiometer can
simulator a thermistor (that is, an internal, on-board thermistor). The potentiometer has
been preset per R5 and R6 so that the TS voltage is 0.5 x V (DRV).
JP6 TS = SIM(INT)
TS = EXT: Connects the TS pin to an external thermistor through J9. The resistor
divider formed by R5 and R6 has been sized to accommodate a 10-kΩthermistor. If a
different thermistor is used, R5 and R6 must be resized.
bq24261 and bq24262 only
PSEL = LO: Input current limit is set to 1.5 A until changed by I2C.
JP7 PSEL = HI
PSEL = HI: For bq24261, input current limit is set to USB100 until changed by I2C. For
bq24262, input current limit is set to USB500 until changed by I2C.
1.7 Recommended Operating Conditions
Min Typ Max Unit
Supply voltage, VIN Input voltage from ac adapter (bq24260) 4.2 10.0 V
Supply voltage, VIN Input voltage from ac adapter (bq24261) 4.2 13.2
Supply voltage, VIN Input voltage from ac adapter (bq24262) 4.2 6.0 V
System voltage, VSYS Voltage output at SYS terminal ; depends on VBAT voltage 3.4 VBATR V
and status of VINDPM) EG +3%
Battery voltage, VBAT Voltage output at VBAT terminal (registers set via I2C 1.9 4.2 4.44 V
communication)
Supply current, IIN(MAX) Maximum input current from ac adapter input (registers set 0.1 2.5 A
via I2C communication)
Fast charge current, Battery charge current (registers set via I2C communication) 0.500 3.0 A
ICHRG(MAX)
Operating junction temperature range, TJ-40 125 °C
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2 Test Summary
This procedure describes one test configuration of the bq2426XEVM-611 evaluation board for bench
evaluation.
2.1 Definitions
The following naming conventions are followed.
VXXX : External voltage supply name (VADP, VBT, VSBT)
LOADW: External load name (LOAD1, LOAD2)
V(TPyyy): Voltage at internal test point TPyyy. For example, V(TP12) means the voltage at
TP12.
V(Jxx): Voltage at header Jxx
V(TP(XXX)): Voltage at test point XXX. For example, V(ACDET) means the voltage at the test
point which is marked as ACDET.
V(XXX, YYY): Voltage across point XXX and YYY
I(JXX(YYY)): Current going out from the YYY terminal of header XX
Jxx(BBB): Terminal or pin BBB of header xx
JPx ON : Internal jumper Jxx terminals are shorted
JPx OFF: Internal jumper Jxx terminals are open
JPx (-YY-) ON: Internal jumper Jxx adjacent terminals marked as YY are shorted
Measure: →A,B Check specified parameters A,B. If measured values are not within specified limits,
the unit under test has failed.
Observe →A,B Observe if A,B occur. If they do not occur, the unit under test has failed.
The assembly drawings (Section 4.2) show locations for jumpers, test points, and individual components.
2.2 Recommended Test Equipment
2.2.1 Power Supplies
1. Power supply #1 (PS #1) capable of supplying 6 V at 3 A is required.
2. If not using a battery as the load, then power supply #2 (PS #2) capable of supplying up to 5 V at 5 A
is required to power the circuit shown in Figure 2.
2.2.2 Load #1 Between BAT and GND
Testing with an actual battery is the best way to verify operation in the system. If a battery is not available,
then a circuit similar to the one shown in Figure 2 can simulate a battery when connected to a power
supply.
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Figure 2. BAT_Load (PR1010) Schematic
2.2.3 Load #2 Between SYS and GND
Although not required, a resistive load capable of sinking up to 3 A can be used.
2.2.4 Meters
Four equivalent voltage meters (VM #) and two equivalent current meters (CM #) are required. The current
meters must be able to measure 3-A current.
2.2.5 Computer
A computer with at least one USB port and a USB cable is required. The bq2416x evaluation software
must be properly installed.
2.2.6 HPA172 Communication Kit (USB to GPIO)
An HPA172 USB-to-I2C communication kit is required.
2.2.7 Software
Download BQ2416xSW.zip from the charger's product folder, unzip the file, and double-click on the
SETUP.EXE file. Follow the installation steps.
Because the bq24260 and bq24261 have the watchdog timers enabled, it is recommended that you set
the software's Reset Watchdog Timer to reset every 5 seconds. Otherwise, after 30 seconds of
operation, the IC enters Default mode. Note that the 27-minute safety timer is not reset by this function
and eventually times out if charging does not complete, unless the Safety Timer Time Limit is expanded
or disabled via the GUI. One way to reset the safety timer is to allow the 30-second watchdog timer to
expire. See Figure 3 in the data sheet (SLUSBA2) for more information about the timers.
Also, it is generally helpful to activate the Write On Change functions, in the upper left of the GUI window,
to ON. The Write On Change function writes any changes to the GUI's check boxes, drop-down boxes,
and registers to the IC. Otherwise, click the WRITE button to write changes to the software. It is
recommended to periodically click the READ button to find the IC's instantaneous status. Alternatively, the
AutoRead function can be activated to periodically update the GUI with the IC's status.
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To
Computer
USB port
USB Interface
Adapter
I/O
USB
Texas Instruments
© 2006
10-pin
Ribbon
Cable
To EVM
Test Summary www.ti.com
2.3 Recommended Test Equipment Setup
1. For all power connections, use short, twisted-pair wires of appropriate gauge wire for the amount of the
current.
2. Set PS #1 for 6-V, 3-A current limit and then turn off the supply.
3. If BAT_Load as shown in Figure 1 is used, connect PS #2 set to approximately 3.6 V to the input side
(PS #2±) of BAT_Load, then turn off PS #2.
4. Connect the output side of the battery or BAT_Load in series with the current meter (multimeter) #2
(CM #2) to J2 and J6 or J3 (BAT, GND). Ensure that a voltage meter is connected across J2 or TP3
and J6 or TP9 (BAT, GND).
5. Connect VM #3 across J10 or TP7 and J14 or TP9 (SYS, GND).
6. Connect VM #4 across J15 or TP5 and J14 or TP9 (DRV, GND).
7. Connect J17 to the HPA172 kit with the 10-pin ribbon cable. Connect the USB port of the HPA172 kit
to the USB port of the computer. The connections are shown in Figure 3.
Figure 3. Connections of HPA172 Kit
8. Ensure jumpers are at the default factory settings per Section 1.6.
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AVVM#2
CM#2
ICHRG
-
-+ +
VM#3
V
+
-
BAT_Load
PS#2
VM#4
V
+
-
Windows
PC
USB-TO-
GPIO
PS
#1
A
V
CM#1
IIN
+
-
VM#1
+
-
www.ti.com Test Summary
9. After the preceding steps have been performed, the test setup for bq2426XEVM-611 is configured as
shown in Figure 4.
Figure 4. Original Test Setup for bq24260, bq24261, bq24262 EVM
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10. Turn on the computer. Open the bq2426x evaluation software. The main window of the software is
shown in Figure 5.
Figure 5. Main Window of the bq2426xSW Evaluation Software
2.4 Recommended Test Procedure
It is best to evaluate the IC with a real battery attached to the BAT pin. If no battery is available, the
following test procedure, with explanation on how to simulate a battery with a second power supply and
load board previously presented, may be useful for evaluating the charger IC.
2.4.1 Charge Voltage and Current Regulation of IN in HOST mode
1. Ensure that the steps listed in Section 2.3 are followed.
2. Ensure that the shunts are installed to the default values per Section 1.6.
3. Connect the output of PS #1, with at least a 4-A current limit setting, in series with CM #1 to J1 as
shown in Figure 4.
4. Connect VM #1 across J4 and J3 or TP5 and/or TP7 (IN, GND).
5. Connect either a real single-cell lithium ion battery or battery simulator across J14 or J13/J5 (BAT,
GND) with CM #2 in series as shown in Figure 4. If using a battery simulator like the one shown in
Figure 2 and referred to as BAT_LOAD in Figure 4, configure PS #2 with at least 4-A current limit for
3.4 V.
6. Install VM #1 across J4 and J3 or TP5 and TP7 (IN and GND).
7. Install VM #2 across J13 and J5 or TP1 and TP7 (BAT and GND).
8. Install VM #3 across J12 and J10 or TP4 and TP7 (SYS and GND).
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9. VM #4 is optional.
10. Turn on PS #1 and PS #2, if used.
11. Software setup:
• Press the READ button to obtain the current settings.
• Set Write On Change to ON, if not already set.
• Set Reset Watchdog Timer to reset every 5 seconds.
• Uncheck Disable Charging, if checked.
• Check Enable STAT/INT Outputs.
• Set Battery Regulation Voltage to 4.20 V.
• Set Input Current Limit to 2.5 A.
• Set Charge Current to 2000 mA.
• Click the READ button at the top of the window and confirm that the previous settings remain.
12. Test the charge current regulation by adjusting the PS #1 power supply so that VM #1 still reads 5 V
and PS #2 so that the voltage measured by VM #2 is 3.6 V.
Measure on CM #2 →ICHRG = 2000 mA ±100 mA.
Measure on CM #1 →IIN < 1600 mA.
13. Test the input current limit by lowering the software's Input Current Limit setting to 900 mA then
readjusting PS #1 so that VM #1 reads 5 V and PS #2 reads 3.6 V.
Measure on CM #2 →ICHRG < 2000 mA.
Measure on CM #1 →IIN = 800 mA – 900 mA.
14. Test the minimum system voltage and DPPM by returning the software's Input Current Limit setting
to 2500 mA then lowering PS #2 until VM #2 reads 3.3 V. Add an external resistive or constant current
load across J13 and J5 that does not draw more than 2.5 A from SYS.
Measure on VM #3 →3.44 V – 3.55 V.
Measure on CM #2 →ICHRG = 2000 mA ±100 mA minus the load current on SYS.
15. Test the VINDPM function by removing the load on SYS, adjusting PS #1 so that VM #1 reads 5 V,
adjusting PS# 2 so that VM #2 reads 3.6 V and then lowering the current limit setting on PS #1 to
below the software's Charge Current setting.
Measure on VM #1 →VIN = software's V INDPM level (default of 4.2 V).
Measure on CM #2 →ICHRG < 2000 mA.
16. Test battery regulation and charge termination by returning the PS #1 current limit to 4-A and
confirming that the software's Enable Termination box is checked, then, slowly increase PS #2 until
VM #2 reaches 4.2 V.
Measure on CM #2 →ICHRG slowly tapers to the software's ITERM setting (default of 150 mA) and then
drops to zero.
Observe →LEDs turn off.
17. Test battery supplement mode by lowering PS #2 until VM #2 reads 3.6 V. Add an external resistive or
constant current load across J13 and J5 that draws more than 3 A from SYS.
Measure on VM #4 →3.6 V – IBATSUP × RDS(ON)(BATFET).
Measure on #2 →ICHRG = –IBATSUP.
18. Turn off PS #1 and PS #2.
11
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Printed-Circuit Board Layout Guideline www.ti.com
2.4.2 Helpful Hints
1. The leads and cables to the various power supplies have resistance. The current meters also have
series resistance. Therefore, voltmeters must be used to measure the voltage as close to the IC pins
as possible instead of relying on each supply's digital measurement.
2. When using a sourcemeter that can source and sink current as your battery simulator, it is highly
recommended to add a large (1000 µF+) capacitor at the EVM BAT and GND connectors in order to
prevent oscillations at the BAT pin due to mismatched impedances of the charger output and
sourcemeter input within their respective regulation loop bandwidths. Configuring the sourcemeter for
4-wire sensing eliminates the need for a separate voltmeter to measure the voltage at the BAT pin.
When using 4-wire sensing, always ensure that the sensing leads are connected first in order to
prevent accidental overvoltage by the power leads.
3. For precise measurements of charge current and battery regulation near termination, remove the
current meter in series with the battery or battery simulator. An alternate method for measuring charge
current is to either use an oscilloscope with hall effect current probe or place a 1% or better, thermally
capable (for example, 0.010 Ωin 1206 or larger footprint) resistor in series between the BAT pin and
battery and measure the voltage across that resistor.
3 Printed-Circuit Board Layout Guideline
Use the following guidelines for PCB layout:
1. To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND,
must be placed as close as possible to the IC.
2. Place 4.7-µF input capacitor as close to PMID pin and PGND pin as possible to make the high-
frequency current loop area as small as possible. Place 1-µF input capacitor GNDs as close to the
respective PMID capacitor GND and PGND pins as possible to minimize the ground difference
between the input and PMID.
3. The local bypass capacitor from SYS to GND must be connected between the SYS pin and PGND of
the IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and
back to the PGND pin.
4. Place all decoupling capacitors close to their respective IC pins and as close as possible to PGND (do
not place components such that routing interrupts power stage currents). All small control signals must
be routed away from the high-current paths.
5. The PCB must have a ground plane (return) connected directly to the return of all components through
vias (two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal
components). It is also recommended to put vias inside the PGND pads for the IC, if possible. A star
ground design approach is typically used to keep circuit block currents isolated (high-power/low-power
small-signal) which reduces noise-coupling and ground-bounce issues. A single ground plane for this
design gives good results. With this small layout and a single ground plane, no ground-bounce issue
exists, and having the components segregated minimizes coupling between signals.
6. The high-current charge paths into IN, USB, BAT, SYS, and from the SW pins must be sized
appropriately for the maximum charge current in order to avoid voltage drops in these traces. The
PGND pins must be connected to the ground plane to return current through the internal low-side FET.
7. For high-current applications, the balls for the power paths must be connected to as much copper in
the board as possible. This allows better thermal performance because the board conducts heat away
from the IC.
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www.ti.com Bill of Materials and Board Layout
4 Bill of Materials and Board Layout
4.1 Bill of Materials
Table 1 contains the bill of materials for this EVM.
Table 1. Bill of Materials - PWR611
-001 -002 -003 Designator Description Manufacturer PartNumber
1 1 1 !PCB Printed Circuit Board Any PWR611
1 1 1 C1 Capacitor, Ceramic, 25V, X5R, 20% TDK C1608X5R1E475M
1 1 1 C2 Capacitor, Ceramic, 6.3V, X5R, 10% TDK C1005X5R0J105K
1 1 1 C3 Capacitor, Ceramic, 25V, X5R, 10% TDK C1005X5R1E333K
1 1 1 C4 Capacitor, Ceramic, 6.3V, X5R, 10% TDK C1005X5R0J105K
1 1 1 C5 Capacitor, Ceramic, 10V, X5R, 20% TDK C1608X5R1A106M
0 0 0 C6 Capacitor, Ceramic Chip, Std Std
1 1 1 C7 Capacitor, Ceramic, 10V, X5R, 20% Taiyo Yuden LMK325BJ106MD-T
0 0 0 C8 Capacitor, Ceramic Chip STD STD
1 1 1 C9 Capacitor, Ceramic, 25V, X5R, 10% TDK C1608X5R1E105K080AC
1 1 1 D1 Diode, LED, Green, 2.1-V, 20-mA, 6-mcd Lite On LTST-C190GKT
1 1 1 D2 Diode, LED, Red, 2.1-V, 20-mA, 6-mcd Lite On LTST-C190CKT
1 1 1 J1 Terminal Block, 2-pin, 6-A, 3.5mm OST ED555/2DS
1 1 1 J10 Header, Male 2-pin, 100mil spacing, Sullins PEC02SAAN
1 1 1 J11 Terminal Block, 2-pin, 6-A, 3.5mm OST ED555/2DS
1 1 1 J12 Header, Male 2-pin, 100mil spacing, Sullins PEC02SAAN
1 1 1 J13 Header, Male 2-pin, 100mil spacing, Sullins PEC02SAAN
1 1 1 J14 Terminal Block, 2-pin, 6-A, 3.5mm OST ED555/2DS
1 1 1 J15 Connector, Male Straight 2x5 pin, 100mil spacing, 4 Wall 3M N2510-6002RB
1 1 1 J2 Connector, USB Micro, Type AB Hirose ZX62D-AB-5P8
1 1 1 J3 Header, Male 2-pin, 100mil spacing, Sullins PEC02SAAN
1 1 1 J4 Header, Male 2-pin, 100mil spacing, Sullins PEC02SAAN
1 1 1 J5 Header, Male 2-pin, 100mil spacing, Sullins PEC02SAAN
1 1 1 J6 Header, Male 2-pin, 100mil spacing, Sullins PEC02SAAN
1 1 1 J7 Terminal Block, 2-pin, 6-A, 3.5mm OST ED555/2DS
1 1 1 J8 Header, Male 2-pin, 100mil spacing, Sullins PEC02SAAN
1 1 1 J9 Terminal Block, 2-pin, 6-A, 3.5mm OST ED555/2DS
1 0 0 JP1 Header, Male 2-pin, 100mil spacing, Sullins PEC02SAAN
1 1 1 JP2 Header, Male 2-pin, 100mil spacing, Sullins PEC02SAAN
1 1 1 JP3 Header, Male 2-pin, 100mil spacing, Sullins PEC02SAAN
1 1 1 JP4 Header, Male 3-pin, 100mil spacing, Sullins PEC03SAAN
13
SLUUAV8A –February 2014–Revised August 2014 User's Guide for QFN Packaged bq24260, bq24261, and bq24262 3-A Battery
Charger Evaluation Module
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Table 1. Bill of Materials - PWR611 (continued)
-001 -002 -003 Designator Description Manufacturer PartNumber
1 1 1 JP5 Header, Male 3-pin, 100mil spacing, Sullins PEC03SAAN
1 1 1 JP6 Header, Male 3-pin, 100mil spacing, Sullins PEC03SAAN
0 1 1 JP7 Header, Male 3-pin, 100mil spacing, Sullins PEC03SAAN
1 1 1 L1 Inductor, IR=3.1A, ISAT=3.5A, 59 mΩtyp TDK SPM4012T-1R5M/
Inductor, IR=3.3A, ISAT=4.1A, 64 mΩtyp Toko Alt: FDSD0415-H-1R5M
Inductor, IR=3.0A, ISAT=4.0A, 55 mΩtyp Wurth Elektronik Alt:S13100073
1 1 1 Q1 MOSFET, PChan, -20V, 60A, 8.7 milliOhm TI CSD25401Q3
1 1 1 R1 Resistor, Chip, 1/16W, 1% Vishay CRCW0603200RFKEA
1 1 1 R2 Resistor, Chip, 1/16W, 1% Vishay CRCW0603200RFKEA
1 1 1 R3 Resistor, Chip, 1/16W, 5% Vishay CRCW06031K50FKEA
1 1 1 R4 Resistor, Chip, 1/16W, 5% Vishay CRCW06031K50FKEA
1 1 1 R5 Resistor, Chip, 1/16W, 1% Vishay CRCW04025K62FKED
1 1 1 R6 Resistor, Chip, 1/16W, 1% Vishay CRCW040212K4FKED
1 1 1 R7 Potentiometer, 3/8 Cermet, Single-Turn Bourns 3266W-1-503LF
1 1 1 R8 Resistor, Chip, 1/16W, 1% Vishay CRCW06031M00FKEA
1 0 0 R9 Resistor, Chip, 1/16W, 1% Vishay CRCW04020000Z0ED
1 0 0 SH-JP1 Shunt, 100mil, Gold plated, Black 3M 969102-0000-DA
1 1 1 SH-JP2 Shunt, 100mil, Gold plated, Black 3M 969102-0000-DA
1 1 1 SH-JP3 Shunt, 100mil, Gold plated, Black 3M 969102-0000-DA
1 1 1 SH-JP4 Shunt, 100mil, Gold plated, Black 3M 969102-0000-DA
1 1 1 SH-JP5 Shunt, 100mil, Gold plated, Black 3M 969102-0000-DA
1 1 1 SH-JP6 Shunt, 100mil, Gold plated, Black 3M 969102-0000-DA
0 1 1 SH-JP7 Shunt, 100mil, Gold plated, Black 3M 969102-0000-DA
1 1 1 TP1 Test Point, White, Thru Hole Color Keyed Keystone 5002
1 1 1 TP10 Test Point, White, Thru Hole Color Keyed Keystone 5002
1 1 1 TP11 Test Point, White, Thru Hole Color Keyed Keystone 5002
1 1 1 TP2 Test Point, White, Thru Hole Color Keyed Keystone 5002
1 1 1 TP3 Test Point, White, Thru Hole Color Keyed Keystone 5002
1 1 1 TP4 Test Point, White, Thru Hole Color Keyed Keystone 5002
1 1 1 TP5 Test Point, White, Thru Hole Color Keyed Keystone 5002
1 1 1 TP6 Test Point, White, Thru Hole Color Keyed Keystone 5002
1 1 1 TP7 Test Point, White, Thru Hole Color Keyed Keystone 5002
1 1 1 TP8 Test Point, White, Thru Hole Color Keyed Keystone 5002
1 1 1 TP9 Test Point, White, Thru Hole Color Keyed Keystone 5002
1 0 0 U1 3A, 30V, Host-Controlled Single-Input, Single Cell Switchmode Li-Ion Battery Charger with Texas Instruments BQ24260RGE
Power Path Management and USB-OTG Support, RGE0024H
0 1 0 U1 3A, 30V, Host-Controlled Single-Input, Single Cell Switchmode Li-Ion Battery Charger with Texas Instruments BQ24261RGE
Power Path Management and USB-OTG Support, RGE0024H
14 User's Guide for QFN Packaged bq24260, bq24261, and bq24262 3-A Battery SLUUAV8A –February 2014–Revised August 2014
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www.ti.com Bill of Materials and Board Layout
Table 1. Bill of Materials - PWR611 (continued)
-001 -002 -003 Designator Description Manufacturer PartNumber
0 0 1 U1 3A, 30V, Host-Controlled Single-Input, Single Cell Switchmode Li-Ion Battery Charger with Texas Instruments BQ24262RGE
Power Path Management and USB-OTG Support, RGE0024H
15
SLUUAV8A –February 2014–Revised August 2014 User's Guide for QFN Packaged bq24260, bq24261, and bq24262 3-A Battery
Charger Evaluation Module
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4.2 Board Layout
Figure 6 through Figure 10 illustrate the PCB layouts for this EVM.
Figure 6. Top Assembly Layer
16 User's Guide for QFN Packaged bq24260, bq24261, and bq24262 3-A SLUUAV8A –February 2014–Revised August 2014
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Figure 7. Top Layer
17
SLUUAV8A –February 2014–Revised August 2014 User's Guide for QFN Packaged bq24260, bq24261, and bq24262 3-A
Battery Charger Evaluation Module
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Figure 8. First Internal Layer
18 User's Guide for QFN Packaged bq24260, bq24261, and bq24262 3-A SLUUAV8A –February 2014–Revised August 2014
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Figure 9. Second Internal Layer
19
SLUUAV8A –February 2014–Revised August 2014 User's Guide for QFN Packaged bq24260, bq24261, and bq24262 3-A
Battery Charger Evaluation Module
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Revision History www.ti.com
Figure 10. Bottom Layer
Revision History
Changes from Original (February 2014) to A Revision .................................................................................................. Page
• Changed content in the bill of materials............................................................................................... 13
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
20 Revision History SLUUAV8A –February 2014–Revised August 2014
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